From 6bf9e23332bffc6362cb63f37957ac69e5a6ac96 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 7 Apr 2015 14:09:09 +0900 Subject: Makefile: remove extra ifdef/endif of top Makefile The GNU make's origin function know undefined variable well, so the outer ifdef/endif conditional checking is unneeded. >From `info make` documentation, origin will return `undefined' if VARIABLE was never defined. `command line' if VARIABLE was defined on the command line. ... Therefore, $(origin V) will get a value anyway, killing ifdef/endif is viable and safe. Furthermore, I've checked the minimal requirements from the top Makefile is GNU make 3.81, and that version of GNU make has support of origin function well already, so now it's safe to kill the outer conditional checking, without upgrading the minimal requirements. Signed-off-by: Cheng Renquan Signed-off-by: Sam Ravnborg [ Commit description is borrowed from Linux Kernel (commit b8b0618cf6fa) and adjusted for Buildroot ] Signed-off-by: Masahiro Yamada Acked-by: "Yann E. MORIN" Signed-off-by: Thomas Petazzoni --- Makefile | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'Makefile') diff --git a/Makefile b/Makefile index c691b577e..2ad88325e 100644 --- a/Makefile +++ b/Makefile @@ -184,10 +184,8 @@ endif # To put more focus on warnings, be less verbose as default # Use 'make V=1' to see the full commands -ifdef V - ifeq ("$(origin V)", "command line") - KBUILD_VERBOSE = $(V) - endif +ifeq ("$(origin V)", "command line") + KBUILD_VERBOSE = $(V) endif ifndef KBUILD_VERBOSE KBUILD_VERBOSE = 0 -- cgit v1.2.3