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<title>igt-gpu-tools.git/docs, branch vm-bind</title>
<subtitle>DRM IGT GPU Tools</subtitle>
<id>https://git.etezian.org/cgit.cgi/igt-gpu-tools.git/atom?h=vm-bind</id>
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<updated>2022-06-13T15:28:24+00:00</updated>
<entry>
<title>lib/i915_crc: Introduce crc32 on gpu for DG2</title>
<updated>2022-06-13T15:28:24+00:00</updated>
<author>
<name>Zbigniew Kempczyński</name>
<email>zbigniew.kempczynski@intel.com</email>
</author>
<published>2022-06-10T07:07:50+00:00</published>
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<id>urn:sha1:d79613643c640e348a7291fbab3bfdddd48d068c</id>
<content type='text'>
Adding crc32 calculation on gpu gives us new possibility to verify data
integrity without relying on trust cpu mapping is correct.

Patch introduces calculating crc32 on DG2 only. On older gens ALU
(MI_MATH) doesn't support bit-shifting instructions as well as multiply
or divide. Emulating n-bit shifts cost hundred of instructions with
predicated SRM (works on render engine only). Another limitation is lack
of indexed load / store. On DG2 we can use WPARID and CS_MI_ADDRESS_OFFSET
to achieve indexed operation on memory.

Due to performance reasons (cpu crc32 calculation even on WC memory is
still much faster than on gpu, also depends on calculated object memory
region) calculation will complete in reasonable of time only for few MiB.

v2: - use registers relative to engine to allow run on all engines (Chris)
    - use predication instead of memory access to get better performance
      (Chris)
    - add location where crc32 implementation comes from (Petri)

v4: - use common crc32 table from igt_crc
    - add docs

v5: - change BIT(n) to informative macros (Zbigniew)

Signed-off-by: Zbigniew Kempczyński &lt;zbigniew.kempczynski@intel.com&gt;
Acked-by: Petri Latvala &lt;petri.latvala@intel.com&gt;
</content>
</entry>
<entry>
<title>lib/igt_crc: Introduce common place for crc tables and functions</title>
<updated>2022-06-13T15:28:24+00:00</updated>
<author>
<name>Zbigniew Kempczyński</name>
<email>zbigniew.kempczynski@intel.com</email>
</author>
<published>2022-06-10T07:07:49+00:00</published>
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<id>urn:sha1:3844434ae2bc013857d1aa90d12875151689164e</id>
<content type='text'>
Add crc32 table for on-cpu crc calculation function. Other tables and
algorithms should be added here allowing reuse tables for in-gpu crc
calculation.

Signed-off-by: Zbigniew Kempczyński &lt;zbigniew.kempczynski@intel.com&gt;
Reviewed-by: Petri Latvala &lt;petri.latvala@intel.com&gt;
</content>
</entry>
<entry>
<title>tests/kms_chamelium: Check if port adapters are in use</title>
<updated>2022-05-25T09:52:51+00:00</updated>
<author>
<name>Ryszard Knop</name>
<email>ryszard.knop@intel.com</email>
</author>
<published>2022-05-20T10:39:45+00:00</published>
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<id>urn:sha1:1b5f7f139660ac27f3c8b4c4a2d23fdd9430ccab</id>
<content type='text'>
If a DUT has Chamelium ports connected via an adapter (for example, DP
on the Chamelium side -&gt; DP-HDMI adapter -&gt; HDMI on the DUT), this will
usually cause many tests to fail. If mismatching port types are found
on both sides, the tests will now be aborted with a warning.

This behavior can be overridden with a new AdapterAllowed config value,
which must be set in [Chamelium:PORT] blocks in .igtrc.

Signed-off-by: Ryszard Knop &lt;ryszard.knop@intel.com&gt;
Reviewed-by: Petri Latvala &lt;petri.latvala@intel.com&gt;
</content>
</entry>
<entry>
<title>docs/code_coverage.md: document the code coverage filter script</title>
<updated>2022-04-14T15:19:39+00:00</updated>
<author>
<name>Mauro Carvalho Chehab</name>
<email>mchehab@kernel.org</email>
</author>
<published>2022-04-14T12:24:57+00:00</published>
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<id>urn:sha1:fc8769fdd2e9ba8645ee92511a9ea513a3902a18</id>
<content type='text'>
Add documentation bits for the code_coverage_parse_info.

While here, also drop the extensions from the scripts that were renamed.

Reviewed-by: Ch Sai Gowtham &lt;sai.gowtham.ch@intel.com&gt;
Reviewed-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
</content>
</entry>
<entry>
<title>docs: add documentation for code coverage</title>
<updated>2022-03-21T16:34:59+00:00</updated>
<author>
<name>Mauro Carvalho Chehab</name>
<email>mchehab@kernel.org</email>
</author>
<published>2022-03-16T15:00:03+00:00</published>
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<id>urn:sha1:04d012b18355b53798af5a55a8915afb1a421bba</id>
<content type='text'>
Document the IGT runner features related to code coverage data capture.

Acked-by: Petri Latvala &lt;petri.latvala@intel.com&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
</content>
</entry>
<entry>
<title>lib/i915_blt: Add library for blitter</title>
<updated>2022-03-11T17:00:51+00:00</updated>
<author>
<name>Zbigniew Kempczyński</name>
<email>zbigniew.kempczynski@intel.com</email>
</author>
<published>2022-03-11T12:13:17+00:00</published>
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<id>urn:sha1:34dc3b8be67e798663bad882552b7d91df4cdc70</id>
<content type='text'>
Blitter commands became complicated thus manual bitshifting is error
prone and hard debugable - XY_BLOCK_COPY_BLT is the best example -
in extended version (for DG2+) it takes 20 dwords of command data.
To avoid mistakes and dozens of arguments for command library provides
input data in more structured form.

Currently supported commands:
- XY_BLOCK_COPY_BLT:
  a)  TGL/DG1 uses shorter version of command which doesn't support
      compression
  b)  DG2+ command is extended and supports compression
- XY_CTRL_SURF_COPY_BLT
- XY_FAST_COPY_BLT

Source, destination and batchbuffer are provided to blitter functions
as objects (structs). This increases readability and allows use same
object in many functions. Only drawback of such attitude is some fields
used in one function may be ignored in another. As an example is
blt_copy_object which contains a lot of information about gem object.
In block-copy all of data are used but in fast-copy only some of them
(fast-copy doesn't support compression).

v2-v3: address review comments (Kamil)

Signed-off-by: Zbigniew Kempczyński &lt;zbigniew.kempczynski@intel.com&gt;
Reviewed-by: Kamil Konieczny &lt;kamil.konieczny@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>lib/i915/gem_create: Introduce gem-pool bo cache</title>
<updated>2022-03-11T17:00:51+00:00</updated>
<author>
<name>Zbigniew Kempczyński</name>
<email>zbigniew.kempczynski@intel.com</email>
</author>
<published>2022-03-11T12:13:13+00:00</published>
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<id>urn:sha1:891f0126992812afdb72db8f4dc0bf675223d0cb</id>
<content type='text'>
Handling batchbuffers with softpin requires tracking its state otherwise
we can write to inflight batchbuffer and encounter gpu hang. Gem pool
adds such tracking (similar to libdrm bo cache) and provides free and
ready to use bo. If pool has no free bo new one is created what means pool
can be growing during test execution. When test completes freeing buffers
and memory is called from igt_core so no additional cleanup is necessary.

Signed-off-by: Zbigniew Kempczyński &lt;zbigniew.kempczynski@intel.com&gt;
Cc: Petri Latvala &lt;petri.latvala@intel.com&gt;
Cc: Kamil Konieczny &lt;kamil.konieczny@linux.intel.com&gt;
Reviewed-by: Kamil Konieczny &lt;kamil.konieczny@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>igt: Split out I/O helpers</title>
<updated>2021-12-07T22:06:42+00:00</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@chromium.org</email>
</author>
<published>2021-11-29T21:46:59+00:00</published>
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<id>urn:sha1:a59b00e4a10c12263e511d6fc2d3f3294527e9b8</id>
<content type='text'>
Split the readN()/writeN() helpers out into an igt_io module, so they
can be re-used by tests.

Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
</content>
</entry>
<entry>
<title>msm: Add helper library</title>
<updated>2021-09-09T05:27:14+00:00</updated>
<author>
<name>Rob Clark</name>
<email>robdclark@chromium.org</email>
</author>
<published>2021-08-31T16:17:15+00:00</published>
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<id>urn:sha1:c53c33433f84559bb3a993dc4fa5b4d2e3811cbe</id>
<content type='text'>
Handle some of the boilerplate for tests.

v2: fix comment, drop unnecessary drm_open_driver_render() error
    handling, docs fixes, drop igt_msm_pipe_get_param() (for now),
    handle NULL in destructors

Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Reviewed-by: Petri Latvala &lt;petri.latvala@intel.com&gt;
</content>
</entry>
<entry>
<title>lib: Add an intel_ctx wrapper struct and helpers (v6)</title>
<updated>2021-06-10T16:13:20+00:00</updated>
<author>
<name>Jason Ekstrand</name>
<email>jason@jlekstrand.net</email>
</author>
<published>2021-03-30T14:24:02+00:00</published>
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<id>urn:sha1:e0e03729a3955b92ee7bb146fd60c9ea32e1904e</id>
<content type='text'>
We're trying to clean up some of our technical debt in the i915 API.  In
particular, context mutability and unnecessary getparam().  There's
quite a bit of the introspection stuff that's not used by any userspace
other than IGT.  Most drivers don't care about fetching the set of
engines, for instance, because they don't forget about what set of
engines they asked for int the first place.

Unfortunately, IGT relies heavily on context introspection for just
about everything when it comes to multi-engine testing.  It also likes
to use ctx0 as temporary storage for whatever the current test config
is.  While effective at keeping IGC simple in some ways, this means
we're making heavy use of context mutability.  Also, passing data around
with in tests isn't really what contexts are for.

This patch adds a new intel_ctx_t struct which wraps a context and
remembers the full context configuration.  This will provide similar
ease-of-use without having use ctx0 as temporary storage.

v2 (Jason Ekstrand):
 - Make all intel_ctx_t's const

v3 (Jason Ekstrand):
 - Fix up the docs so they build properly

v4 (Jason Ekstrand):
 - Add an intel_ctx_create_for_engine helper

v5 (Zbigniew Kempczyński):
 - Use SPDX license identifiers
 - Document default context semantics

v6 (Ashutosh Dixit):
 - Fix SPDX in intel_ctx.h
 - Fix a typo in a comment

v6 (Jason Ekstrand):
 - Add documentation about num_engines to intel_ctx_cfg_t

Signed-off-by: Jason Ekstrand &lt;jason@jlekstrand.net&gt;
Reviewed-by: Zbigniew Kempczyński &lt;zbigniew.kempczynski@intel.com&gt;
</content>
</entry>
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