intel_reg_dumper: make Haswell dump useful

It was previously printing ironlake_debug_regs and haswell_debug_regs.
Since ironlake_debug_regs contains a lot of registers that don't exist
on Haswell, running intel_reg_dumper on Haswell caused "unclaimed
register" messages. Now I've copied the existing registers from
ironlake_debug_regs to haswell_debug_regs, so we won't print the
registers that don't exist anymore.

Also removed DP_TP_STATUS_A since it doesn't exist.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

2 files changed, 140 insertions, 7 deletions

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 99d97bb8..ead00a28 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -1106,6 +1106,14 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define BCLRPAT_C	0x62020
 #define VSYNCSHIFT_C	0x62028
 
+#define HTOTAL_EDP	0x6F000
+#define HBLANK_EDP	0x6F004
+#define HSYNC_EDP	0x6F008
+#define VTOTAL_EDP	0x6F00c
+#define VBLANK_EDP	0x6F010
+#define VSYNC_EDP	0x6F014
+#define VSYNCSHIFT_EDP	0x6F028
+
 #define PP_STATUS	0x61200
 # define PP_ON					(1 << 31)
 /**
@@ -2541,6 +2549,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define PIPEC_DP_LINK_M		0x72060
 #define PIPEC_DP_LINK_N		0x72064
 
+#define PIPEEDPCONF		0x7F008
+
 #define DSPACNTR		0x70180
 #define DSPBCNTR		0x71180
 #define DSPCCNTR		0x72180
@@ -3031,6 +3041,12 @@ typedef enum {
 #define PIPEC_LINK_M2		0x62048
 #define PIPEC_LINK_N2		0x6204c
 
+#define PIPEEDP_DATA_M1		0x6F030
+#define PIPEEDP_DATA_N1		0x6F034
+
+#define PIPEEDP_LINK_M1		0x6F040
+#define PIPEEDP_LINK_N1		0x6F044
+
 /* PIPECONF for pipe A/B addr is same */
 
 /* cusor A is only connected to pipe A,
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index b66a1ea2..26e4446a 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -1859,7 +1859,6 @@ static struct reg_debug haswell_debug_regs[] = {
 	DEFINEREG(DP_TP_CTL_E),
 
 	/* DP status */
-	DEFINEREG(DP_TP_STATUS_A),
 	DEFINEREG(DP_TP_STATUS_B),
 	DEFINEREG(DP_TP_STATUS_C),
 	DEFINEREG(DP_TP_STATUS_D),
@@ -1873,7 +1872,6 @@ static struct reg_debug haswell_debug_regs[] = {
 	DEFINEREG(DDI_BUF_CTL_E),
 
 	/* Clocks */
-	DEFINEREG(PIXCLK_GATE),
 	DEFINEREG(SPLL_CTL),
 	DEFINEREG(LCPLL_CTL),
 	DEFINEREG(WRPLL_CTL1),
@@ -1899,6 +1897,127 @@ static struct reg_debug haswell_debug_regs[] = {
 	/* Fuses */
 	DEFINEREG(SFUSE_STRAP),
 
+	/* Pipe A */
+	DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
+	DEFINEREG2(DSPACNTR, i830_debug_dspcntr),
+	DEFINEREG2(DSPASTRIDE, ironlake_debug_dspstride),
+	DEFINEREG(DSPASURF),
+	DEFINEREG2(DSPATILEOFF, i830_debug_xy),
+
+	/* Pipe B */
+	DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
+	DEFINEREG2(DSPBCNTR, i830_debug_dspcntr),
+	DEFINEREG2(DSPBSTRIDE, ironlake_debug_dspstride),
+	DEFINEREG(DSPBSURF),
+	DEFINEREG2(DSPBTILEOFF, i830_debug_xy),
+
+	/* Pipe C */
+	DEFINEREG2(PIPECSRC, i830_debug_yxminus1),
+	DEFINEREG2(DSPCCNTR, i830_debug_dspcntr),
+	DEFINEREG2(DSPCSTRIDE, ironlake_debug_dspstride),
+	DEFINEREG(DSPCSURF),
+	DEFINEREG2(DSPCTILEOFF, i830_debug_xy),
+
+	/* Transcoder A */
+	DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
+	DEFINEREG2(HTOTAL_A, i830_debug_hvtotal),
+	DEFINEREG2(HBLANK_A, i830_debug_hvsyncblank),
+	DEFINEREG2(HSYNC_A, i830_debug_hvsyncblank),
+	DEFINEREG2(VTOTAL_A, i830_debug_hvtotal),
+	DEFINEREG2(VBLANK_A, i830_debug_hvsyncblank),
+	DEFINEREG2(VSYNC_A, i830_debug_hvsyncblank),
+	DEFINEREG(VSYNCSHIFT_A),
+	DEFINEREG2(PIPEA_DATA_M1, ironlake_debug_m_tu),
+	DEFINEREG2(PIPEA_DATA_N1, ironlake_debug_n),
+	DEFINEREG2(PIPEA_LINK_M1, ironlake_debug_n),
+	DEFINEREG2(PIPEA_LINK_N1, ironlake_debug_n),
+
+	/* Transcoder B */
+	DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
+	DEFINEREG2(HTOTAL_B, i830_debug_hvtotal),
+	DEFINEREG2(HBLANK_B, i830_debug_hvsyncblank),
+	DEFINEREG2(HSYNC_B, i830_debug_hvsyncblank),
+	DEFINEREG2(VTOTAL_B, i830_debug_hvtotal),
+	DEFINEREG2(VBLANK_B, i830_debug_hvsyncblank),
+	DEFINEREG2(VSYNC_B, i830_debug_hvsyncblank),
+	DEFINEREG(VSYNCSHIFT_B),
+	DEFINEREG2(PIPEB_DATA_M1, ironlake_debug_m_tu),
+	DEFINEREG2(PIPEB_DATA_N1, ironlake_debug_n),
+	DEFINEREG2(PIPEB_LINK_M1, ironlake_debug_n),
+	DEFINEREG2(PIPEB_LINK_N1, ironlake_debug_n),
+
+	/* Transcoder C */
+	DEFINEREG2(PIPECCONF, i830_debug_pipeconf),
+	DEFINEREG2(HTOTAL_C, i830_debug_hvtotal),
+	DEFINEREG2(HBLANK_C, i830_debug_hvsyncblank),
+	DEFINEREG2(HSYNC_C, i830_debug_hvsyncblank),
+	DEFINEREG2(VTOTAL_C, i830_debug_hvtotal),
+	DEFINEREG2(VBLANK_C, i830_debug_hvsyncblank),
+	DEFINEREG2(VSYNC_C, i830_debug_hvsyncblank),
+	DEFINEREG(VSYNCSHIFT_C),
+	DEFINEREG2(PIPEC_DATA_M1, ironlake_debug_m_tu),
+	DEFINEREG2(PIPEC_DATA_N1, ironlake_debug_n),
+	DEFINEREG2(PIPEC_LINK_M1, ironlake_debug_n),
+	DEFINEREG2(PIPEC_LINK_N1, ironlake_debug_n),
+
+	/* Transcoder EDP */
+	DEFINEREG2(PIPEEDPCONF, i830_debug_pipeconf),
+	DEFINEREG2(HTOTAL_EDP, i830_debug_hvtotal),
+	DEFINEREG2(HBLANK_EDP, i830_debug_hvsyncblank),
+	DEFINEREG2(HSYNC_EDP, i830_debug_hvsyncblank),
+	DEFINEREG2(VTOTAL_EDP, i830_debug_hvtotal),
+	DEFINEREG2(VBLANK_EDP, i830_debug_hvsyncblank),
+	DEFINEREG2(VSYNC_EDP, i830_debug_hvsyncblank),
+	DEFINEREG(VSYNCSHIFT_EDP),
+	DEFINEREG2(PIPEEDP_DATA_M1, ironlake_debug_m_tu),
+	DEFINEREG2(PIPEEDP_DATA_N1, ironlake_debug_n),
+	DEFINEREG2(PIPEEDP_LINK_M1, ironlake_debug_n),
+	DEFINEREG2(PIPEEDP_LINK_N1, ironlake_debug_n),
+
+	/* Panel fitter */
+	DEFINEREG2(PFA_CTL_1, ironlake_debug_panel_fitting),
+	DEFINEREG2(PFA_WIN_POS, ironlake_debug_pf_win),
+	DEFINEREG2(PFA_WIN_SIZE, ironlake_debug_pf_win),
+
+	DEFINEREG2(PFB_CTL_1, ironlake_debug_panel_fitting),
+	DEFINEREG2(PFB_WIN_POS, ironlake_debug_pf_win),
+	DEFINEREG2(PFB_WIN_SIZE, ironlake_debug_pf_win),
+
+	DEFINEREG2(PFC_CTL_1, ironlake_debug_panel_fitting),
+	DEFINEREG2(PFC_WIN_POS, ironlake_debug_pf_win),
+	DEFINEREG2(PFC_WIN_SIZE, ironlake_debug_pf_win),
+
+	/* LPT */
+
+	DEFINEREG2(TRANS_HTOTAL_A, i830_debug_hvtotal),
+	DEFINEREG2(TRANS_HBLANK_A, i830_debug_hvsyncblank),
+	DEFINEREG2(TRANS_HSYNC_A, i830_debug_hvsyncblank),
+	DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
+	DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
+	DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
+	DEFINEREG(TRANS_VSYNCSHIFT_A),
+
+	DEFINEREG2(TRANSACONF, ironlake_debug_transconf),
+
+	DEFINEREG2(FDI_RXA_MISC, ironlake_debug_fdi_rx_misc),
+	DEFINEREG(FDI_RXA_TUSIZE1),
+	DEFINEREG(FDI_RXA_IIR),
+	DEFINEREG(FDI_RXA_IMR),
+
+	DEFINEREG(BLC_PWM_CPU_CTL2),
+	DEFINEREG(BLC_PWM_CPU_CTL),
+	DEFINEREG(BLC_PWM_PCH_CTL1),
+	DEFINEREG(BLC_PWM_PCH_CTL2),
+
+	DEFINEREG2(PCH_PP_STATUS, i830_debug_pp_status),
+	DEFINEREG2(PCH_PP_CONTROL, ilk_debug_pp_control),
+	DEFINEREG(PCH_PP_ON_DELAYS),
+	DEFINEREG(PCH_PP_OFF_DELAYS),
+	DEFINEREG(PCH_PP_DIVISOR),
+
+	DEFINEREG(PIXCLK_GATE),
+
+	DEFINEREG(RC6_RESIDENCY_TIME),
 };
 
 static struct reg_debug i945gm_mi_regs[] = {
@@ -2348,7 +2467,9 @@ int main(int argc, char** argv)
 			intel_check_pch();
 	}
 
-	if (HAS_PCH_SPLIT(devid)) {
+	if (IS_HASWELL(devid)) {
+		intel_dump_regs(haswell_debug_regs);
+	} else if (IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid)) {
 		intel_dump_regs(ironlake_debug_regs);
 	} else if (IS_945GM(devid)) {
 		intel_dump_regs(i945gm_mi_regs);
@@ -2362,10 +2483,6 @@ int main(int argc, char** argv)
 	if (IS_GEN6(devid) || IS_GEN7(devid))
 		intel_dump_regs(gen6_rp_debug_regs);
 
-	if (IS_HASWELL(devid))
-		intel_dump_regs(haswell_debug_regs);
-
-
 	intel_register_access_fini();
 	return 0;
 }