diff options
| author | Xiang, Haihao <haihao.xiang@intel.com> | 2013-02-22 11:14:13 +0800 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2013-11-06 09:39:41 -0800 |
| commit | 60c9b41e11bf4a3ea4935bd30f5c169ca24de06d (patch) | |
| tree | 452ad416b6e75fc21243e9709c839116d78af6fd | |
| parent | 3d8d094efec8cd6efbcead9c2fd54067e1a83223 (diff) | |
assembler/bdw: SEND instruction
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| -rw-r--r-- | assembler/gram.y | 19 |
1 files changed, 15 insertions, 4 deletions
diff --git a/assembler/gram.y b/assembler/gram.y index 6978de30..5671a0f4 100644 --- a/assembler/gram.y +++ b/assembler/gram.y @@ -1274,7 +1274,6 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget memset(&$$, 0, sizeof($$)); set_instruction_opcode(&$$, $2); - GEN(&$$)->header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ set_instruction_predicate(&$$, &$1); $4.width = $3; @@ -1297,7 +1296,13 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget set_instruction_src0(&$$, &src0, NULL); set_instruction_src1(&$$, &$7, NULL); - GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); + if (IS_GENp(8)) { + gen8_set_sfid(GEN8(&$$), $6 & EX_DESC_SFID_MASK); + gen8_set_eot(GEN8(&$$), !!($6 & EX_DESC_EOT_MASK)); + } else { + GEN(&$$)->header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ + GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); + } } | predicate sendop execsize dst sendleadreg sndopr directsrcoperand instoptions { @@ -1315,7 +1320,6 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget memset(&$$, 0, sizeof($$)); set_instruction_opcode(&$$, $2); - GEN(&$$)->header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ set_instruction_predicate(&$$, &$1); $4.width = $3; @@ -1338,7 +1342,14 @@ sendinstruction: predicate sendop execsize exp post_dst payload msgtarget set_instruction_src0(&$$, &src0, NULL); set_instruction_src1(&$$, &$7, &@7); - GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); + + if (IS_GENp(8)) { + gen8_set_sfid(GEN8(&$$), $6 & EX_DESC_SFID_MASK); + gen8_set_eot(GEN8(&$$), !!($6 & EX_DESC_EOT_MASK)); + } else { + GEN(&$$)->header.destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ + GEN(&$$)->bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); + } } | predicate sendop execsize dst sendleadreg payload sndopr imm32reg instoptions { |