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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2019-06-04 17:27:26 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-06-06 09:46:00 +0100 |
| commit | 3e2b20817b68ab41377c1b86207a1e7309fc3779 (patch) | |
| tree | c7604eb8bab43513dddfad1a577687b6783d11a9 | |
| parent | f354607cee4baef103f209cc1cc13bbab7def386 (diff) | |
i915/gem_ctx_shared: Fixup vecs0 mmio base for icl
I told vecs0 to use vecs1 registers...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Antonio Argenziano <antonio.argenziano@intel.com>
| -rw-r--r-- | tests/i915/gem_ctx_shared.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c index 67ecd095..06996454 100644 --- a/tests/i915/gem_ctx_shared.c +++ b/tests/i915/gem_ctx_shared.c @@ -544,9 +544,11 @@ static void independent(int i915, unsigned ring, unsigned flags) mmio_base = 0x22000; break; +#define GEN11_VECS0_BASE 0x1c8000 +#define GEN11_VECS1_BASE 0x1d8000 case I915_EXEC_VEBOX: if (intel_gen(intel_get_drm_devid(i915)) >= 11) - mmio_base = 0x1d8000; + mmio_base = GEN11_VECS0_BASE; else mmio_base = 0x1a000; break; |