diff options
author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2017-06-05 12:36:54 +0100 |
---|---|---|
committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2017-06-08 09:03:06 +0100 |
commit | 65173e1aaa909ddef37321170dfb33a2992ba6f4 (patch) | |
tree | 2a73e99b82f79f919552f11f16d8329c5075d048 /benchmarks/wsim/media_1n5_asy.wsim | |
parent | c14a2602a973da42d4cfcaed68dbf1c80d47945d (diff) |
gem_wsim: Asymmetrical 1-to-n workloads
Simulates a single decoder feeding multiple processing and
encoding pipelines.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Diffstat (limited to 'benchmarks/wsim/media_1n5_asy.wsim')
-rw-r--r-- | benchmarks/wsim/media_1n5_asy.wsim | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/benchmarks/wsim/media_1n5_asy.wsim b/benchmarks/wsim/media_1n5_asy.wsim new file mode 100644 index 00000000..78bb4a86 --- /dev/null +++ b/benchmarks/wsim/media_1n5_asy.wsim @@ -0,0 +1,21 @@ +1.VCS.12000-15000.0.0 +2.RCS.2000-3000.-1.0 +3.RCS.500-900.-1.0 +3.RCS.8000-10000.0.0 +3.VCS.1500-2500.-1.0 +4.RCS.2000-4000.-5.0 +5.RCS.1000-1200.-1.0 +5.RCS.6000-8000.0.0 +5.VCS.6000-8000.-1.0 +6.RCS.1000-2200.-9.0 +7.RCS.1000-1400.-1.0 +7.RCS.10000-12000.0.0 +7.VCS.2500-3500.-1.0 +8.RCS.300-600.-13.0 +9.RCS.600-1200.-1.0 +9.RCS.8000-10000.0.0 +9.VCS.8000-10000.-1.0 +10.RCS.800-1200.-17.0 +11.RCS.1000-1200.-1.0 +11.RCS.7000-10000.0.0 +11.VCS.4500-5500.-1.1 |