diff options
| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2018-10-04 16:55:00 +0100 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2019-05-22 09:52:21 +0100 |
| commit | 4a2583fc2e55ae23bab265fc0390d48d35b89bad (patch) | |
| tree | 504b75a00663f862948c8952059d64e210efee42 /benchmarks | |
| parent | a392abd96a78ac6d5faf6c1ab96e4df2f1f20282 (diff) | |
gem_wsim: Submit fence support
Add support for submit fences in a way similar to how normal input fences
are handled. Eg:
1.RCS.500-1000.0.0
1.VCS1.3000.s-1.0
1.VCS2.3000.s-2.0
Submit fences are signalled when the originating request enters the
submission backend.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'benchmarks')
| -rw-r--r-- | benchmarks/gem_wsim.c | 20 | ||||
| -rw-r--r-- | benchmarks/wsim/README | 17 |
2 files changed, 33 insertions, 4 deletions
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c index 6c9eb1e2..464314c0 100644 --- a/benchmarks/gem_wsim.c +++ b/benchmarks/gem_wsim.c @@ -87,6 +87,7 @@ enum w_type struct deps { int nr; + bool submit_fence; int *list; }; @@ -253,17 +254,23 @@ parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) w->data_deps.list == w->fence_deps.list); while ((token = strtok_r(tstart, "/", &tctx)) != NULL) { + bool submit_fence = false; char *str = token; struct deps *deps; int dep; tstart = NULL; - if (strlen(token) > 1 && token[0] == 'f') { + if (str[0] == '-' || (str[0] >= '0' && str[0] <= '9')) { + deps = &w->data_deps; + } else { + if (str[0] == 's') + submit_fence = true; + else if (str[0] != 'f') + return -1; + deps = &w->fence_deps; str++; - } else { - deps = &w->data_deps; } dep = atoi(str); @@ -281,6 +288,7 @@ parse_dependencies(unsigned int nr_steps, struct w_step *w, char *_desc) sizeof(*deps->list) * deps->nr); igt_assert(deps->list); deps->list[deps->nr - 1] = dep; + deps->submit_fence = submit_fence; } } @@ -1944,7 +1952,11 @@ do_eb(struct workload *wrk, struct w_step *w, enum intel_engine_id engine, igt_assert(tgt >= 0 && tgt < w->idx); igt_assert(wrk->steps[tgt].emit_fence > 0); - w->eb.flags |= I915_EXEC_FENCE_IN; + if (w->fence_deps.submit_fence) + w->eb.flags |= I915_EXEC_FENCE_SUBMIT; + else + w->eb.flags |= I915_EXEC_FENCE_IN; + w->eb.rsvd2 = wrk->steps[tgt].emit_fence; } diff --git a/benchmarks/wsim/README b/benchmarks/wsim/README index 205cd6c9..4786f116 100644 --- a/benchmarks/wsim/README +++ b/benchmarks/wsim/README @@ -114,6 +114,23 @@ runnable. When the second RCS batch completes the standalone fence is signaled which allows the two VCS batches to be executed. Finally we wait until the both VCS batches have completed before starting the (optional) next iteration. +Submit fences +------------- + +Submit fences are a type of input fence which are signalled when the originating +batch buffer is submitted to the GPU. (In contrary to normal sync fences, which +are signalled when completed.) + +Submit fences have the identical syntax as the sync fences with the lower-case +'s' being used to select them. Eg: + + 1.RCS.500-1000.0.0 + 1.VCS1.3000.s-1.0 + 1.VCS2.3000.s-2.0 + +Here VCS1 and VCS2 batches will only be submitted for executing once the RCS +batch enters the GPU. + Context priority ---------------- |