diff options
author | Jeevan B <jeevan.b@intel.com> | 2022-05-23 17:14:19 +0530 |
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committer | Swati Sharma <swati2.sharma@intel.com> | 2022-05-25 12:13:15 +0530 |
commit | ba0d294b3e0a8c14380a3c9aec49d9dbaa4c1b2a (patch) | |
tree | a1103898496d99d2fb5e066be14d16cfb0fce632 /include/drm-uapi/drm_fourcc.h | |
parent | 4ce82dc0eeb65974c383e5d1f8f0820174b4e9bb (diff) |
drm/fourcc: Import drm_fourcc header from 9035039e1ed69
commit 9035039e1ed691cd893777a42e048003a2f349d6
Author: Mika Kahola <mika.kahola@intel.com>
Date: Mon Apr 11 17:34:04 2022 +0300
drm/fourcc: Introduce format modifier for DG2 clear color
Signed-off-by: Jeevan B <jeevan.b@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Diffstat (limited to 'include/drm-uapi/drm_fourcc.h')
-rw-r--r-- | include/drm-uapi/drm_fourcc.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h index d8f7cad9..78bebdea 100644 --- a/include/drm-uapi/drm_fourcc.h +++ b/include/drm-uapi/drm_fourcc.h @@ -584,6 +584,42 @@ extern "C" { #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9) /* + * Intel color control surfaces (CCS) for DG2 render compression. + * + * The main surface is Tile 4 and at plane index 0. The CCS data is stored + * outside of the GEM object in a reserved memory area dedicated for the + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The + * main surface pitch is required to be a multiple of four Tile 4 widths. + */ +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10) + +/* + * Intel color control surfaces (CCS) for DG2 media compression. + * + * The main surface is Tile 4 and at plane index 0. For semi-planar formats + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices + * 0 and 1, respectively. The CCS for all planes are stored outside of the + * GEM object in a reserved memory area dedicated for the storage of the + * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface + * pitch is required to be a multiple of four Tile 4 widths. + */ +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11) + +/* + * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression. + * + * The main surface is Tile 4 and at plane index 0. The CCS data is stored + * outside of the GEM object in a reserved memory area dedicated for the + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The + * main surface pitch is required to be a multiple of four Tile 4 widths. The + * clear color is stored at plane index 1 and the pitch should be ignored. The + * format of the 256 bits of clear color data matches the one used for the + * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description + * for details. + */ +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12) + +/* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * * Macroblocks are laid in a Z-shape, and each pixel data is following the |