diff options
| author | Imre Deak <imre.deak@intel.com> | 2021-10-26 20:41:25 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2021-11-02 18:00:43 +0200 |
| commit | bd361e81d653093b05821127296a843accfa58d4 (patch) | |
| tree | 8eb771631abe09d1e8c3dd8e2bb9959179b4290c /lib/igt_fb.c | |
| parent | 14a20fb2bbf51c40e178e4435a739c99b48529f3 (diff) | |
lib/igt_fb/tgl+: Remove CCS FB 4 tile height alignment restriction
The spec is somewhat unclear about this and suggests a 4x4 tile layout
on the main surface of TGL+ CCS FBs. So far IGT ensured that the height
of the main surface is 4 tiles aligned accordingly. However, the layout
of tiles is just the usual Y-tiled one where consecutive tiles in memory
order fill one full tile-row at a time, continuing with the next
tile-row afterwards. Perhaps the spec referred to the layout where CCS
cachelines mapped to the main surface in the "vertical" cacheline-pair
mode. However up until ADLP the horizontal cacheline-pair mode is used,
where consecutive CCS cachelines in memory order map to consecutive main
surface tiles mapping one full tile-row first and then continuing with
the next tile-row.
Accordingly we don't need to align the surface height to 4 tiles, remove
this restriction.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Diffstat (limited to 'lib/igt_fb.c')
| -rw-r--r-- | lib/igt_fb.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 4d961270..67e63d48 100644 --- a/lib/igt_fb.c +++ b/lib/igt_fb.c @@ -670,7 +670,7 @@ static unsigned fb_plane_height(const struct igt_fb *fb, int plane) if (ccs_to_main_plane(fb, plane)) height = DIV_ROUND_UP(height, format->vsub); - return DIV_ROUND_UP(height, 128) * 4; + return DIV_ROUND_UP(height, 32); } else if (is_ccs_plane(fb, plane)) { return DIV_ROUND_UP(fb->height, 512) * 32; } @@ -838,10 +838,6 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane) igt_get_fb_tile_size(fb->fd, fb->modifier, fb->plane_bpp[plane], &tile_width, &tile_height); - /* A main surface using a CCS AUX surface must be 4x4 tiles aligned. */ - if (is_gen12_ccs_modifier(fb->modifier)) - tile_height *= 4; - size = (uint64_t)fb->strides[plane] * ALIGN(fb->plane_height[plane], tile_height); |