diff options
| author | Jeevan B <jeevan.b@intel.com> | 2022-03-02 20:09:16 +0530 |
|---|---|---|
| committer | Kunal Joshi <kunal1.joshi@intel.com> | 2022-03-09 11:16:34 +0530 |
| commit | ff9b8f21ce93309ed516e2bab2833985abf0de19 (patch) | |
| tree | d867fb65a1bd1133a80ebaf61fcfcbb5559971dc /lib/intel_batchbuffer.h | |
| parent | 534d00d3ffe1e1f592ba5772a763893d80db1d1e (diff) | |
igt/lib: Add tile 4(F-tile) format support
Introduce support for the new Tile4 format, which is
4K column-major tiles consisting of 64B row-major subtiles,
with same base structure as Y Tile(16B OWords * 4)
v2: place I915_TILING_4 correctly.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Diffstat (limited to 'lib/intel_batchbuffer.h')
| -rw-r--r-- | lib/intel_batchbuffer.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index a488f9cf..75d41ea3 100644 --- a/lib/intel_batchbuffer.h +++ b/lib/intel_batchbuffer.h @@ -202,7 +202,7 @@ void intel_copy_bo(struct intel_batchbuffer *batch, long int size); /* - * Yf/Ys tiling + * Yf/Ys/4 tiling * * Tiling mode in the I915_TILING_... namespace for new tiling modes which are * defined in the kernel. (They are not fenceable so the kernel does not need @@ -210,8 +210,9 @@ void intel_copy_bo(struct intel_batchbuffer *batch, * * They are to be used the the blitting routines below. */ -#define I915_TILING_Yf 3 -#define I915_TILING_Ys 4 +#define I915_TILING_4 (I915_TILING_LAST + 1) +#define I915_TILING_Yf (I915_TILING_LAST + 2) +#define I915_TILING_Ys (I915_TILING_LAST + 3) enum i915_compression { I915_COMPRESSION_NONE, |