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authorImre Deak <imre.deak@intel.com>2019-11-29 12:38:41 +0200
committerImre Deak <imre.deak@intel.com>2019-12-09 10:29:39 +0200
commitd999a7c546764cd6c84efd3e55583b69a4d82e9f (patch)
tree771480e582feee5b8ce9b6280652810501953bae /lib/intel_reg.h
parentf36328e7ca04833aad3589ca3c5572aea6ce20c5 (diff)
lib/intel_aux_pgtable: Set MMIO remap for write the AUX pagedir reg
We're only using the first instance of the render engine, but the standard way on GEN12 to read/write engine registers is to depend on the MMIO remapping to select the proper instance based on which command streamer the read/write instruction was run from. Enable the MMIO remapping to align with the standard way to do reg read/writes. Cc: Mika Kahola <mika.kahola@intel.com> Cc: Brian Welty <brian.welty@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Diffstat (limited to 'lib/intel_reg.h')
-rw-r--r--lib/intel_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 96236828..cabfc879 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2572,6 +2572,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_LOAD_SCAN_LINES_INCL (0x12<<23)
#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
#define MI_LOAD_REGISTER_MEM_GEN8 ((0x29 << 23) | (4 - 2))
+#define MI_MMIO_REMAP_ENABLE_GEN12 (1 << 17)
/* Flush */
#define MI_FLUSH (0x04<<23)