diff options
| author | David Zhang <dingchen.zhang@amd.com> | 2022-03-12 00:29:10 -0500 |
|---|---|---|
| committer | Aurabindo Pillai <aurabindo.pillai@amd.com> | 2022-03-16 15:49:16 -0400 |
| commit | f3df40281d93d5a63ee98fa30e90852d780673c9 (patch) | |
| tree | 8b0430360e561a025d0ddc61c5fb4d4f52a332dd /lib | |
| parent | bc1be26e0f31e4da9e897ed05693b9cea7e1ae83 (diff) | |
tests/amdgpu/amd_psr: add PSR-SU MPO subtest case
[why]
We need a test case to imitate the multiplane overlay (MPO) video
playback use case and check PSR-SU enablement during test run.
[how]
The test run only works for PSR-SU capable sink device and skip for
any non-eDP or non-PSR-SU connector or kernel driver not supporting
PSR-SU feature.
To emulate the video playback and MPO scenario, we use overlay plane
w/ size of addressable and primary plane w/ size of quater of overlay
acting as video playback region.
Create couple of framebuffers w/ size of primary plane and with
the pattern of vertical color strip on different position on the
FB. During test run, we flip the primary framebuffer and expect the
visual effect of moving strip within the region of primary plane
acting as video playback. The primary plane during test run is not
moving position or resizing.
changes in v3
----------------
* make the indentation consistent to use tabs
* newline after for loop for readability
Cc: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Leo Li <sunpeng.li@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: David Zhang <dingchen.zhang@amd.com>
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/igt_amd.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/lib/igt_amd.h b/lib/igt_amd.h index f87c1991..e4e12ce5 100644 --- a/lib/igt_amd.h +++ b/lib/igt_amd.h @@ -90,6 +90,31 @@ enum dc_link_training_type { LINK_TRAINING_NO_PATTERN }; +/* + * enumeration of PSR STATE below should be aligned to the upstreamed + * amdgpu kernel driver 'enum dc_psr_state' in dc_type.h + */ +enum amdgpu_psr_state { + PSR_STATE0 = 0x0, + PSR_STATE1, + PSR_STATE1a, + PSR_STATE2, + PSR_STATE2a, + PSR_STATE2b, + PSR_STATE3, + PSR_STATE3Init, + PSR_STATE4, + PSR_STATE4a, + PSR_STATE4b, + PSR_STATE4c, + PSR_STATE4d, + PSR_STATE5, + PSR_STATE5a, + PSR_STATE5b, + PSR_STATE5c, + PSR_STATE_INVALID = 0xFF +}; + uint32_t igt_amd_create_bo(int fd, uint64_t size); void *igt_amd_mmap_bo(int fd, uint32_t handle, uint64_t size, int prot); unsigned int igt_amd_compute_offset(unsigned int* swizzle_pattern, |