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author | Kamil Konieczny <kamil.konieczny@linux.intel.com> | 2022-03-31 18:34:29 +0200 |
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committer | Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> | 2022-04-01 08:17:45 +0200 |
commit | 1420324ea8a2b77706dd9c999b8730c9041bf217 (patch) | |
tree | d64cd21996429e5fd16fae6c9396f8dcf2053fff /scripts/code_cov_gather_on_test.py | |
parent | ee9ef376a054818cefcfc1d5701760995e1f0c39 (diff) |
tests/i915/gem_concurrent_all: Add no-reloc capability
Add noreloc mode for GPU gens without relocations. Also
while at this, add some caching for required properties.
Change also snoop function so it will work on DG1.
Tested with ./gem_concurrent_blit --run '4KiB-tiny-gpu-*'
and 256KiB with modified drm-tip to allow softpinning and
second run with relocs.
v9: restore empty newlines which where added/removed, use
CANONICAL for high bits of address in butchbuffer
v8: In main fixture, first try to open allocator should be done
with get_simple_h2l_ahnd so only on no-relocs gens we will
later use intel_allocator_open_full function (Zbigniew).
v7: rebase, cleanup bit17 caching (Zbigniew comments)
v6: correct comment, rewrite bit17 caching (Zbigniew)
v5: rebase, fix caching in bit17_require, changes according
to Zbigniew review: simplify cache of !gem_has_llc, drop
multiprocess start/stop, use ALLOC_STRATEGY_HIGH_TO_LOW,
correct offset and flags
v4: corrected alloc_open and first ahnd setting
Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Diffstat (limited to 'scripts/code_cov_gather_on_test.py')
0 files changed, 0 insertions, 0 deletions