summaryrefslogtreecommitdiff
path: root/tests/gem_tiled_pread_pwrite.c
diff options
context:
space:
mode:
authorDamien Lespiau <damien.lespiau@intel.com>2013-07-18 12:23:49 +0100
committerDamien Lespiau <damien.lespiau@intel.com>2013-07-18 16:16:19 +0100
commit161e610765b0b590a93c5a69468bc75f726c3f1b (patch)
tree77fe521f1291ac7d2649ccbff0e58da42a51b85d /tests/gem_tiled_pread_pwrite.c
parent00ab9a1313997f6292f064989b2c295d3fb2903b (diff)
tests: Add some tiled tests to the runs on simulation
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Diffstat (limited to 'tests/gem_tiled_pread_pwrite.c')
-rw-r--r--tests/gem_tiled_pread_pwrite.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/gem_tiled_pread_pwrite.c b/tests/gem_tiled_pread_pwrite.c
index 0eb70982..18a593a3 100644
--- a/tests/gem_tiled_pread_pwrite.c
+++ b/tests/gem_tiled_pread_pwrite.c
@@ -123,10 +123,8 @@ main(int argc, char **argv)
uint32_t handle, handle_target;
int count;
- drmtest_skip_on_simulation();
-
fd = drm_open_any();
- count = intel_get_total_ram_mb() * 9 / 10;
+ count = SLOW_QUICK(intel_get_total_ram_mb() * 9 / 10, 8) ;
for (i = 0; i < count/2; i++) {
current_tiling_mode = I915_TILING_X;