diff options
| author | Matthew Brost <matthew.brost@intel.com> | 2021-10-05 09:47:45 -0700 |
|---|---|---|
| committer | Ashutosh Dixit <ashutosh.dixit@intel.com> | 2021-11-11 08:43:02 -0800 |
| commit | a37519a6dfe3e75a8d776c73bb69dee85de69847 (patch) | |
| tree | 67f902639edb4abd6609062b82c1626424e89c3b /tests/i915/gem_ctx_shared.c | |
| parent | 5f856084c0f8b2edbfd01e115ab341da7a1b27a6 (diff) | |
i915/gem_ctx_shared: Make gem_ctx_shared understand static priority mapping
The i915 currently has 2k visible priority levels which are currently
unique. This is changing to statically map these 2k levels into 3
buckets:
low: < 0
mid: 0
high: > 0
Update gem_ctx_shared to understand this. This entails updating
promotion test to use 3 levels that will map into different buckets and
also add bit of delay after releasing a cork beforing completing the
spinners to give time to the i915 schedule to process the fence and
release and queue the requests.
v2: Add a delay between starting releasing spinner and cork in
promotion
v3:
(Daniele)
- Always add delay, update commit message
v4:
(Tvrtko)
- Reduce sleep period
(Daniele)
- Add comment in code by sleep
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Diffstat (limited to 'tests/i915/gem_ctx_shared.c')
| -rw-r--r-- | tests/i915/gem_ctx_shared.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/tests/i915/gem_ctx_shared.c b/tests/i915/gem_ctx_shared.c index 2f7ee69b..37444185 100644 --- a/tests/i915/gem_ctx_shared.c +++ b/tests/i915/gem_ctx_shared.c @@ -624,6 +624,9 @@ static void unplug_show_queue(int i915, struct igt_cork *c, uint64_t ahnd, igt_cork_unplug(c); /* batches will now be queued on the engine */ igt_debugfs_dump(i915, "i915_engine_info"); + /* give time to the kernel to complete the queueing */ + usleep(25000); + for (int n = 0; n < ARRAY_SIZE(spin); n++) { ahnd = spin[n]->ahnd; igt_spin_free(i915, spin[n]); @@ -832,10 +835,10 @@ static void promotion(int i915, const intel_ctx_cfg_t *cfg, unsigned ring) gem_context_set_priority(i915, ctx[LO]->id, MIN_PRIO); ctx[HI] = intel_ctx_create(i915, &q_cfg); - gem_context_set_priority(i915, ctx[HI]->id, 0); + gem_context_set_priority(i915, ctx[HI]->id, MAX_PRIO); ctx[NOISE] = intel_ctx_create(i915, &q_cfg); - gem_context_set_priority(i915, ctx[NOISE]->id, MIN_PRIO/2); + gem_context_set_priority(i915, ctx[NOISE]->id, 0); result = gem_create(i915, 4096); result_offset = get_offset(ahnd, result, 4096, 0); |