diff options
author | Jessica Zhang <quic_jesszhan@quicinc.com> | 2022-04-21 10:28:58 -0700 |
---|---|---|
committer | Abhinav Kumar <quic_abhinavk@quicinc.com> | 2022-04-25 11:50:49 -0700 |
commit | c133e54369ea4d4fcb56df659f07c74952e69ab8 (patch) | |
tree | afff1eec0fb53edeec147cb386de3c451662ed73 /tests/msm | |
parent | cbe10bd742faf5e4f6fdec9be8a75365d1319a88 (diff) |
meson: Move MSM-specific tests to their own subdirectory
Move all custom MSM tests to their own subdirectory and have them
installed in an msm/ subdirectory
Changes from v1:
- Removed extra whitespace
- Moved meson build commands for msm tests from tests/msm/meson.build
to tests/meson.build
Changes from v2:
- Removed unused variables
Acked-by: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Diffstat (limited to 'tests/msm')
-rw-r--r-- | tests/msm/msm_mapping.c | 257 | ||||
-rw-r--r-- | tests/msm/msm_recovery.c | 174 | ||||
-rw-r--r-- | tests/msm/msm_submit.c | 194 |
3 files changed, 625 insertions, 0 deletions
diff --git a/tests/msm/msm_mapping.c b/tests/msm/msm_mapping.c new file mode 100644 index 00000000..e1474f9f --- /dev/null +++ b/tests/msm/msm_mapping.c @@ -0,0 +1,257 @@ +/* + * Copyright © 2021 Google, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include <ctype.h> +#include <fcntl.h> +#include <glob.h> +#include <string.h> +#include <sys/poll.h> +#include <sys/stat.h> + +#include "igt.h" +#include "igt_msm.h" +#include "igt_io.h" + +/* + * Tests to ensure various kernel controlled buffers are mapped with the + * appropriate permissions (either read-only or not-accessible to userspace + * controlled cmdstream) + */ + +/* + * Helper to get and clear devcore dumps + */ + +static char * +get_and_clear_devcore(void) +{ + glob_t glob_buf = {0}; + char *buf = NULL; + int ret, fd; + + ret = glob("/sys/class/devcoredump/devcd*/data", GLOB_NOSORT, NULL, &glob_buf); + if ((ret == GLOB_NOMATCH) || !glob_buf.gl_pathc) + return NULL; + + fd = open(glob_buf.gl_pathv[0], O_RDWR); + + if (fd >= 0) { + /* We don't need to read the entire devcore, the first bit is + * sufficient for our purposes: + */ + buf = calloc(1, 0x1000); + igt_readn(fd, buf, 0x1000); + + /* Clear the devcore: */ + igt_writen(fd, "1", 1); + } + + globfree(&glob_buf); + + return buf; +} + +/* + * Helper to find named buffer address + */ + +static const char * +get_line(char **buf) +{ + char *ret, *eol; + + ret = *buf; + eol = strstr(*buf, "\n"); + + if (!eol) { + /* could be last line in file: */ + *buf = NULL; + return ret; + } + + *eol = '\0'; + *buf += 1 + strlen(ret); + + return ret; +} + +static bool +endswith(const char *str, const char *end) +{ + char *p = strstr(str, end); + + /* Trim trailing whitespace: */ + if (p) { + char *c = p; + while (c) { + if (isspace(*c)) { + *c = '\0'; + break; + } + c++; + } + } + + return p && (strlen(p) == strlen(end)); +} + +static uint64_t +get_bo_addr(int drm_fd, const char *name) +{ + char buf[0x4000]; + char *p = buf; + + igt_debugfs_read(drm_fd, "gem", buf); + + /* NOTE: the contents of the debugfs file look like: + * + * flags id ref offset kaddr size madv name + * 00040000: I 0 ( 1) 00000000 ffffffc0104b9000 00004096 memptrs + * vmas: [gpu: aspace=ffffff808bf03e00, 1000000000000,mapped,inuse=1] + * 00020002: I 0 ( 1) 00000000 ffffffc012001000 00032768 ring0 + * vmas: [gpu: aspace=ffffff808bf03e00, 1000000001000,mapped,inuse=1] + * + * There can be potentially multiple vma's per bo, listed on the lines + * following the line for the buffer (which ends in the buffer name), + * but this should not be the case for any kernel controlled buffers. + */ + + while (*p) { + const char *line = get_line(&p); + + if (endswith(line, name)) { + uint64_t addr, dummy; + int ret; + + line = get_line(&p); + + igt_fail_on(!line); + + ret = sscanf(line, " vmas: [gpu: aspace=%"PRIx64", %"PRIx64",mapped,inuse=1]", + &dummy, &addr); + igt_fail_on(ret != 2); + + return addr; + } + } + + return 0; +} + +/* + * Helper for testing access to the named buffer + */ +static void +do_mapping_test(struct msm_pipe *pipe, const char *buffername, bool write) +{ + struct msm_bo *scratch_bo = NULL; + struct msm_cmd *cmd; + char *devcore, *s; + uint64_t addr, fault_addr; + int fence_fd, ret; + + /* Clear any existing devcore's: */ + while ((devcore = get_and_clear_devcore())) { + free(devcore); + } + + addr = get_bo_addr(pipe->dev->fd, buffername); + igt_skip_on(addr == 0); + + cmd = igt_msm_cmd_new(pipe, 0x1000); + + if (write) { + msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3); + msm_cmd_emit(cmd, lower_32_bits(addr)); /* ADDR_LO */ + msm_cmd_emit(cmd, upper_32_bits(addr)); /* ADDR_HI */ + msm_cmd_emit(cmd, 0x123); /* VAL */ + } else { + scratch_bo = igt_msm_bo_new(pipe->dev, 0x1000, MSM_BO_WC); + msm_cmd_pkt7(cmd, CP_MEM_TO_MEM, 5); + msm_cmd_emit(cmd, 0); + msm_cmd_bo (cmd, scratch_bo, 0); /* DEST_ADDR_LO/HI */ + msm_cmd_emit(cmd, lower_32_bits(addr)); /* SRC_A_ADDR_LO */ + msm_cmd_emit(cmd, upper_32_bits(addr)); /* SRC_A_ADDR_HI */ + } + + fence_fd = igt_msm_cmd_submit(cmd); + + /* Wait for submit to complete: */ + poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1); + close(fence_fd); + + igt_msm_bo_free(scratch_bo); + + /* And now we should have gotten a devcore from the iova fault + * triggered by the read or write: + */ + devcore = get_and_clear_devcore(); + igt_fail_on(!devcore); + + /* Make sure the devcore is from iova fault: */ + igt_fail_on(!strstr(devcore, "fault-info")); + + s = strstr(devcore, " - far: "); + igt_fail_on(!s); + + ret = sscanf(s, " - far: %"PRIx64, &fault_addr); + igt_fail_on(ret != 1); + igt_fail_on(addr != fault_addr); +} + +/* + * Tests for drm/msm hangcheck, recovery, and fault handling + */ + +igt_main +{ + struct msm_device *dev = NULL; + struct msm_pipe *pipe = NULL; + + igt_fixture { + dev = igt_msm_dev_open(); + pipe = igt_msm_pipe_open(dev, 0); + } + + igt_describe("Test ringbuffer mapping, should be read-only"); + igt_subtest("ring") { + do_mapping_test(pipe, "ring0", true); + } + + igt_describe("Test sqefw mapping, should be read-only"); + igt_subtest("sqefw") { + igt_require(dev->gen >= 6); + do_mapping_test(pipe, "sqefw", true); + } + + igt_describe("Test shadow mapping, should be inaccessible"); + igt_subtest("shadow") { + do_mapping_test(pipe, "shadow", true); + do_mapping_test(pipe, "shadow", false); + } + + igt_fixture { + igt_msm_pipe_close(pipe); + igt_msm_dev_close(dev); + } +} diff --git a/tests/msm/msm_recovery.c b/tests/msm/msm_recovery.c new file mode 100644 index 00000000..890c543a --- /dev/null +++ b/tests/msm/msm_recovery.c @@ -0,0 +1,174 @@ +/* + * Copyright © 2021 Google, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include <fcntl.h> +#include <sys/poll.h> + +#include "igt.h" +#include "igt_msm.h" + +static struct msm_device *dev; +static struct msm_bo *scratch_bo; +static uint32_t *scratch; + +/* + * Helpers for cmdstream packet building: + */ + +static void +wait_mem_gte(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t ref) +{ + msm_cmd_pkt7(cmd, CP_WAIT_MEM_GTE, 4); + msm_cmd_emit(cmd, 0); /* RESERVED */ + msm_cmd_bo (cmd, scratch_bo, offset_dwords * 4); /* POLL_ADDR_LO/HI */ + msm_cmd_emit(cmd, ref); /* REF */ +} + +static void +mem_write(struct msm_cmd *cmd, uint32_t offset_dwords, uint32_t val) +{ + msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3); + msm_cmd_bo (cmd, scratch_bo, offset_dwords * 4); /* ADDR_LO/HI */ + msm_cmd_emit(cmd, val); /* VAL */ +} + +/* + * Helper to wait on a fence-fd: + */ +static void +wait_and_close(int fence_fd) +{ + poll(&(struct pollfd){fence_fd, POLLIN}, 1, -1); + close(fence_fd); +} + +/* + * Helper for hang tests. Emits multiple submits, with one in the middle + * that triggers a fault, and confirms that the submits before and after + * the faulting one execute properly, ie. that the driver properly manages + * to recover and re-queue the submits after the faulting submit; + */ +static void +do_hang_test(struct msm_pipe *pipe) +{ + struct msm_cmd *cmds[16]; + int fence_fds[ARRAY_SIZE(cmds)]; + + memset(scratch, 0, 0x1000); + + for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) { + struct msm_cmd *cmd = igt_msm_cmd_new(pipe, 0x1000); + + cmds[i] = cmd; + + /* + * Emit a packet to wait for scratch[0] to be >= 1 + * + * This lets us force the GPU to wait until all the cmdstream is + * queued up. + */ + wait_mem_gte(cmd, 0, 1); + + if (i == 10) { + msm_cmd_emit(cmd, 0xdeaddead); + } + + /* Emit a packet to write scratch[1+i] = 2+i: */ + mem_write(cmd, 1+i, 2+i); + } + + for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) { + fence_fds[i] = igt_msm_cmd_submit(cmds[i]); + } + + usleep(10000); + + /* Let the WAIT_MEM_GTE complete: */ + scratch[0] = 1; + + for (unsigned i = 0; i < ARRAY_SIZE(cmds); i++) { + wait_and_close(fence_fds[i]); + igt_msm_cmd_free(cmds[i]); + if (i == 10) + continue; + igt_assert_eq(scratch[1+i], 2+i); + } +} + +/* + * Tests for drm/msm hangcheck, recovery, and fault handling + */ + +igt_main +{ + static struct msm_pipe *pipe = NULL; + + igt_fixture { + dev = igt_msm_dev_open(); + pipe = igt_msm_pipe_open(dev, 0); + scratch_bo = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC); + scratch = igt_msm_bo_map(scratch_bo); + } + + igt_describe("Test sw hangcheck handling"); + igt_subtest("hangcheck") { + igt_require(dev->gen >= 6); + igt_require(igt_debugfs_exists(dev->fd, "disable_err_irq", O_WRONLY)); + + /* Disable hw hang detection to force fallback to sw hangcheck: */ + igt_debugfs_write(dev->fd, "disable_err_irq", "Y"); + + do_hang_test(pipe); + + igt_debugfs_write(dev->fd, "disable_err_irq", "N"); + } + + igt_describe("Test hw fault handling"); + igt_subtest("gpu-fault") { + igt_require(dev->gen >= 6); + + do_hang_test(pipe); + } + + igt_describe("Test iova fault handling"); + igt_subtest("iova-fault") { + struct msm_cmd *cmd; + + igt_require(dev->gen >= 6); + + cmd = igt_msm_cmd_new(pipe, 0x1000); + + msm_cmd_pkt7(cmd, CP_MEM_WRITE, 3); + msm_cmd_emit(cmd, 0xdeaddead); /* ADDR_LO */ + msm_cmd_emit(cmd, 0x1); /* ADDR_HI */ + msm_cmd_emit(cmd, 0x123); /* VAL */ + + wait_and_close(igt_msm_cmd_submit(cmd)); + } + + igt_fixture { + igt_msm_bo_free(scratch_bo); + igt_msm_pipe_close(pipe); + igt_msm_dev_close(dev); + } +} diff --git a/tests/msm/msm_submit.c b/tests/msm/msm_submit.c new file mode 100644 index 00000000..95f8318f --- /dev/null +++ b/tests/msm/msm_submit.c @@ -0,0 +1,194 @@ +/* + * Copyright © 2021 Google, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "igt.h" +#include "igt_msm.h" + +igt_main +{ + struct msm_device *dev = NULL; + struct msm_pipe *pipe = NULL; + struct msm_bo *a = NULL, *b = NULL; + + igt_fixture { + dev = igt_msm_dev_open(); + pipe = igt_msm_pipe_open(dev, 0); + a = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC); + b = igt_msm_bo_new(dev, 0x1000, MSM_BO_WC); + } + + igt_describe("Check that a valid empty submit succeeds"); + igt_subtest("empty-submit") { + struct drm_msm_gem_submit req = { + .flags = pipe->pipe, + .queueid = pipe->submitqueue_id, + }; + do_ioctl(dev->fd, DRM_IOCTL_MSM_GEM_SUBMIT, &req); + } + + igt_describe("Check that submit with invalid submitqueue id fails"); + igt_subtest("invalid-queue-submit") { + struct drm_msm_gem_submit req = { + .flags = pipe->pipe, + .queueid = 0x1234, + }; + do_ioctl_err(dev->fd, DRM_IOCTL_MSM_GEM_SUBMIT, &req, ENOENT); + } + + igt_describe("Check that submit with invalid flags fails"); + igt_subtest("invalid-flags-submit") { + struct drm_msm_gem_submit req = { + .flags = 0x1234, + .queueid = pipe->submitqueue_id, + }; + do_ioctl_err(dev->fd, DRM_IOCTL_MSM_GEM_SUBMIT, &req, EINVAL); + } + + igt_describe("Check that submit with invalid in-fence fd fails"); + igt_subtest("invalid-in-fence-submit") { + struct drm_msm_gem_submit req = { + .flags = pipe->pipe | MSM_SUBMIT_FENCE_FD_IN, + .queueid = pipe->submitqueue_id, + .fence_fd = dev->fd, /* This is not a fence fd! */ + }; + do_ioctl_err(dev->fd, DRM_IOCTL_MSM_GEM_SUBMIT, &req, EINVAL); + } + + igt_describe("Check that submit with duplicate bo fails"); + igt_subtest("invalid-duplicate-bo-submit") { + struct drm_msm_gem_submit_bo bos[] = { + [0] = { + .handle = a->handle, + .flags = MSM_SUBMIT_BO_READ, + }, + [1] = { + .handle = b->handle, + .flags = MSM_SUBMIT_BO_READ, + }, + [2] = { + /* this is invalid.. there should not be two entries + * for the same bo, instead a single entry w/ all + * usage flags OR'd together should be used. Kernel + * should catch this, and return an error code after + * cleaning up properly (not leaking any bo's) + */ + .handle = a->handle, + .flags = MSM_SUBMIT_BO_WRITE, + }, + }; + struct drm_msm_gem_submit req = { + .flags = pipe->pipe, + .queueid = pipe->submitqueue_id, + .nr_bos = ARRAY_SIZE(bos), + .bos = VOID2U64(bos), + }; + do_ioctl_err(dev->fd, DRM_IOCTL_MSM_GEM_SUBMIT, &req, EINVAL); + } + + igt_describe("Check that submit with cmdstream referencing an invalid bo fails"); + igt_subtest("invalid-cmd-idx-submit") { + struct drm_msm_gem_submit_cmd cmds[] = { + [0] = { + .type = MSM_SUBMIT_CMD_BUF, + .submit_idx = 0, /* bos[0] does not exist */ + .size = 4 * 4, /* 4 dwords in cmdbuf */ + }, + }; + struct drm_msm_gem_submit req = { + .flags = pipe->pipe, + .queueid = pipe->submitqueue_id, + .nr_cmds = ARRAY_SIZE(cmds), + .cmds = VOID2U64(cmds), + }; + do_ioctl_err(dev->fd, DRM_IOCTL_MSM_GEM_SUBMIT, &req, EINVAL); + } + + igt_describe("Check that submit with invalid cmdstream type fails"); + igt_subtest("invalid-cmd-type-submit") { + struct drm_msm_gem_submit_bo bos[] = { + [0] = { + .handle = a->handle, + .flags = MSM_SUBMIT_BO_READ, + }, + }; + struct drm_msm_gem_submit_cmd cmds[] = { + [0] = { + .type = 0x1234, + .submit_idx = 0, + .size = 4 * 4, /* 4 dwords in cmdbuf */ + }, + }; + struct drm_msm_gem_submit req = { + .flags = pipe->pipe, + .queueid = pipe->submitqueue_id, + .nr_cmds = ARRAY_SIZE(cmds), + .cmds = VOID2U64(cmds), + .nr_bos = ARRAY_SIZE(bos), + .bos = VOID2U64(bos), + }; + do_ioctl_err(dev->fd, DRM_IOCTL_MSM_GEM_SUBMIT, &req, EINVAL); + } + + igt_describe("Check that a valid non-empty submit succeeds"); + igt_subtest("valid-submit") { + struct drm_msm_gem_submit_bo bos[] = { + [0] = { + .handle = a->handle, + .flags = MSM_SUBMIT_BO_READ, + }, + }; + struct drm_msm_gem_submit_cmd cmds[] = { + [0] = { + .type = MSM_SUBMIT_CMD_BUF, + .submit_idx = 0, + .size = 4 * 4, /* 4 dwords in cmdbuf */ + }, + }; + struct drm_msm_gem_submit req = { + .flags = pipe->pipe, + .queueid = pipe->submitqueue_id, + .nr_cmds = ARRAY_SIZE(cmds), + .cmds = VOID2U64(cmds), + .nr_bos = ARRAY_SIZE(bos), + .bos = VOID2U64(bos), + }; + uint32_t *cmdstream = igt_msm_bo_map(a); + if (dev->gen >= 5) { + *(cmdstream++) = pm4_pkt7_hdr(CP_NOP, 3); + } else { + *(cmdstream++) = pm4_pkt3_hdr(CP_NOP, 3); + } + *(cmdstream++) = 0; + *(cmdstream++) = 0; + *(cmdstream++) = 0; + + do_ioctl(dev->fd, DRM_IOCTL_MSM_GEM_SUBMIT, &req); + } + + igt_fixture { + igt_msm_bo_free(a); + igt_msm_bo_free(b); + igt_msm_pipe_close(pipe); + igt_msm_dev_close(dev); + } +} |