diff options
| author | Eric Anholt <eric@anholt.net> | 2009-10-22 15:52:02 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-02-25 10:41:49 -0800 |
| commit | 613d1c48968bf5b6130d01a3408a70fc2d1307ee (patch) | |
| tree | 34fad033ca78a57b698ff59a08dcd2d3e191161f /tools/intel_reg_dumper.c | |
| parent | c94174d106b0b7c97643309ec85d763b0429ef11 (diff) | |
Add some initial definitions for Sandybridge.
Diffstat (limited to 'tools/intel_reg_dumper.c')
| -rw-r--r-- | tools/intel_reg_dumper.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c index d21e6763..125434ba 100644 --- a/tools/intel_reg_dumper.c +++ b/tools/intel_reg_dumper.c @@ -131,7 +131,7 @@ DEBUGSTRING(i830_debug_dspcntr) { char *enabled = val & DISPLAY_PLANE_ENABLE ? "enabled" : "disabled"; char plane = val & DISPPLANE_SEL_PIPE_B ? 'B' : 'A'; - if (IS_IRONLAKE(devid)) + if (HAS_PCH_SPLIT(devid)) asprintf(result, "%s", enabled); else asprintf(result, "%s, pipe %c", enabled, plane); @@ -149,7 +149,7 @@ DEBUGSTRING(i830_debug_pipeconf) bit30 = val & PIPEACONF_DOUBLE_WIDE ? "double-wide" : "single-wide"; - if (IS_IRONLAKE(devid)) { + if (HAS_PCH_SPLIT(devid)) { switch (val & (7 << 5)) { case PIPECONF_8BPP: bpc = "8bpc"; @@ -165,7 +165,7 @@ DEBUGSTRING(i830_debug_pipeconf) break; } } - if (IS_IRONLAKE(devid)) + if (HAS_PCH_SPLIT(devid)) asprintf(result, "%s, %s, %s", enabled, bit30, bpc); else asprintf(result, "%s, %s", enabled, bit30); @@ -447,7 +447,7 @@ DEBUGSTRING(i830_debug_adpa) char hsync = (val & ADPA_HSYNC_ACTIVE_HIGH) ? '+' : '-'; char vsync = (val & ADPA_VSYNC_ACTIVE_HIGH) ? '+' : '-'; - if (IS_IRONLAKE(devid)) + if (HAS_PCH_SPLIT(devid)) asprintf(result, "%s, transcoder %c, %chsync, %cvsync", enable, pipe, hsync, vsync); else @@ -1655,7 +1655,7 @@ int main(int argc, char** argv) { intel_get_mmio(); - if (IS_IRONLAKE(devid)) + if (HAS_PCH_SPLIT(devid)) ironlake_dump_regs(); else intel_dump_regs(); |