quick_dump: pass register offsets as int

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[imre: fix s/regi/intreg/ typo]
Reviewed-by: Imre Deak <imre.deak@intel.com>

2 files changed, 10 insertions, 14 deletions

diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index ac8cede6..a3bd8427 100755
--- a/tools/quick_dump/quick_dump.py
+++ b/tools/quick_dump/quick_dump.py
@@ -36,13 +36,13 @@ def parse_file(file):
         if ignore_line(line):
             continue
         register = ast.literal_eval(line)
-        if register[2] == 'DPIO':
-            val = reg.dpio_read(register[1], 0)
-        elif register[2] == 'FLISDSI':
-            val = reg.flisdsi_read(register[1])
-        else:
-            val = reg.read(register[1])
         intreg = int(register[1], 16)
+        if register[2] == 'FLISDSI':
+            val = reg.flisdsi_read(intreg)
+        elif register[2] == 'DPIO':
+            val = reg.dpio_read(intreg, 0)
+        else:
+            val = reg.read(intreg)
         print('{0:#010x} | {1:<28} | {2:#010x}'.format(intreg, register[0], val))
     print('')
 
diff --git a/tools/quick_dump/reg_access.py b/tools/quick_dump/reg_access.py
index 84fea7c0..6a93f63e 100755
--- a/tools/quick_dump/reg_access.py
+++ b/tools/quick_dump/reg_access.py
@@ -3,7 +3,6 @@
 import chipset
 
 def read(reg):
-    reg = int(reg, 16)
     val = chipset.intel_register_read(reg)
     return val
 
@@ -12,15 +11,15 @@ def write(reg, val):
 
 def gen6_forcewake_get():
     write(0xa18c, 0x1)
-    read("0xa180")
+    read(0xa180)
 
 def mt_forcewake_get():
     write(0xa188, 0x10001)
-    read("0xa180")
+    read(0xa180)
 
 def vlv_forcewake_get():
     write(0x1300b0, 0x10001)
-    read("0x1300b4")
+    read(0x1300b4)
 
 # don't be clever, just try all possibilities
 def get_wake():
@@ -29,15 +28,12 @@ def get_wake():
     vlv_forcewake_get()
 
 def dpio_read(reg, phy):
-    reg = int(reg, 16)
     phy = int(phy)
 
     val = chipset.intel_dpio_reg_read(reg, phy)
     return val
 
 def flisdsi_read(reg):
-    reg = int(reg, 16)
-
     val = chipset.intel_flisdsi_reg_read(reg)
     return val
 
@@ -62,5 +58,5 @@ if __name__ == "__main__":
         sys.exit()
 
     reg = sys.argv[1]
-    print(hex(read(reg)))
+    print(hex(read(int(reg,16))))
     chipset.intel_register_access_fini()