Age | Commit message (Collapse) | Author |
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One property lost in the expansion for various coherency checks was
ensuring that every time we overwrote the batch it had a unique value
(to ensure that the GPU was seeing the latest value).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Look at handling of multiple batches within the buffer and avoiding as
much synchronisation as possible.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Enable testing on all connectors that have the "scaling mode"
property set.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93012
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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Switched from DRIVER_INTEL to DRIVER_ANY to enable test
on all hardware.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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Changed the DRM format to LOCAL_DRM_FORMAT_MOD_NONE since it
is hardware agnostic.
Also fixed formatting/tabs.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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ref_crc is never assigned or read, and can be safely
removed.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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pipe_crc in data_t is assigned an allocated memory space and
then later free'd. But it is never used for any comparisons.
It should therefore be safe to remove pipe_crc and the crc
requirement.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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Remove devid from data_t since it is never read.
Also remove one assignment to devid.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93012
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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We can simply sscanf the crc in one go. Also split up the igt asserts to
get better details about what went wrong.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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We'll be adding more context for the subtests than just the max
brightness.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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Gives out better diagnostics than just igt_asssert.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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Before we print the exitcode to the debug/kmsg logs, we should inspect
what its final value will be. For example, in the case of running
multiple subtests which all happen to be skipped, igt_exitcode is 0, but
the final exit code will be 77.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Tested-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Avoid the second pair of full clflushes when setting up the batch.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Unlike in the kernel driver coding style, IS_965() matches the platform
and all subsequent ones. Replace IS_965() with suitable but less
confusing alternatives.
Most occurences are on code paths that only get called for gens 2, 3 and
4, so replace those with IS_GEN4(). In the one other call site just flip
the condition to check for gens 2 and 3 instead.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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It's also confusing as the style differs from the kernel (exact platform
in the kernel vs. the platform and any later ones in igt).
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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No functional change and no change in the current format.
Just introducing the missing Kabylake name strings.
v2: Duh! forgot the ")"...
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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When using the kernel set-domain cache management, we need to set the
domain as appropriate for our pointer access. In this case we access the
buffer through a CPU mmap, and so we must request access via the CPU
domain.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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When looking at a pair of GPU writes, where we want to make sure that
the clean cacheline is invalidated automatically, we want to reuse that
cacheline whilst we know it remains valid (i.e. repeat the test using a
new value to the same location).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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32bit builds ran into a silly multiplication issue when computing
elapsed nanoseconds of more than 2s...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Since the value in the bo may be altered by the test, we only want to
repeat phases of the test to avoid breaking the test itself.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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If we assume that the first settimer and clock_gettime() itself have
appreciable overhead, try to exclude those from the calibration delay.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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Add a requirement for mmap-wc so that failure on older kernels is explained.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Look at different cachelines on each pass, otherwise each group of 16
flush the same cachline.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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As a point of comparison, test the pread/pwrite interface as well.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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We can make the requirement testing and reporting tidier by using
igt_subtest_group.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Alternate between two values written by the GPU so that we can look for
stale cachelines without having to overwrite the value with the CPU.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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On Baytrail, Braswell and Atoms beyond we see an issue where the mfence
is insufficient to force the cacheline to be coherent (i.e. such that
writes from the GPU are visible by the CPU after the call to clflush). A
second clflush is ordered with an earlier clflush to the same address
and this appears sufficient to give the coherency required for GPU/CPU
interop.
Testcase: igt/gem_exec_flush
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Akash Goel <akash.goel@intel.com>
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A basic check that the execbuf flushes writes from the batch and that
they are coherent afterwards.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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When waiting for the producers to start, use the cond/mutex of the
Nth producer and not always the first.
Spotted-by: "Goel, Akash" <akash.goel@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Attempt to fill buffers using many clients working in parallel.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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igt_fork_hang_detector() was called from a igt_fixture block, while its
counterpart (igt_stop_hang_detector) was called normally, causing
SIGTERM to be sent when running under check target.
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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Remember to skip using BSD on gen6, unless you want to kill the machine.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95134
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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This change mirrors the change in drm made by krh@redhat.com
on "Mon Apr 6 17:18:17 2009" on the drm branch intel_on_all_hw.
The assert(major < 1) is only needed for the legacy intel driver.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Switched to assert helpers to enable better error output.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
[tomeu: fix test of major version to be lte]
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Caught by check target.
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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So that this test can be run in drivers other than i915.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Series-version: 1
Series-to: intel-gfx
Series-cc: padovan, daniels, marcheu, seanpaul, xexaxo, fedkem, mvlad, danvet
Series-prefix: i-g-t
Cover-letter:
Make more tests generic
Hi,
these patches allow a few more tests to run on drivers other than i915,
mainly by removing the last usage of
DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID and removing superfluous dependencies
on bufmgr and tiled BOs.
Thanks,
Tomeu
END
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As the test doesn't actually need tiled BOs, drop the tiled formats so
the test can run on drivers other than i915.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
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So that this test can be run in drivers other than i915.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
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Because bufmgr is currently a i915-only thing and it's only needed in a
subset of the subtests, require it only in the subtests that actually
need it so that the other subtests aren't skipped without a reason.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
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Because attempts to create a tiled BO will cause a igt_require call to
fail on drivers that don't support tiling, do so in the subtest that
actually needs it so that other subtests aren't skipped without reason.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
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Batchbuffers are only needed in the subtest that does the blit on the
GPU, so move that dependency into it so the other subtest can be ran on
!i915.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
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