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v2: Moved identical code into a single function (Paulo)
v3 (from Paulo): stay under 80 columns.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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Allow tests to create Y-tiled bufferes using a separate
argument to the test without increasing the number of
subtests.
v2: Changed tiling option to string (Paulo)
v3 (from Paulo): minor nitpicks.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
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The multidraw subtest was not taking whether or not the GEM buffer had
ever been in write-combining mode when checking for PSR state, so fix
that.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
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Each Linux distro takes a different spin on providing kernel's uapi
headers (especialy the *drm*.h).
You can get them with linux-headers, you can get them with libdrm.
Sometime you can even get them twice, from both sources.
Sometimes the headers match your kernel version, sometimes you end up
stuck with headers matching the kernel that the given release of the
distro came out with.
This makes things harder for code that does not depend on libdrm, as we
cannot have sane ./configure-time checks.
So let's define LOCAL_ version for FENCE and EXECBUFFER2_WB defines
until all the stable distros catch up (+/- some epsilon).
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
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This will make the IGT tests that use fences more useful, since they can
perform the waiting themselves when required.
To celebrate, also add plane-use-after-nonblocking-unbind-fencing,
the fence version of plane-use-after-nonblocking-unbind.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Gustavo Padovan <gustavo.padovan@collabora.com>
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This is already done in igt_display_commit* functions.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Gustavo Padovan <gustavo.padovan@collabora.com>
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Trying to set a fence on disabled pipes will be rejected by the kernel:
[ 1275.865029] [drm:drm_atomic_check_only [drm]] [CRTC:39:pipe B] requesting event but off
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99911
Acked-by: Gustavo Padovan <gustavo.padovan@collabora.com>
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All other atomic properties are reset in display_commit_changed,
which is the right place because TEST_ONLY commits don't need to
be reset.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Gustavo Padovan <gustavo.padovan@collabora.com>
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When a plane gets disabled, that commit has to complete before an
atomic commit on that disabled plane only. Else for the old commit,
new_plane_state may have been freed.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Gustavo Padovan <gustavo.padovan@collabora.com>
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Trivial test to alternate executing a batch either stored in the last
slot (default) or the first slot (EXEC_BATCH_FIRST).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Negative testing ftw.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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References: https://bugs.freedesktop.org/show_bug.cgi?id=101717
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Currently the panning tests actually stop panning when they hit the
right edge fo the framebuffer. Let's make them ping-pong across the
fb to make it clear that they are indeed trying to pan around all the
time.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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This reverts commit 218eb00f3bd0a0e8dd9bb184f6df1550593e8d27.
Accidentally pushed I patch that wasn't meant to be.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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We need this for AMDGPU_FAMILY_AI. Fixes:
commit 36b92e809f378e18af980ffa5b29361bd28098cb
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat Apr 22 13:45:18 2017 +0100
igt: Import basic amdgpu tests from libdrm
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
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This adds support for configurable suspend/resume delay and takes the
occasion to move igtrc configuation from igt_chamelium to igt_core.
This way, suspend/resume delay configuration can be used for all tests.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@linux.intel.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
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Since most tests are already doing a reset, there is no need to
duplicate it at init time. This removes that duplicate reset and adds
a call to reset_state where in-test resets where not done previously.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@linux.intel.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
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This reverts commit d7a0b61450797a3d6644c65aebf75c2a90da1a15.
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This reverts commit f807953c4e90870df940ecb0e4b5c51caa50167e.
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This reverts commit 537c4849d476661409425b0e2a5ad8bce4c561eb.
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For tests with attempt to hit races and such by running for
relatively long time, it seems that it might be possible to get
by only testing some subtest-engine combinations as long as in
total we still exercise all engines per test.
More precisely, I think that if we view our engines as fast
(!rcs) and a little less fast (others), we group the race
hitting tests in those two camps, we keep the same coverage
by running each subtest against each engine group.
v2: Replace individual engine gem_sync subtests with all
variants. (Chris Wilson)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@intel.com>
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Extended versions of the already existing short tests.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Daniel Vetter <daniel.vetter@intel.com>
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Exercise the ABI with a basic test now that we have removed the
defaul engine alias from the engine list.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@intel.com>
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Default is not an engine but an ABI alias for RCS. Remove it
from the engine list to eliminate redundant subtests and test
passes.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@intel.com>
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AMDGPU_FAMILY_AI was introduced in commit being part of libdrm 2.4.76
release and amd_basic tests are using that define.
Since the module is turned on by default this results in compilation
failing on machines with older libdrm.
Let make them fail on ./configure step instead.
Cc: Leo Liu <leo.liu@amd.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reported-by: Martin Peres <martin.peres@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
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Testing LNCFCMOCS values on non-render engines is tricky. The values in
those registers are lost on RC6, which means that if users of non-render
engines want to see the proper values, they need to obtain a forcewake
and execute something on render (relying on it to restore the values)
before using non-render engine.
Previous version of the test did exactly that - we were relying on the
fact that we're taking forcewake (hidden by intel_register_access_init,
even though the test is not doing any mmio accesses) before iterating
through engines (and render is before other engines, so job done).
I really hope that this is not an ABI and those registers are not used
on non-render in any way. Let's limit testing LNCFCMOCS to render
engine only.
The other non-render issue is that when we're using I915_EXEC_BSD, we
can't be sure which BSD ring we'll end up executing on. Let's
explicitly select BSD1 and BSD2 in our tests.
While we're here, let's also remove the duplicated code and add some
structure by extracting moving more content into subtests.
We're only doing tests that involve "dirtying" the registers for the
render engine - since it's the only one that has those registers in its
context.
v2: Do not skip all BSD engines, test non-default contexts on render
only, change names in CI extended.testlist
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Łukasz Kałamarz <lukasz.kalamarz@intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Łukasz Kałamarz <lukasz.kalamarz@intel.com>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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This reverts commit 9a6ed6c6398c2218d65392593fa43852810515cc.
Test actually exposes a bug in the kernel where opening the crtc-data
file takes a long time.
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
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When descending thru debugfs directory. Doing this tends to
takes forever. CRC pipe read tests for this are already
covered under kms_pipe_crc_basic.
v2: Be more verbose that the check is meant for the crtc control data
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: arkadiusz.hiler@intel.com
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
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This currently only happens when the power well is not enabled,
but in theory should happen every time the file is opened when
the CRTC is not enabled.
This fixes debugfs_test@read_all_entries failing on f2-bxt-j3405.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Use the convenience function instead of handrolling it.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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On CHV pipe C when the cursor is visible with a negative X coordinate
a FIFO Underrun will occur. The kernel worked around this by disallowing
cursor updates on pipe C at negative X coordinates when the cursor is
visible.
This was done in the following kernel commit:
commit ef8dd37af85a8f37ca3a29074647511e52c56181
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date: Fri Dec 18 19:24:39 2015 +0200
drm/i915: Workaround CHV pipe C cursor fail
kms_chv_cursor_fail was created to test this issue, but it also happens
in kms_cursor_crc, so workaround it there too.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97960
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No functional change.
When CNL patches got rebased on top of cfl
the ids ended up in the middle of CFL ids. So let's
clean-up this mess a bit.
Also remove a spurious line.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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None of the fields we use on render_copy and gpgpu_fill has changed
when compared to gen9. So let's reuse them.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Apparently nothing changed since BDW on these instdone bits.
So let's reuse instead of empty duplication.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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By the Spec all CNL Y skus are 2+2, i.e. GT2.
This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")
v2: Based on Anusha's kernel clean-up.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
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Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is also the new Spec style what makes the review much
more easy and straightforward.
This is a copy of merged i915's
commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")
v2: Based on Anusha's kernel clean-up.
v3: Add kernel commit id for reference.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
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Cannonlake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.
It is Gen10.
Let's start by adding the platform definition based on previous
platforms.
On following patches we will start adding PCI IDs and the
platform specific changes.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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Follow the spec and add ID for U SKU
v2: Update IDs in accordance to the kernel commit:
d29fe702c9cb682df99146d24d06e5455f043101 (Chris)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clint Taylor <clinton.a.taylor@intel.com>
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Follow the spec and add the ID for H SKU in
CFL.
v2: Update IDs following kernel commit:
ccfd13215fd25a0e8c28221f3acc0dcaec11cd15 (Chris)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clint Taylor <clinton.a.taylor@intel.com>
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Just following the spec and adding these extra IDs.
v2: update IDs following the kernel commit:
b056f8f3d6b900e8afd19f312719160346d263b4 (Chris)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clint Taylor <clinton.a.taylor@intel.com>
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Coffeelake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.
It is Gen9 graphics based platform on top of CNP PCH.
On following patches we will start adding PCI IDs and the
platform specific changes.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
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The intent is that during interruptible runs we always force a
relocation between batch. This requires us to set an invalid
presumed_offset.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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The content of the batch may no longer match the offset/presumed_offset
pair, so force the relocation by setting reloc.presumed_offset=-1
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Several tests were passing a presumed_offset that matches the actual
offset of the object and so were very suprised when the kernel promptly
skipped performing the relocation (as expected).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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"This is a wraps" -> "This wraps"
"hw/hardware context" -> "context"
gem_context_create does not use igt_require() but igt_skip_on() so make
the similarity note more vague and in result true.
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
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Function description incorrectly stated that gem_context_get_param
and gem_context_set_param were freeing hw context.
v2: removed additional incorrect information
Signed-off-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
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They're not useful since GPU reset may kill off our spin batch.
This used to be the case but wasn't in the kernel when I wrote this
test. But the following commit reintroduced this behavior:
commit 36703e79a982c8ce5a8e43833291f2719e92d0d1
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Jun 22 11:56:25 2017 +0100
drm/i915: Break modeset deadlocks on reset
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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DRM_MODE_PAGE_FLIP_EVENT is now rejected if no CRTC is affected by the
changes. Make sure the TEST_ONLY test keeps working, and test with
DRM_MODE_PAGE_FLIP_EVENT.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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