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Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Now that all instructions (relocatable or not) are struct
brw_program_instructions, this means we can move the relocation specific
information out the "relocatable instruction" structure. This will allow
us to share the relocation information between different types of
instructions.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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This will be less typing for the refactoring to come (which is use
struct brw_program_instruction in gram.y for the type of all the
instructions).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Not everything has to be exported out the compilation unit. Do a small
cleanup pass.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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The list of region restrictions in bspec do say that we can't have:
width == 1 && hstrize != 0
We do have plenty of assembly code that don't respect that behaviour. So
let's hide the warning under a -W flag (for now) while we fix things.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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A few notes:
I needed to introduce a brw context and compile structs. These are only
used to get which generation we are compiling code for, but eventually
we can use more of the infrastructure.
brw_set_dest() uses the destination register width to program the
instruction execution size.
The assembler can either take subnr in bytes or in number of elements,
so we need a resolve step when setting a brw_reg.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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and make then static.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Until now, the assembler had relocation-related fields added to struct
brw_instruction. This changes the size of the structure and break code
assuming the opcode structure is really 16 bytes, for instance the
emission code in brw_eu_emit.c.
With this commit, we build on the infrastructure that slowly emerged in
the few previous commits to add a relocatable instruction with the
needed fields.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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The output of the parsing is a list of struct brw_program_instruction.
These instructions can be either GEN instructions aka struct
brw_instruction or labels. To make this more explicit we now have a type
to test to determine which instruction we are dealing with.
This will also allow to to pull the relocation bits into struct
brw_program_instruction instead of having them in the structure
representing the opcodes.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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No need to use a brw_program_instruction there as a brw_instruction is
what you really dump anyway, espcially when the plan is to use
brw_compile from Mesa sooner rather than later.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Once again, import the equivalent struct from mesa.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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