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2017-03-10assembler/gen8_disasm.c: Remove unused m_mask_ctrlPetri Latvala
Signed-off-by: Petri Latvala <petri.latvala@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com>
2016-11-30assembler: RSQ is a math functionKristian H. Kristensen
Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-11-30assembler: Set 3src options before sourcesKristian H. Kristensen
Setting the 3src sources will assert align16, but that doesn't get set until we call set_instruction_options(). Call that before setting sources. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-11-30assembler: Fix assert when setting 3src sourcesKristian H. Kristensen
We need to map the type to the 3src encoding before comparing to insn->bits1.da3src.src_reg_type, which is 3src encoded. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2016-09-01autotools/: Allow check target to be invoked w/o the need to issue a build.Marius Vlad
We need to have the test list generated before running the check target. Migrated igt_command_line.sh to tests/ from lib/tests/, which allows to building the tests and execute the script. This would allow cleaning followed by a make check. Also assembler/ directory needs also to be adjusted in order for this to work. Kept the possibility to invoke tests/igt_command_line.sh to determine which test is failing. Signed-off-by: Marius Vlad <marius.c.vlad@intel.com> Url: https://patchwork.freedesktop.org/series/6539/ Reviewed-By: Chris Wilson <chris@chris-wilson.co.uk>
2016-06-23assembler/: Fix lex warnings for %empty and %nonassoc.marius vlad
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com> Acked-by: Damien Lespiau <damien.lespiau@intel.com>
2015-08-21assembler: remove built sources with make cleanThomas Wood
Built sources are generated by "make all", so should be removed by "make clean". This also ensures "distcleancheck" passes. Signed-off-by: Thomas Wood <thomas.wood@intel.com>
2014-09-30assembler/skl: update the extdesc field for SEND instructionZhao Yakui
The send instruction on gen9 uses the 32bit immediate instead of 6bit immediate for the extended message descriptors. And some bits of SEND instruction are defined as the extdesc field. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: Add more cache agent for write(...)Zhao Yakui
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: update read(...)Zhao Yakui
READ(...) is used for Render Target read and Media Block read. But there is no sampler cache agent on gen9. At the same time two message types don't share the same cache agent any more. So a parameter is needed for cache agent. The 2th parameter of read(...) is not used for gen6/gen7/gen8. Hence it is reused as cache agent for SKL as that on ILK. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: Redefine the cache agent type for some fixed functionsZhao Yakui
The different cache agent type is defined for SKL although it still uses the same function ID as the previous generations. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-09-30assembler/skl: Add gen 9 to the -g optionDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-05-19assembler: distinguish the channel of .z from the condition of .zXiang, Haihao
The scratch patch only works for generic register Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75631 Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-05-19assembler: switch the order of swizzle and regtype to match the BNF of the ↵Xiang, Haihao
assembly Fortunately our existing source didn't use swizzle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75631 Tested-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-02-13Assembler/bdw: Remove the unsupported cache agent for WRITE(...)Zhao Yakui
The Sampler/Constant cache is read-only. And it can't be used as the target cache agent of WRITE message. Reviewed-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-02-11assembler: fix condition for printing a warningThomas Wood
Signed-off-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-02-06assembler: define YY_NO_INPUT to prevent unused symbol warningsThomas Wood
Signed-off-by: Thomas Wood <thomas.wood@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-06assembler/bdw: Update write(...)Xiang, Haihao
write(...) is used for Render Target Write and Media Block Write. The two message types no longer share the same cache agent on GEN8, So a parameter is needed for cache agent. The 4th parameter of write() is used for write commit bit which has been removed since GEN7. Hence we can re-use the 4th parameter as cache agent on GEN8 Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-06assembler/bdw: Add the DATA_PORT_CACHE1 shared function for Gen8+Zhao Yakui
This is required to send some messages to data port in GPU shader. For example: media_block_write message. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Add the support of align1 register-indirect addressing mode ↵Zhao Yakui
on Gen8 Otherwise it can't compile the following GPU shader that uses the register-indirect addressing mode. >add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw >add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: SEND instructionXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Small cleanupBen Widawsky
This was originally part of: commit 62298329350b965e4bbfc558e5a4b1b3646742ea Author: Xiang, Haihao <haihao.xiang@intel.com> Date: Wed Aug 14 14:21:16 2013 -0700 assembler: error for the wrong syntax of SEND instruction on GEN6+ I merged that patch separately, but this tiny hunk was leftover. In order to not muck in changing too much history, I am leaving this as a discrete patch, but with the changed commit message Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Check & Refinement Engine messageXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Video Motion Estimation(VME) messageXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Thread Spawn messageXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Data port messageXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Set thread switch for multiple branch instructionsXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Set jip/uip offsets used by flow control instructionsXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Disable mask control for advanced modeXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Set math functionXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Use gen8_set_exec_size() to set the execution sizeDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Preliminary gen8 send & msgtarget supportDamien Lespiau
Still some work needed there, but enough for rendercopy. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Add the start of a gen8 disassemblerDamien Lespiau
Directly taken from Mesa. v2 (Ben): Updated copyright Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Make the validation functions take a brw_program_instructionDamien Lespiau
This allows to use the same functions to validate operands on gen8 for now. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Support some basic gen8 intructionsDamien Lespiau
We should now support alu2 intructions with direct register addressing. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06assembler/bdw: Add gen8_instruction from mesaDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-04Update .gitignore a bitDaniel Vetter
- Ignore build-aux/ - Cleanup ignores for assembler/
2013-08-20assembler: Disable the declare testDamien Lespiau
It's not hitting a valid assertion that it tries to write an instruction without a defined execution size (because the "default" exec_size never end up being set). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-20assembler: Disable tests that where already failing in the gen4asm repoDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-20assembler: Ignore make check outputDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-20assembler: Fix the path of intel-gen4asmDamien Lespiau
With the move to intel-gpu-tools, we need to update that as well. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-20assembler: Revert "Fix missing environment variables problem in ↵Damien Lespiau
test/run-test.sh" Same as: commit 497814f2f2828efdc5bdd787ebc490d5083f61b8 Author: Damien Lespiau <damien.lespiau@intel.com> Date: Tue Aug 20 14:52:05 2013 +0100 assembler: Revert "Automatically run all test cases." make check will define srcdir and buildir variables for us. This reverts commit 1c009349bc894bd195b5522540536898b0bee574.
2013-08-20assembler: Revert "Automatically run all test cases."Damien Lespiau
The tests where supposed to be run through make check, not running the "run-test.sh" standalone. So revert that patch to have make check work as intended. This reverts commit 6983eebf47f37def8f2315d5af1800b81644f240.
2013-08-20assembler: Tune the error message for invalid send on gen6+Damien Lespiau
And be a bit more descriptive. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-15assembler: error for the wrong syntax of SEND instruction on GEN6+Xiang, Haihao
predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions predicate SEND execsize dst sendleadreg payload imm32reg instoptions predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions The above four syntaxes are only used on legacy platforms which support implied move from payload to dst. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-05-22assembler: Add support for the SENDC instruction.Matt Turner
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Mark format() as PRINTFLIKE in the disassemblerDamien Lespiau
So when making changes in code using that function, we get warnings about mismatches between the format string and arguments. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Fix the decoding of the destination horizontal strideDamien Lespiau
dest_horizontal_stride needs go through the horiz_stride[] indirection to pick up the rigth stride when its value is 11b (4 elements). Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Group the header inclusions togetherDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-03-04assembler: Don't use GL typesDamien Lespiau
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \ -e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \ -e 's/GLshort/int16_t/g' assembler/*.[ch] Drop the GL types here, they don't bring anything to the table. For instance, GLuint has no guarantee to be 32 bits, so it does not make too much sense to use it in structure describing hardware tables and opcodes. Of course, some bikeshedding can be applied to use uin32_t instead, I figured that some of the GLuint are used without size constraints, so a sed with uint32_t did not seem the right thing to do. On top of that initial sed, one bothered enough could change the structures with size constraints to actually use uint32_t. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-14 09:40:37 +0000