Age | Commit message (Collapse) | Author |
|
The Sampler/Constant cache is read-only. And it can't be used as
the target cache agent of WRITE message.
Reviewed-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
|
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
|
write(...) is used for Render Target Write and Media Block Write.
The two message types no longer share the same cache agent on GEN8,
So a parameter is needed for cache agent. The 4th parameter of write()
is used for write commit bit which has been removed since GEN7. Hence
we can re-use the 4th parameter as cache agent on GEN8
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
This is required to send some messages to data port in GPU shader.
For example: media_block_write message.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
on Gen8
Otherwise it can't compile the following GPU shader that uses the
register-indirect addressing mode.
>add.sat (16) r[a0.5,0]<1>:uw r[a0.5,0]<16;16,1>:uw 0x0080:uw
>add.sat (16) r[a0.5,32]<1>:uw r[a0.5,32]<16;16,1>:uw 0x0080:uw
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
This was originally part of:
commit 62298329350b965e4bbfc558e5a4b1b3646742ea
Author: Xiang, Haihao <haihao.xiang@intel.com>
Date: Wed Aug 14 14:21:16 2013 -0700
assembler: error for the wrong syntax of SEND instruction on GEN6+
I merged that patch separately, but this tiny hunk was leftover. In
order to not muck in changing too much history, I am leaving this as a
discrete patch, but with the changed commit message
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Still some work needed there, but enough for rendercopy.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Directly taken from Mesa.
v2 (Ben): Updated copyright
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
This allows to use the same functions to validate operands on gen8 for
now.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
We should now support alu2 intructions with direct register addressing.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
- Ignore build-aux/
- Cleanup ignores for assembler/
|
|
It's not hitting a valid assertion that it tries to write an instruction
without a defined execution size (because the "default" exec_size never
end up being set).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
With the move to intel-gpu-tools, we need to update that as well.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
test/run-test.sh"
Same as:
commit 497814f2f2828efdc5bdd787ebc490d5083f61b8
Author: Damien Lespiau <damien.lespiau@intel.com>
Date: Tue Aug 20 14:52:05 2013 +0100
assembler: Revert "Automatically run all test cases."
make check will define srcdir and buildir variables for us.
This reverts commit 1c009349bc894bd195b5522540536898b0bee574.
|
|
The tests where supposed to be run through make check, not running the
"run-test.sh" standalone. So revert that patch to have make check work
as intended.
This reverts commit 6983eebf47f37def8f2315d5af1800b81644f240.
|
|
And be a bit more descriptive.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions
predicate SEND execsize dst sendleadreg payload imm32reg instoptions
predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions
predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions
The above four syntaxes are only used on legacy platforms which support implied move
from payload to dst.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
|
|
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
So when making changes in code using that function, we get warnings
about mismatches between the format string and arguments.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
dest_horizontal_stride needs go through the horiz_stride[] indirection
to pick up the rigth stride when its value is 11b (4 elements).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
sed -i -e 's/GLuint/unsigned/g' -e 's/GLint/int/g' \
-e 's/GLfloat/float/g' -e 's/GLubyte/uint8_t/g' \
-e 's/GLshort/int16_t/g' assembler/*.[ch]
Drop the GL types here, they don't bring anything to the table. For
instance, GLuint has no guarantee to be 32 bits, so it does not make too
much sense to use it in structure describing hardware tables and
opcodes.
Of course, some bikeshedding can be applied to use uin32_t instead, I
figured that some of the GLuint are used without size constraints, so
a sed with uint32_t did not seem the right thing to do. On top of that
initial sed, one bothered enough could change the structures with size
constraints to actually use uint32_t.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Instead of just using hardcoded numbers or resorting to ffs().
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
No reason not to!
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
I originally moved struct opcode_desc from brw_context.h to brw_eu.h on
the mesa side, but that was before the realization we needed struct
brw_context if we wanted to not touch the code too much.
So put it back there now that the mesa patch has been dropped.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
gen4asm.h is assembler specific while we want the library files to be
somewhat of a proper library.
This means that we have to redefine the GL* typedefs for brw_structs.h,
not using any of thet GL typedef will be for a future commit.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Also simplify the logic that was setting the saturate bit in the math
instruction.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
This allow us to factor out the test that checks if, when using both
predicates and conditional modifiers, we are using the same flag
register.
Also get rid of of a FIXME that we are now dealing with (the warning
mentioned above).
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|
|
Like with the predicate fields before, there's no need to use the full
instruction to collect the list of options. This allows us to decouple
the list of options from a specific instruction encoding.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
|