Age | Commit message (Collapse) | Author |
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Stronger checks for some of the fields like dependencies out
of range and invalid values.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Instead of numbers passed to -b also allow strings.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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It makes more sense for the sequence of random batch durations
to be different between different clients.
Also add a new command line option (-S) to enable forcing the
same sequence if so can be useful for testing.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
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New command option -R enables the initial VCS engine assignment
to be round-robinned across all clients.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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This one flips a coin when it fails to decide where to schedule.
It works well with the hd12 workload, either for one or multiple
clients, on which other balancers fail at the moment.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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hd06mp2, hd12: Want many parallel clients (20+) and lets itself
be balanced.
fhd26u7, 4k12u7: Simulates either encoder or decoder with VCS1
(HEVC) dependency and some balancing VCS usage. Needs fewer
clients (3-6).
hd01, hd17i4: Mostly RCS limited targetting maximum execution
speed for a single client. Must not be hampered by incorrect
balancing decisions.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Last step has to be a batch for the implicit sync to make sense.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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This enables media balancing workloads to be ran on GT2 SKUs.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Multiple dependencies separated by forward slashes are now supported.
Some media workloads also updated to use this for better efficiency.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Put the batch in exec object array last instead of moving it
after checking have there been any dependencies requested.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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Workloads generated from a high level description of how
things usually work in the transcoding world.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
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One copy and paste error sneaked in the no reloc changes.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
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Tool which emits batch buffers to engines with configurable
sequences, durations, contexts, dependencies and userspace waits.
Unfinished but shows promise so sending out for early feedback.
v2:
* Load workload descriptors from files. (also -w)
* Help text.
* Calibration control if needed. (-t)
* NORELOC | LUT to eb flags.
* Added sample workload to wsim/workload1.
v3:
* Multiple parallel different workloads (-w -w ...).
* Multi-context workloads.
* Variable (random) batch length.
* Load balancing (round robin and queue depth estimation).
* Workloads delays and explicit sync steps.
* Workload frequency (period) control.
v4:
* Fixed queue-depth estimation by creating separate batches
per engine when qd load balancing is on.
* Dropped separate -s cmd line option. It can turn itself on
automatically when needed.
* Keep a single status page and lie about the write hazard
as suggested by Chris.
* Use batch_start_offset for controlling the batch duration.
(Chris)
* Set status page object cache level. (Chris)
* Moved workload description to a README.
* Tidied example workloads.
* Some other cleanups and refactorings.
v5:
* Master and background workloads (-W / -w).
* Single batch per step is enough even when balancing. (Chris)
* Use hars_petruska_f54_1_random IGT functions and see to zero
at start. (Chris)
* Use WC cache domain when WC mapping. (Chris)
* Keep seqnos 64-bytes apart in the status page. (Chris)
* Add workload throttling and queue-depth throttling commands.
(Chris)
v6:
* Added two more workloads.
* Merged RT balancer from Chris.
v7:
* Merged NO_RELOC patch from Chris.
* Added missing RT balancer to help text.
TODO list:
* Fence support.
* Batch buffer caching (re-use pool).
* Better error handling.
* Less 1980's workload parsing.
* More workloads.
* Threads?
* ... ?
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Rogozhkin, Dmitry V" <dmitry.v.rogozhkin@intel.com>
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In order to bend over backwards to keep supporting Android.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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This reverts commit 25fbae15262cf570e207e62f50e7c5233e06bc67, restoring
commit 301ad44cdf1b868b1ab89096721da91fa8541fdc
Author: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Date: Thu Mar 2 10:37:11 2017 +0100
lib: Open debugfs files for the given DRM device
with fixes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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This reverts commit 301ad44cdf1b868b1ab89096721da91fa8541fdc.
When a render-only device is opened and gem_quiescent_gpu is called, we
need to use the debugfs dir for the master device instead.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
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When opening a DRM debugfs file, locate the right path based on the
given DRM device FD.
This is needed so, in setups with more than one DRM device, any
operations on debugfs files affect the expected DRM device.
v2: - rebased and fixed new API additions
v3: - updated chamelium test, which was missed previously
- use the minor of the device for the debugfs path, not the major
- have a proper exit handler for calling igt_hpd_storm_reset with the
right device fd.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
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Fix compiler warning about I915_EXEC_FENCE_OUT definition/redefinition
as it is defined in libdrm/i915_drm.h:890:0
gem_latency.c:48:0: warning: "I915_EXEC_FENCE_OUT" redefined
#define I915_EXEC_FENCE_OUT (1 << 17)
^
In file included from ../lib/intel_batchbuffer.h:6:0,
from ../lib/drmtest.h:39,
from ../lib/igt.h:27,
from gem_latency.c:31:
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
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Lots of test cases are re-declaring this.
v2: Remove definition in benchmarks/gem_syslatency.c
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
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Also re-sort the file.
Signed-off-by: Petri Latvala <petri.latvala@intel.com>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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In the middle of a line of double calculations is (int * int) and a
potential overflow.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Just a silly benchmark to stress prime_fd_to_handle and
prime_handle_to_fd.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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benchmarks/ doesn't have the same automagic .gitignore so add the
missing ones.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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The benchmark was failing with:
gem_busy.c:158:8: error: implicit declaration of function 'intel_gen'
is invalid in C99 [-Werror,-Wimplicit-function-declaration]
gen = intel_gen(intel_get_drm_devid(fd));
The root cause was due to the local lib directory not being specified
in benchmarks/Android.mk, resulting in intel_chipset.h from drm being
used instead.
This patch adds the lib path to the LOCAL_C_INCLUDES
Signed-off-by: Derek Morton <derek.j.morton@intel.com>
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
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Instead of causing each engine to execute serially (and so only testing
on fence underneath the sync_file) merge them all together (as we do for
the other interfaces).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Useful for comparing the cost of explict fences versus implicit.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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And include poll(dmabuf) for comparison.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Makfile.sources
Replace the automake specific name of listings in Makefile.sources
with something not automake specific.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Use the HAS_INTEL automake flag to avoid building benchmarks that won't
compile unless libdrm_intel is available in the build system.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Primarily to check that we have the WC read/write disparity.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Currently, we look at the throughput for submitting a read batch to a
single engine or any. The kernel optimises for this by allowing multiple
engine to read at the same time, but writes are exclusive to a single
engine. So lets try to measure the impact of inserting the barriers
between writes on different engines.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Oops, because -nightly doesn't handle 64bit alignments correctly, this
was not working quite as expected.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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If we specify an unobtainable alignment (e.g, 63bits) the kernel will
eviction the object from the GTT and fail to rebind it. We can use this,
to measure how long it takes to move objects around in the GTT by
running execbuf followed by the unbind. For small objects, this will be
dominated by the nop execution time, but for larger objects this will be
ratelimited by how fast we can rewrite the PTE.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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v2: Initially added Werror by default. Make it optional so it doesn't
break android build and (potential) distros maintaing the package
(Hinted by Damien Lespiau).
--enable-werror will enable -Werror compiler flag.
Signed-off-by: Marius Vlad <marius.c.vlad@intel.com>
Acked-by: Damien Lespiau <damien.lespiau@intel.com>
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In theory, we need to only worry about concurrent mmio writes to the
same cacheline. So far, disabling the spinlock hasn't hung the machine.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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