| Age | Commit message (Collapse) | Author |
|---|
|
Currently when children processes try to communicate to not existing
allocator thread they got crash with vague SIGSEGV.
Adding readyness flag and detailed explanation in assert should hint
the developer to add missing intel_allocator_multiprocess_start|stop)
functions.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
|
|
For DG2 and beyond regions alignment may vary so many tests would need
to be rewritten to handle this constraint. As Ashutosh noticed most of
tests can use safe alignment as a default.
Adopt intel-allocator to use safe or user defined power-of-two alignment.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Suggested-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
|
|
To use spinners with no-reloc we need to alloc offsets for them
from already opened allocator. As we don't know what strategy
is chosen for open (likely HIGH_TO_LOW for SIMPLE allocator) we
want to overwrite it for spinners (there's expectation they
will reside on low addresses).
Extend allocator API adding intel_allocator_alloc_with_strategy()
to support spinners rewriting.
v2: add change in api_intel_allocator test to compile properly
whole series.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Petri Latvala <petri.latvala@intel.com>
|
|
For discrete gens we have to cease of using relocations when batch
buffers are submitted to GPU. On cards which have ppgtt we can use
softpin establishing addresses on our own.
We added simple allocator (taken from Mesa; works on lists) and
random allocator to exercise batches with different addresses. All
of that works for single VM (context) so we have to add additional
layer (intel_allocator) to support multiprocessing / multithreading.
For main IGT process (also for threads created in it) intel_allocator
resolves addresses "locally", just by mutexing access to global
allocator data (ctx/vm map). When fork() is in use children cannot
establish addresses on they own and have to contact to the thread
spawned within main IGT process. Currently SysV IPC message queue was
chosen as a communication channel between children and allocator thread.
Child calls same functions as main IGT process, only communication path
will be chosen instead of acquiring addresses locally.
v2:
Add intel_allocator_open_full() to allow user pass vm range.
Add strategy: NONE, LOW_TO_HIGH, HIGH_TO_LOW passed to allocator backend.
v3:
Child is now able to use allocator directly as standalone. It only need
to call intel_allocator_init() to reinitialize appropriate structures.
v4:
Add pseudo allocator - INTEL_ALLOCATOR_RELOC which just increments
offsets to avoid unnecessary conditional code.
v5:
Alter allocator core according to igt_map changes.
v6:
Add internal version __intel_allocator_alloc() to return
ALLOC_INVALID_ADDRESS without assertion.
v7:
Add libatomic for linking libigt library. It is required on some
archs, like mips.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Petri Latvala <petri.latvala@intel.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Petri Latvala <petri.latvala@intel.com>
|
