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In few tests we got some MI_* duplicates (MI_MATH for example).
Add common definitions in intel_reg.h and remove local definitions
in the tests.
v2: Definitions MI_LOAD_REGISTER_MEM_GEN8 was removed so from now
on user will need to encode length on it own. :
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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Add support for DG2 flat ccs framebuffers with tile-4.
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Jeevan B <jeevan.b@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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As opposed to other GEN12 platforms ADLP provides a way to program the
stride of CCS surfaces independently of the main surface stride (within
the corresponding limit of the preceeding and succeeding power-of-two
values of the main surface). Using that feature we can remove the
restriction on the strides of both the main and CCS surfaces, making the
ADLP CCS FB uAPI (FB modifiers) identical to that of TGL.
Remove the stride alignment restrictions and the special casing of the
ADLP AUX pagetable setup - which was only required assuming the pre-ADLP
fixed CCS stride logic.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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To avoid confusion with intel_buf_bo_size() which for some buffers
can return size not equal to underlying gem bo size rename it to
intel_buf_size().
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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Having a kernel support for this, CCS framebuffer strides don't need to
be power-of-two aligned, the kernel will auto-pad the stride.
Only the main surface tiles can be remapped and the AUX surface must be
generated to align with the POT padded main surface stride. Add the
required AUX pagetable programming for this.
Since the AUX pagetable has a granularity of 64 kbytes on the main
surface, mapped by one AUX PTE, the main surface stride must be either 8
tiles, or the stride must be aligned to 16 tiles.
v2:
- Remove the restriction on plane size and update the code comment on
the CCS stride.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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Use the AYUV encodings for both the surface format and the AUX page
table tag. This matches the layout of XYUV8888, except for the missing
alpha channel, and this is the closest format I found in bspec.
Tested by igt/kms_plane and kms_ccs.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
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Refactor the intel-bb interface to introduce the IGT allocator for
specifying the position of objects within the ppGTT.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Petri Latvala <petri.latvala@intel.com>
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For fast clear we haven't defined source buffer. Therefore, we only
need to initialize only destination aux pagetable.
v2: Cleaner solution proposed by Imre (Imre)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
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Use intel_bb as main batch implementation to remove libdrm dependency.
Rewrite all pipelines to use intel_bb and update render|vebox_copy
function prototypes.
Note that this will introduce compile failures into the indiviual users
until they are transitioned over to the new interface in the following
patches. The process is completed with "lib/rendercopy_bufmgr: remove
rendercopy_bufmgr."
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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../lib/intel_aux_pgtable.c: In function ‘ptr_mask’:
../lib/intel_aux_pgtable.c:14:12: warning: right shift count >= width of type [-Wshift-count-overflow]
14 | (~0UL >> (BITS_PER_LONG - 1 - (e))))
| ^~
../lib/intel_aux_pgtable.c:138:9: note: in expansion of macro ‘BITMASK’
138 | return BITMASK(GFX_ADDRESS_BITS - 1, ld->entry_ptr_shift);
| ^~~~~~~
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Add the missing bits to the Vebox copy and AUX pagetable helpers for
copying YUV FBs with the Vebox engine.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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UV FBs have two color surfaces so extend the igt_buf struct accordingly
to support blitting such FBs.
The patch is produced with the coccinelle patch below.
No functional changes.
@@
@@
struct igt_buf {
...
- uint32_t stride;
...
- uint32_t size;
+ struct {
+ uint32_t stride;
+ uint32_t size;
+ } surface[2];
...
};
@@
struct igt_buf b;
@@
<...
(
- b.stride
+ b.surface[0].stride
|
- b.size
+ b.surface[0].size
)
...>
@@
struct igt_buf *b;
@@
<...
(
- b->size
+ b->surface[0].size
|
- b->stride
+ b->surface[0].stride
)
...>
@@
identifier I;
expression E1;
expression E2;
@@
(
struct igt_buf I = {
- .size = E1,
- .stride = E2,
+ .surface[0] = {
+ .size = E1,
+ .stride = E2,
+ },
};
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struct igt_buf I = {
- .size = E1,
+ .surface[0] = {
+ .size = E1,
+ },
};
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struct igt_buf I = {
- .stride = E1,
+ .surface[0] = {
+ .stride = E1,
+ },
};
)
v2:
- Rebase on latest upstream. (Mika)
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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YUV FBs have two CCS surfaces so extend the igt_buf struct accordingly
to support blitting such FBs.
The patch is produced with the coccinelle patch below, along with some
w/s fixup.
No functional change.
@@
@@
struct igt_buf {
...
struct {
uint32_t offset;
uint32_t stride;
- } aux;
+ } ccs[2];
...
};
@@
struct igt_buf *b;
@@
(
- b->aux.offset
+ b->ccs[0].offset
|
- b->aux.stride
+ b->ccs[0].stride
)
@@
struct igt_buf b;
@@
(
- b.aux.offset
+ b.ccs[0].offset
|
- b.aux.stride
+ b.ccs[0].stride
)
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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Use the igt_buf compression field to determine the compression type for
a buffer, instead of the fact that AUX stride is set. We need to look at
the former one anyway to distinguish between compression types.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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To produce surfaces that are compressed using the media compression
format we need to use one of the media engines. The simplest way for
this is to use the vebox engine's tiling convert command, so add support
for this.
v2:
- Rebase on latest igt. (Mika)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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We're only using the first instance of the render engine, but the
standard way on GEN12 to read/write engine registers is to depend on the
MMIO remapping to select the proper instance based on which command
streamer the read/write instruction was run from.
Enable the MMIO remapping to align with the standard way to do reg
read/writes.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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The AUX pagetables need to be set up for blits using the vebox engine
too, so move the related helper functions to intel_aux_pgtable.c.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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On GEN12+ the AUX CCS surfaces required by the render and media
compression must be specified by a 3 level page table directory, which
translates the main surface graphics address to the AUX CCS surface
graphics address. For this purpose add support for creating a GEM buffer
to translate the linear surface address range to the linear AUX surface
address range.
The buffers containing the main surface must be pinned down, since the
directory table entry indices depend on the surface address, and they
must be 64kB aligned. The page table can be relocated OTOH, so allow
that and emit the required relocation entries.
v2:
- Make level variables to be 0 based (l1..l3 -> level=0..2).
- Add missing drm_intel_bo_set_softpin_offset() stub to fix build on
non-Intel archs.
- Fix missing offsets in reloc entries of already bound objects. (Chris)
- Randomize pin offsets, to try to avoid eviction. (Chris)
- Remove redundant MI_NOOPS around MI_LOAD_REGISTER_MEM
- Stop using explicit reloc cache domains, as these don't make sense on
GEN12 anyway. (Chris)
- Fix missing autotools support. (Chris)
- s/igt_aux_pgtable/intel_aux_pgtable/, since the functionality is Intel
specific. (Chris)
v3:
- Make sure all objects with an AUX surface are pinned.
v4:
- s/MI_LOAD_REGISTER_MEM/MI_LOAD_REGISTER_MEM_GEN8/ (Chris)
- Fix using buf->bo->size instead of buf->size when finding a free
range for a pinned obj.
- Fix alignment of the reserved space start for a pinned obj.
- Move gen12_emit_aux_pgtable_state() to its logical spot.
v5:
- Fix reloc emit call, passing a relative instead of absolute target
offset. (Chris)
- Fix off-by-one error when generating a random offset for pinned objs.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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