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Use intel_bb as main batch implementation to remove libdrm dependency.
Rewrite all pipelines to use intel_bb and update render|vebox_copy
function prototypes.
Note that this will introduce compile failures into the indiviual users
until they are transitioned over to the new interface in the following
patches. The process is completed with "lib/rendercopy_bufmgr: remove
rendercopy_bufmgr."
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Dominik Grzegorzek <dominik.grzegorzek@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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To produce surfaces that are compressed using the media compression
format we need to use one of the media engines. The simplest way for
this is to use the vebox engine's tiling convert command, so add support
for this.
v2:
- Rebase on latest igt. (Mika)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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The AUX pagetables need to be set up for blits using the vebox engine
too, so move the related helper functions to intel_aux_pgtable.c.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
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On GEN12+ the AUX CCS surfaces required by the render and media
compression must be specified by a 3 level page table directory, which
translates the main surface graphics address to the AUX CCS surface
graphics address. For this purpose add support for creating a GEM buffer
to translate the linear surface address range to the linear AUX surface
address range.
The buffers containing the main surface must be pinned down, since the
directory table entry indices depend on the surface address, and they
must be 64kB aligned. The page table can be relocated OTOH, so allow
that and emit the required relocation entries.
v2:
- Make level variables to be 0 based (l1..l3 -> level=0..2).
- Add missing drm_intel_bo_set_softpin_offset() stub to fix build on
non-Intel archs.
- Fix missing offsets in reloc entries of already bound objects. (Chris)
- Randomize pin offsets, to try to avoid eviction. (Chris)
- Remove redundant MI_NOOPS around MI_LOAD_REGISTER_MEM
- Stop using explicit reloc cache domains, as these don't make sense on
GEN12 anyway. (Chris)
- Fix missing autotools support. (Chris)
- s/igt_aux_pgtable/intel_aux_pgtable/, since the functionality is Intel
specific. (Chris)
v3:
- Make sure all objects with an AUX surface are pinned.
v4:
- s/MI_LOAD_REGISTER_MEM/MI_LOAD_REGISTER_MEM_GEN8/ (Chris)
- Fix using buf->bo->size instead of buf->size when finding a free
range for a pinned obj.
- Fix alignment of the reserved space start for a pinned obj.
- Move gen12_emit_aux_pgtable_state() to its logical spot.
v5:
- Fix reloc emit call, passing a relative instead of absolute target
offset. (Chris)
- Fix off-by-one error when generating a random offset for pinned objs.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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