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2014-04-29Add Cherryview PCI IDsVille Syrjälä
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-03-22lib: remove uncessary #includes from headersDaniel Vetter
Only include what the header itself needs. The big fish here is intel-gpu-tools.h. More will follow. One ugly thing removed here is the duplicated GEN6_TD_CTL #define, one of which was broken. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-22lib/intel_chipset: api docsDaniel Vetter
Unfortunately gtkdoc doesn't pick up the intel_pch enum. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-22lib/intel_chipset: intel_ prefix for pch globalDaniel Vetter
Just a bit better namespacing. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-22lib: consolidate chipset helpers in intel_chipset.[hc]Daniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-06bdw: Add gen8 to the IS_9XX() macroDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06pciid/bdw: Add Broadwell PCI idsBen Widawsky
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06chipset: IS_I9XX macroBen Widawsky
This isnt useful in IGT, but it will allow us to keep the merge process with libdrm simpler. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-06-05intel_chipset: Adding more reserved PCI IDs for Haswell.Rodrigo Vivi
At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2013-06-05intel_chipset: Fix Haswell GT3 names.Rodrigo Vivi
When publishing first HSW ids we weren't allowed to use "GT3" codname. But this is the correct codname and Mesa is using it already. So to avoid people getting confused why in Mesa it is called GT3 and here it is called GT2_PLUS let's fix this name in a standard and correct way. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-08lib: Remove the execution bit of intel_chipset.hDamien Lespiau
2013-04-24tests: storedw on VEBOXXiang, Haihao
v2 (Ben): Define LOCAL_I915_EXEC_VEBOX Small copyright fixes Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Zhong Li <zhong.li@intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-03-22lib: fix HAS_PCH_SPLIT checkPaulo Zanoni
So HAS_PCH_SPLIT on't be true on VLV. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2013-03-03intel_chipset: Fix Haswell CRW PCI IDs.Kenneth Graunke
The second digit was off by one, which meant we accidentally treated GT(n) as GT(n-1). This also meant no support for GT1 at all. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-19intel_chipset: Add multiple inclusion guards into intel_chipset.hVille Syrjälä
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-19intel_chipset: Use parens around macro argumentsVille Syrjälä
Protect the macro argument evaluations with parens. This is already touching most lines, so while at it, fix up all white space to uniform style throughout the file. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-02-02add more VLV PCI IDsJesse Barnes
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-08-21tools: Added intel_dpio_read and intel_dpio_writeVijay Purushothaman
In Valleyview the DPLL and lane control registers are accessible only through side band fabric called DPIO. Added two tools to read and write registers residing in this space. v2: Moved the core read/write functions to lib/intel_dpio.c based on Ben's feedback Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-07lib: add more Haswell PCI IDsPaulo Zanoni
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
2012-06-11add VLV PCI IDJesse Barnes
This allows the tests to run on the prototype boards.
2012-04-28chipset: accidentally left the old IS_GEN7 macroBen Widawsky
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2012-04-25chipset updatesBen Widawsky
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2011-12-06tests/gem_partial_pwrite_pread: don't trash gtt unnecessarilyDaniel Vetter
On chips that don't have a unmappable gtt part it's utterly pointless. Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-09-12tests: basic ring<->cpu and ring<->ring testsDaniel Vetter
Using a dummy reloc that doesn't matter to trick the kernel into synchroizing the rings. v2: properly apply MI_NOOP workaround to MI_FLUSH_DW and switch to MI_COND_BATCH_BUFFER_END as a dummy command on the render ring to avoid PIPE_CONTROL errata. v3: somebody clever decided that in C, you cound from 1, i.e. I915_EXEC_RENDER == 1. It works now ... Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2011-07-28intel-gpu-tools/range handling: register range handlingBen Widawsky
Hooks to allow safe accesses from userspace. Can revert to old behavior by using unsafe access.
2011-05-17Add Ivybridge support to intel_gpu_dump and the BLT tests.Eric Anholt
2011-05-10Add Ivybridge device IDsJesse Barnes
Makes the reg dumper work better.
2011-02-14Remove confusing use of IS_9XXChris Wilson
... and test for what we mean instead. Reported-by: Diego Celix <dcelix@gmail.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-06Fix typo excluding Ironlake from IS_INTELChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-01Search for the first Intel dri device.Chris Wilson
This is vital in a multi-GPU system so that we only test the Intel card and not the discrete GPUs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-27Add all sandybridge device idsZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-06-30intel_reg_dumper: add some 945 MI reg dumpingJesse Barnes
2010-02-25Add support for Sandybridge mobile chipset.Eric Anholt
2010-02-25Add some initial definitions for Sandybridge.Eric Anholt
2009-09-08Add support for new chipsXiang, Haihao
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2009-03-27Add intel_stepping from the 2D driver.Eric Anholt
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 17:23:25 +0000