Age | Commit message (Collapse) | Author |
|
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.
This is also the new Spec style what makes the review much
more easy and straightforward.
This is a copy of merged i915's
commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")
v2: Based on Anusha's kernel clean-up.
v3: Add kernel commit id for reference.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
|
|
Cannonlake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.
It is Gen10.
Let's start by adding the platform definition based on previous
platforms.
On following patches we will start adding PCI IDs and the
platform specific changes.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
|
|
Just following the spec and adding these extra IDs.
v2: update IDs following the kernel commit:
b056f8f3d6b900e8afd19f312719160346d263b4 (Chris)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clint Taylor <clinton.a.taylor@intel.com>
|
|
Coffeelake is a Intel® Processor containing Intel® HD Graphics
following Kabylake.
It is Gen9 graphics based platform on top of CNP PCH.
On following patches we will start adding PCI IDs and the
platform specific changes.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
|
|
Sync to
commit 77a9e13b5a3c9c0cbd9e672e55970e7358a1a482
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Mar 13 11:26:09 2017 +0000
drm/i915: Add i810/i815 pci-ids for completeness
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
|
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
|
|
Copy the include/drm/i915_pciids.h file from following kernel commit,
which includes Geminilake PCI IDs.
commit 8363e3c3947d0e22955f94a6a87e4f17ce5087b4
Author: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Date: Thu Nov 10 17:23:08 2016 +0200
drm/i915/glk: Add Geminilake PCI IDs
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
|
|
gtkdoc can't handle aliasing, so let's rename the intel_device_info
function.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
|
|
A spelling fix patch must always include one mistake. What does that
mean when the patch only contains a single change?
Even though I had the bspec open, I still managed to confuse a 'li' for
'll'
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
|
aaglelake, the Scottish version.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
|
Instead of a large if-chain for matching devid to GT, we can just
compute it directly from the encoded devid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|
|
Several years ago we made the plan of only having one canonical source
for i915_pciids.h, the kernel and everyone importing their definitions
from that. For consistency, we style the intel_device_info after the
kernel, most notably using a generation mask and a per-codename bitfield.
This first step converts looking up the generation for a devid tree from
a massive if(devid)-chain to a (cached) table lookup.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
|