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Unify the MOCS to be more consistently across the platforms.
Currently gen8+ are specifyig UC whereas earlier platforms
generally use PTE. Let's make everyone more or less specify
L3+PTE.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Allow copying between fp16 surfaces. We'll use the FLOAT
surface format since that's all the display supports currently.
Hopefully the hardware gives us a 1:1 copy, at least if
the input doesn't contain crazy infs/nans etc. We could
choose UNORM instead but that won't work for eventually
exposing fp16+ccs. Although we do need to replace the
simple bpp value with a more specific format type to get
10bpc+ccs working as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Sprinkle some asserts into rendercopy to make sure we don't try
to exceed the render engine surface size/stride limitations.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Set up the surface state accordingly to support Yf/Ys tiling.
>From DK:
Rebase.
Move support to gen-9 surface state
Cc: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Create a gen9 specific struct so that the gen-9+ Yf/Ys tiling bits can be
added there.
Suggested-by: Katarzyna Dec <katarzyna.dec@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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To handle drawing 16 bpp formats correctly with odd x/w, we need to
use the correct bpp to rendercopy. Now that everything sets bpp in
igt_buf, fix the rendercopy support to use it and set the correct
format.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
[mlankhorst: Add assert(src->bpp == dst->bpp)]
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This patch introduces a render copy shader for GEN11.
The plumbing is same as with GEN9, so we can reuse it, extracting the
common parts, and wrapping it in GEN-specific helpers.
v2: Added gen11 shader source path next to its binary form
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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In shaders/ directory we got Intel specific information. As igt
is a project for more vendors, let's move this directory to
lib/i915.
v2: Changed shaders directory path in library files comments.
Signed-off-by: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Kalamarz Lukasz <lukasz.kalamarz@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Instead of using definitions duplicated in gen7_render header,
we should use the oldest definition that is working with chosen
gen. This patch reuse gen6 definitons if registers/fields/shifts
that were introduced in other genX_render headers.
v3: Rebase and checkpatch
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Populate the gen8+ SURFACE_STATE aux bits correctly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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gen8 introduces 48 bit virtual addresses. Set both dwords correctly
as otherwise the presumed_offset will not match what we actually
have stored in the surface state if the buffer is located somewhere
above 4GiB.
I guess we're not currently using 48bit addresses with rendercopy?
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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No one generally needs to modify the igt_bufs we pass around,
so make them const.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Remove the hardcoded dword offsets for the relocs and instead rely
fully on intel_batchbuffer_subdata_offset().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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The shaders/blit.g7a has weird artefacts (random pixel kill) when
drawing to an odd destination coordinate. Rather than debug the
issue with the asm/assembler, replace the kernel with the one used by
SNA for simple copies.
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> #chv, skl
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
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This patch cleans gen9 header from a duplicate definition
and it dependency.
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ewelina Musial <ewelina.musial@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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This patch implements some changes in gen8_render header and
all files that include it. Renamed all definition that were
introduced in that file with prefix GEN8_* instead of
previous GEN's one if they were not implemented there,
otherwise dropped duplicates. Modified include to use
gen7_render header instead of gen6.
v2: Fixed commit message
v3: fixed typo in commit msg
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ewelina Musial <ewelina.musial@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Instead of using definitions duplicated in gen7_render header,
we should use the oldest definition that is working with
chosen gen. This patch reuses gen6 definitons if
registers/fields/shifts that were reintroduced in
other genX_render headers.
v2: Fixed commit message
v3: fixed typos in commit msg
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ewelina Musial <ewelina.musial@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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This patch is renaming all surfaceformat registers to use
names introduced in surfaceformat.h instead of using
per gen definitions
v2: Drop GEN_ from register names. Applied that to
other libs.
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
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Batch functions were copy/pasted across several libs.
With moving it into intel_batchbuffer lib test can now be
easly maintained without worrying that we forgot to modify
older version of lib.
v2: Added documentation into lib and rebased patch
v3: Fixed typos and rebased patch
v4: Fixed documentation issues
v5: Rename, clean up of leftovers from previous version
and documentation polishing
v6: Fixing assert
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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No functionality related to aub is provided by libdrm aside from
intel_aub.h which somewhat defines the file format. Move the
header into this project to ease aub-related development.
Signed-off-by: Scott D Phillips <scott.d.phillips@intel.com>
Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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Emil prefers if the approach in v2 is used (it was sent around the time
v1 had been applied).
This reverts commit 438c8d7c688780337d271016d84a69aab0474097.
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File is provided by the libdrm_intel package which is optional. Since we
already have a local copy of the file, we might as well use it ;-)
Cc: Brian Starkey <brian.starkey@arm.com>
Reported-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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From Gen9, by default push constant command is not committed to the shader unit
untill the corresponding shader's BTP_* command is parsed. This is the
behaviour when set shader is enabled. This patch updates the batch to follow
this requirement otherwise it results in gpu hang.
Set shader need to be disabled if legacy behaviour is required.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89959
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Tested-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
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Don't set the size of bindless surface state on rendercopy.
And as of doing so, take into account the workaround for setting
the command size.
This was tried during hunting for
https://bugs.freedesktop.org/show_bug.cgi?id=89959. But no
impact was found.
Cc: Arun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
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Add rules to fix unused-result warnings when compiling with
_FORTIFY_SOURCE defined and apply them to the library and tests.
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
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Without emitting the default 3DSTATE_WM_DEPTH_STENCIL state the test
will fail.
Signed-off-by: Imre Deak <imre.deak@intel.com>
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After applying the commit(982f7eb238a0898c456e0574dee7c4507738d75f), the
OUT_RELOC is updated on Broadwell and later, which is to handle the
64-bit field of gfx address internally. In such case some commands
should be fixed, otherwise GPU hang will be triggered when running
rendercopy. (It is already fixed on Broadwell)
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Signed-off-by: Thomas Wood <thomas.wood@intel.com>
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A value less than 4 might result in GPU hang on simulation
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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This is from that on BDW. Without it, the pixel pipeline can't work well.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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This is ported from that on BDW.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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This is ported from that on BDW.
v2: Only bump the prefix when we need to program the instruction
differently with the previous generations.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
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SBE has now to be explicitely told which channels of which components
are used by the pixel shader.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
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This is to ensure the "Component Packing Enable" bit is set to 0.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
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v2 (Ben): Rebased on:
commit ea11d103e0617e33bce6f11328521d15b13422b0
Author: Oscar Mateo <oscar.mateo@intel.com>
Date: Tue Nov 12 11:50:35 2013 +0000
build: list all test/tool/lib source files in their own Makefile.sources
v3: (Ben): Rebased on the doc/API rework. Probably needs review
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
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