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For DG2 and beyond regions alignment may vary so many tests would need
to be rewritten to handle this constraint. As Ashutosh noticed most of
tests can use safe alignment as a default.
Adopt intel-allocator to use safe or user defined power-of-two alignment.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Suggested-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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Save the opts with which the spin was created
as part of the spin so that the opts are available
in case they are needed.
Signed-off-by: Jasmine Newsome <jasmine.newsome@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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The library provides igt_device_get_pci_device() function that allows to
get access to a PCI device from an open DRM device file descriptor. It
can be used on VF devices as long as a DRM driver is bound to them.
However, SR-IOV tests may want to exercise VF PCI devices created by a PF
without binding any DRM driver to them.
While keeping the API of igt_device_get_pci_device() untouched, extend API
of its underlying helper __igt_device_get_pci_device() with an extra
argument for specifying VF ID of the requested PCI device and expose this
function as public.
v2: refresh on top of IGT libpciaccess wrappers and drop previously added
but no longer needed error unwind path and recommendations for users
on calling pci_system_cleanup() after use (Chris),
- fix incorrect validation of snprintf() result and misaligned
formatting of igt_warn_on_f() arguments.
Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Reviewed-by: Chris Wilson <chris.p.wilson@intel.com>
[jkrzyszt: DOC fix and wording improvement]
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This reverts commit c220c60bb4679e2e9cdf8accbf90f888e6819456.
Incorrect version of the patch has been pushed, sorry.
Signed-of-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
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The library provides igt_device_get_pci_device() function that allows to
get access to a PCI device from an open DRM device file descriptor. It
can be used on VF devices as long as a DRM driver is bound to them.
However, SR-IOV tests may want to exercise VF PCI devices created by a PF
without binding any DRM driver to them.
While keeping the API of igt_device_get_pci_device() untouched, extend API
of its underlying helper __igt_device_get_pci_device() with an extra
argument for specifying VF ID of the requested PCI device and expose this
function as public.
While being at it, fix pci_system_cleanup() not called on errors and
instruct users to call it for symmetry when the obtained struct pci_device
is no longer needed.
Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
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Kmod igt library functions like igt_i915_driver_{load, unload}
uses process exit IGT_EXIT_{FAILURE, SKIP, SUCCESS} return values.
Let these function return actual return values
from returned igt_kmod_{load, unload} functions.
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Suggested-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
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Multiple calls to igt functions using pci_system_init() provided by
libpciaccess result in memory leaking if not followed by its counterpart
pci_system_cleanup() before next use. On the other hand, calling
pci_system_cleanup() can affect other users which still depend on global
data initialized by pci_system_init().
Introduce safe IGT wrappers around those libpciaccess functions and use
those wrappers in IGT library and tests.
Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
[jkrzyszt: shorten excessive long name of hidden variable (Chris)]
Reviewed-by: Chris Wilson <chris.p.wilson@intel.com>
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Add silent __igt_i915_driver_unload(), which will not
print any warning in case of passed argument is NULL.
This will be used by some igt test, which marks i915
module busy and expect i915 module unload to fail.
These tests requires a silent lib function to unload
the i915 module correctly.
v2:
- Change commit log. [Ashutosh]
- Change whom to who. [Ashutosh]
- When aux audule unload fails mark who with module name. [Ashutosh]
- Keep same type of return type in
__igt_i915_driver_unload(). [Ashutosh]
Cc: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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FlatCCS is discrete DG2+ feature and is worth to add the flag which
enables it. Add HAS_FLATCCS() macro which should make conditional code
simpler and compact.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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Before pciids will land in the kernel and then is merged to IGT we need
to add them locally to unblock compilation and testing staged kernels.
We can use some hybrid solution where intel_device_info takes official
pciids from i915_pciids.h and not official from i915_pciids_local.h.
Such strategy allows us to decrease code changes in the libraries/tests
especially where IS_GENx() or IS_<machine>() macros are in use.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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[Why & How]
Add new igt test amd_ilr for ilr fature.
ILR (Intermediate Link Rate) is the feature introduced in eDP1.4.
For saving power purpose, it provides finer granularity of link
rates to optimize the allocated bandwidth needed for resolutions of
eDP panels.
This new igt test "amd_ilr" validates ILR feature from two perspective:
* Test if we can sucessfully train link rate at all supported ILRs
* Iterate over all modes to see if we do use ILR to optimize the link
rate to light up the mode.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
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[Why & How]
Link rate is shown as hexadecimal not decimal by the debugfs entry.
Correct the parameter from 10 to 16.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
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After subtest ends, due to normal flow or after fail by
igt_assert, igt_core inits intel_allocator before next subtest,
and this makes allocator handle keeped in intel_batchbuffer
invalid. Moreover any call to intel_allocator can result in
fail as there are no allocators until first allocator_open.
Add tracking intel_butchbuffer if it is using allocator and
recreate its allocator handle and offsets from igt_core before
next subtest.
Add flag for turn on tracking and a helper function for it with
default value off. It will not change behaviour of already used
tests. Use case is for standalone runs with many subtests like
gem_concurrent_blit.
v2: add tracking flag with default off (Zbigniew)
v3: add and correct functions descriptions (Zbigniew)
Signed-off-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
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Various tests want to configure engine properties such as pre-emption
timeout and heartbeat interval. Some don't bother to restore the
original values again afterwards. So, add a helper to make it easier
to do this.
v2: Fix for platforms with no pre-emption capability.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
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A lot of tests use almost identical code for creating a batch buffer
which does a single write to memory and another is about to be added.
Instead, move the most generic version into a common helper function.
Unfortunately, the other instances are all subtly different enough to
make it not so trivial to try to use the helper. It could be done but
it is unclear if it is worth the effort at this point. This patch
proves the concept, if people like it enough then it can be extended.
v2: Fix up object address vs store offset confusion (with help from
Zbigniew K).
v3: Cope with >32bit store_offset (review feedback from Matthew Brost).
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
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Some of the IGT framework relies on receving a uevent when a hang
occurs. So add a test that this actually works.
While testing this, noticed that hangs could sometimes be missed
because the uevent was (presumably) still in flight by the time the
handler was de-registered. So add an extra delay during cleanup to
give the uevent chance to arrive.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
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The above function was checking for valid rings via the old interface.
The new scheme is to check for engines on contexts as there are now
more engines than could be supported.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
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With era of new gens we're enforced to use no-reloc (softpin). This
brings few problems like vm range limitations which were well solved
by the kernel. This can be handled also in userspace code by adding
gen related conditionals or by trying to detect the constraints.
Lets try to do this dynamically and detect safe start offset and
alignment for each memory region we got. This should be universal solution
regardless hw limitations and bugs. As such detection is not lightweight
technique add also some caching structures to handle consequtive calls
about same data.
v2: unify cache
v3: move allocation of cache entry out of mutex
v4: remove assert on allocation newentry, just skip adding to cache
v5: fix function documentation (Ashutosh)
v6: remove unnecessary buffers count initialization (Ashutosh)
add 48b flag for pinning object
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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Media samplers are not present on some of Gen11 platforms adding
skip on EHL and JSL as per Bspec.
Bspec:29151
Changes since V1 :
Moved this skip check to igt_get_media_vme_func.[Tony Ye]
CC: Tony Ye <tony.ye@intel.com>
Signed-off-by: Mastan Katragadda <mastanx.katragadda@intel.com>
Reviewed-by: Tony Ye <tony.ye@intel.com>
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RPLS and ADLS use the same OA metrics. Add RPLS support for OA tests.
Resolves: https://gitlab.freedesktop.org/drm/intel/-/issues/4808
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Acked-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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This commit adds a DP DSC test that checks:
* Forces DSC on/off and ensures it is reset properly
* Check DSC slice height property
* Verify various DSC slice dimensions
* Tests various combinations of link_rate + lane_count and logs if DSC
enabled/disabled Tests different bpc settings and logs if DSC is
enabled/disabled
Change since V3:
- Drop useless test
Change since V2:
- Remove IGT_CRTC_DSC_SLICE_HEIGHT crtc property from this commit
Change since V1:
- Rebase
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Choi <Nicholas.Choi@amd.com>
Cc: Mark Yacoub <markyacoub@chromium.org>
Cc: Hayden Goodfellow <hayden.goodfellow@amd.com>
Cc: Hersen Wu <hersenxs.wu@amd.com>
Cc: Roman Li <roman.li@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
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Adding Alder lake N platform definitions
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
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This synchronizes with kernel commit
7e28d0b26759 ("drm/i915/adl-n: Enable ADL-N platform")
to bring in ADL-N PCI IDs.
Acked-by: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
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Adding Raptor lake platform definitions
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Raviteja Goud Talla <ravitejax.goud.talla@intel.com>
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This synchronizes with kernel commit
52407c220c44 ("drm/i915/rpl-s: Add PCI IDS for Raptor Lake S")
to bring in RPL-S PCI IDs.
Acked-by: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
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Even though the best practices for dynamic subtests is to not execute
the dynamic subtest at all instead of skipping, there are a couple of
tests that to the opposite, without an easy way to construct them
along best practices. Accomodate this with fixing the handling of
skipping dynamic subtests so that the result of the containing subtest
becomes a skip also if all dynamic subtests skip, not just when there
are no dynamic subtests.
Signed-off-by: Petri Latvala <petri.latvala@intel.com>
Cc: Arkadiusz Hiler <arek@hiler.eu>
Cc: Jari Tahvanainen <jari.tahvanainen@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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clear_yuv_buffer() checks the size of the plane_size[] to
make sure its greater than the number of planes to avoid
overflows.
The plane_size[] is fixed to two currently.
However some of the formats like YV12 indeed have more than
2 planes in the format_desc[] hence this incorrectly failing
this check.
Increase the size of the plane_size[] to match the correct
max number of planes.
changes in v3:
- use drm_format->num_planes to create the plane_size
- add assert checks for num of planes before memset
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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As Ashutosh noticed I've handled errors from the kernel too wide
packing it to same error bag and returning system memory region in this
case. That's of course is wrong and can lead to return system memory on
discrete if invalid arguments would be passed to the query.
Return previous behavior of query memory regions handling -ENODEV path
individually. For this error lets assume we got kernel which doesn't
support this query yet so returning system memory region is a reasonable
choice because this region exists for all of i915 gens.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reported-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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For stable kernels we get -ENODEV on integrated where gem_create_ext()
call tries to allocate bo in system memory. Instead of asserting this
case we can fallback to gem_create() as this allocation can be resolved
using legacy call.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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For stable kernels we can currently get -ENODEV on integrated gens
when no CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM is set.
Provide system memory region stub to avoid failing on querying
kernel for memory regions.
v2: use offsetof() instead of manual size calculation
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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rename igt_debug_manual_check and patch the igt function
igt_debug_wait_for_keypress() to assert if "all" is supplied.
v2: calling igt_debug_wait_for_keypress() with "all" will assert.
v3: Change igt_assert to igt_assert_f for adding clear log message.
v4: Rebase only.
Signed-off-by: Jeevan B <jeevan.b@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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Tests that reads and/or writes to kernel managed buffers which should be
inaccessible to userspace controlled cmdstream, are indeed inaccessible.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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Split the readN()/writeN() helpers out into an igt_io module, so they
can be re-used by tests.
Signed-off-by: Rob Clark <robdclark@chromium.org>
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[Why]
Mediatek devices have a HW issue with sending their vblank IRQ at the same time interval
everytime. The drift can be below or above the expected frame time, causing the
timestamp to drift with a relatively larger standard deviation over a large sample.
[How]
Filter out the flags TEST_CHECK_TS and TEST_VBLANK_EXPIRED_SEQ from the
tests flags, and restrict sequence and ts checks.
Tested on Jacuzzi (MT8183)
Signed-off-by: Mark Yacoub <markyacoub@chromium.org>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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Add tests to exercise:
1. sw hangcheck timeout
2. gpu fault (hang) recovery
3. iova fault recovery
Signed-off-by: Rob Clark <robdclark@chromium.org>
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A pretty minimal subset compared to what a full gallium driver would
need, but OTOH for igt tests we should only need to emit fairly basic
command stream.
Signed-off-by: Rob Clark <robdclark@chromium.org>
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Add a helper that can be used with, for ex, igt_require() so that tests
can be skipped if the kernel is too old.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
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When doing a primary or sprite plane flip, PSR2 selective fetch code
also adds all the planes including cursor that overlaps with the
area being updated, so this causes legacy cursor API calls to
wait for a pending atomic commit to finish causing tests that do
checks with vblank counters.
So here when running in an Intel platform that has PSR2 selective
fetch enabled, it will switch to PSR1 before executing the subtests.
Because what this whole test mostly wants to do, is check if userspace
can do asynchronous cursors updates.
v2:
- rename functions and add documentation
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2346
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Jouni Hogander <jouni.hogander@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
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The macro is for choosing between two values depending on whether IGT
has been told it's running in simulation mode. The parameter names and
their documentation was the opposite of what actually happened.
The only user, gem_lut_handle, uses the macro correctly, having the
"use this value in simulation mode" value as the second parameter.
v2: Remove confusion on whether "slow" means "slow test" or "slow
platform" by using "hw" and "sim" instead. (Ashutosh)
Signed-off-by: Petri Latvala <petri.latvala@intel.com>
Cc: Arkadiusz Hiler <arek@hiler.eu>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
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Add basic parallel execbuf submission test which more or less just
submits the same BB in loop a which does an atomic increment to a memory
location. The memory location is checked at the end for the correct
value. Different sections use various IOCTL options (e.g. fences,
location of BBs, etc...).
In addition to above sections, an additional section ensure the ordering
of parallel submission by submitting a spinning batch to 1 individual
engine, submit a parallel execbuf to all engines instances within the
class, verify none on parallel execbuf make to hardware, release
spinner, and finally verify everything has completed.
The parallel-ordering section assumes default timeslice / preemption
timeout values. If these values are changed the test may fail.
v2:
(Daniele)
- Add assert to ensure parallel & load_balance both not set in ctx lib
- s/count/expected/g in check_bo()
- use existing query library functions
- clean up bb_per_execbuf / count usage
- drop dead loop
- add comment for parallel-ordering
- don't declare loop variables inside loop
v3:
(Daniele)
- Read timeslice from sysfs
v4:
(Daniele)
- Add comment in timeslice sysfs function
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
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Also delete PXP defines / structures from i915_drm_local.h.
Taken from 806acd381960 ("Merge tag 'amd-drm-fixes-5.16-2021-11-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-next")
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
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mapping
The i915 currently has 2k visible priority levels which are currently
unique. This is changing to statically map these 2k levels into 3
buckets:
low: < 0
mid: 0
high: > 0
Update gem_exec_schedule to understand this. This entails updating
promotion test to use 3 levels that will map into different buckets and
also add bit of delay after releasing a cork beforing completing the
spinners to give time to the i915 schedule to process the fence and
release and queue the requests.
Also skip any tests that rely on having more than 3 priority levels.
v2: Add a delay between starting releasing spinner and cork in
promotion, add local define for static mapping engine info
v3:
(Daniele)
- Update commit message explaining why delay is needed,
unconditionally add delay
v4:
(Tvrtko)
- Reduce sleep period
(Daniele)
- Add comment in code by sleep
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
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The function names gem_has_guc_submission and gem_has_execlists and
gem_has_semaphores are ambiguous. After "lib/i915: Return actual submission
method from gem_submission_method" these functions return which submission
method the kernel is actually using, not merely one which is
present (e.g. execlist submission is present on all kernels on which GuC
submission is present).
Therefore change the function names to clarify that they return the actual
submission method being used, not merely one which is present.
Suggested-by: John Harrison <john.c.harrison@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
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gem_submission_method() purports to return the currently used submission
method by the kernel, as evidenced by its callers. Therefore remove the
GEM_SUBMISSION_EXECLISTS flag when GuC submission is detected.
This also fixes gem_has_execlists() to match its description, previously
gem_has_execlists() would return true even if GuC submission was actually
being used in the driver.
v2: Or gem_has_execlists call-sites with gem_has_guc_submission to make the
new code equivalent to the previous code.
v3: Clarify that submission method is either guc (0x4), execlists (0x2) or
legacy without semaphores (0x0) or legacy with semaphores (0x1)
v4: Submission methods are now clearly defined as one of guc (3),
execlists (2) or legacy ring buffer (1)
Reported-by: John Harrison <john.c.harrison@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
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As part of cleaning up the submission library functions, remove the
"semaphores" submission method. Semaphores are not a "submission method",
semaphores can be used with GuC, execlists or legacy ring buffer submission.
Suggested-by: John Harrison <john.c.harrison@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: John Harrison <john.c.harrison@intel.com>
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With GuC submission, engine resets are handled entirely within GuC
rather than within i915. Traditionally, IGT has disallowed engine
based resets becuase they don't send the uevent which IGT uses to
check for unexpected resets. However, it is important to be able to
test all reset mechanisms that can be used, so allow engine based
resets to be enabled.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
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The syfs helper functions were all using basic 'int' data types for
sizs, offsets, etc. when reading from sysfs. This works fine for
little files, but not for large error capture logs (which can be
gigabytes in sizes).
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
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fetch enabled
Intel's PSR2 selective fetch adds other planes to state when
necessary, causing the async flip to fail because async flip is not
supported in cursor plane.
v2:
- adding a description to the skip message
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Karthik B S <karthik.b.s@intel.com>
Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
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So far the page alignment of the size of CCS AUX surfaces was ensured
by aligning the height of the surface to 64, which multiplied by the 64
byte CCS tile width resulted in the multiple of a 4k value. This can
overallocate the CCS surface up to ~1/4th of one main surface tile-row
size. Avoid the overallocation by simply aligning the size to 4k.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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