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MI_MEM_VIRTUAL actually means use global gtt now, not setting the bit
means use ppgtt. On previous gens, not setting the bits ment 'use
physical memory'. So what, the usual confusion.
Note that for some odd reasong this is broken on gen6, but only on the
bsd ring. Unexpected.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Not much use running them in the test rig otherwise.
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Doesn't work.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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MI_*/PIPE_CONTROL writes need to be in DOMAIN_INSTRUCTION, because
that is what mesa uses and I plan to use this to work around a
gen6 ppgtt issue.
Also testing with intentionally b0rked GFX_MODE on my snb shows that
we need to increase the loop counter a bit to reliably hit the tlb
invalidation problem. Test still completes within a few seconds.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Add a couple of simple store dword tests to test memory coherence.
gem_storedw_loop simply executes a batch that continually stores an
incremented value to a target buffer object, checking the results after
each batch completes.
gem_storedw_batches_loop does the same thing, but creates a new command
batch buffer for each iteration, which can exercise the buffer creation
code. This test is based on one from Andrzej Kacprowski from Intel.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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