From 191c85976d7f924de781ac4d9ad8a73b034493bf Mon Sep 17 00:00:00 2001 From: Damien Lespiau Date: Mon, 14 Jan 2013 23:21:21 +0000 Subject: build: Integrate the merged gen assembler in the build system Signed-off-by: Damien Lespiau --- .gitignore | 6 + Makefile.am | 2 +- assembler/AUTHORS | 1 - assembler/COPYING | 22 - assembler/INSTALL | 236 ---- assembler/Makefile.am | 34 +- assembler/autogen.sh | 12 - assembler/brw_defines.h | 878 ++++++++++++ assembler/brw_structs.h | 1579 +++++++++++++++++++++ assembler/configure.ac | 41 - assembler/disasm-main.c | 158 +++ assembler/disasm.c | 906 +++++++++++++ assembler/gen4asm.h | 202 +++ assembler/gram.y | 3167 +++++++++++++++++++++++++++++++++++++++++++ assembler/lex.l | 428 ++++++ assembler/main.c | 493 +++++++ assembler/src/Makefile.am | 23 - assembler/src/brw_defines.h | 878 ------------ assembler/src/brw_structs.h | 1579 --------------------- assembler/src/disasm-main.c | 158 --- assembler/src/disasm.c | 906 ------------- assembler/src/gen4asm.h | 202 --- assembler/src/gram.y | 3167 ------------------------------------------- assembler/src/lex.l | 428 ------ assembler/src/main.c | 493 ------- configure.ac | 19 + 26 files changed, 7863 insertions(+), 8155 deletions(-) delete mode 100644 assembler/AUTHORS delete mode 100644 assembler/COPYING delete mode 100644 assembler/INSTALL delete mode 100755 assembler/autogen.sh create mode 100644 assembler/brw_defines.h create mode 100644 assembler/brw_structs.h delete mode 100644 assembler/configure.ac create mode 100644 assembler/disasm-main.c create mode 100644 assembler/disasm.c create mode 100644 assembler/gen4asm.h create mode 100644 assembler/gram.y create mode 100644 assembler/lex.l create mode 100644 assembler/main.c delete mode 100644 assembler/src/Makefile.am delete mode 100644 assembler/src/brw_defines.h delete mode 100644 assembler/src/brw_structs.h delete mode 100644 assembler/src/disasm-main.c delete mode 100644 assembler/src/disasm.c delete mode 100644 assembler/src/gen4asm.h delete mode 100644 assembler/src/gram.y delete mode 100644 assembler/src/lex.l delete mode 100644 assembler/src/main.c diff --git a/.gitignore b/.gitignore index 063aeec0..611ab061 100644 --- a/.gitignore +++ b/.gitignore @@ -79,3 +79,9 @@ core *.swo *.swp cscope.* + +/assembler/gram.c +/assembler/gram.h +/assembler/intel-gen4asm +/assembler/intel-gen4disasm +/assembler/lex.c diff --git a/Makefile.am b/Makefile.am index 20bca79d..a8062329 100644 --- a/Makefile.am +++ b/Makefile.am @@ -21,7 +21,7 @@ ACLOCAL_AMFLAGS = ${ACLOCAL_FLAGS} -I m4 -SUBDIRS = lib man tools scripts benchmarks demos +SUBDIRS = lib man tools scripts benchmarks demos assembler if BUILD_SHADER_DEBUGGER SUBDIRS += debugger diff --git a/assembler/AUTHORS b/assembler/AUTHORS deleted file mode 100644 index 1ae4aff2..00000000 --- a/assembler/AUTHORS +++ /dev/null @@ -1 +0,0 @@ -Written in 2006 by Eric Anholt. diff --git a/assembler/COPYING b/assembler/COPYING deleted file mode 100644 index 8dfc33d6..00000000 --- a/assembler/COPYING +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright © 2006 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ diff --git a/assembler/INSTALL b/assembler/INSTALL deleted file mode 100644 index 23e5f25d..00000000 --- a/assembler/INSTALL +++ /dev/null @@ -1,236 +0,0 @@ -Installation Instructions -************************* - -Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005 Free -Software Foundation, Inc. - -This file is free documentation; the Free Software Foundation gives -unlimited permission to copy, distribute and modify it. - -Basic Installation -================== - -These are generic installation instructions. - - The `configure' shell script attempts to guess correct values for -various system-dependent variables used during compilation. It uses -those values to create a `Makefile' in each directory of the package. -It may also create one or more `.h' files containing system-dependent -definitions. Finally, it creates a shell script `config.status' that -you can run in the future to recreate the current configuration, and a -file `config.log' containing compiler output (useful mainly for -debugging `configure'). - - It can also use an optional file (typically called `config.cache' -and enabled with `--cache-file=config.cache' or simply `-C') that saves -the results of its tests to speed up reconfiguring. (Caching is -disabled by default to prevent problems with accidental use of stale -cache files.) - - If you need to do unusual things to compile the package, please try -to figure out how `configure' could check whether to do them, and mail -diffs or instructions to the address given in the `README' so they can -be considered for the next release. If you are using the cache, and at -some point `config.cache' contains results you don't want to keep, you -may remove or edit it. - - The file `configure.ac' (or `configure.in') is used to create -`configure' by a program called `autoconf'. You only need -`configure.ac' if you want to change it or regenerate `configure' using -a newer version of `autoconf'. - -The simplest way to compile this package is: - - 1. `cd' to the directory containing the package's source code and type - `./configure' to configure the package for your system. If you're - using `csh' on an old version of System V, you might need to type - `sh ./configure' instead to prevent `csh' from trying to execute - `configure' itself. - - Running `configure' takes awhile. While running, it prints some - messages telling which features it is checking for. - - 2. Type `make' to compile the package. - - 3. Optionally, type `make check' to run any self-tests that come with - the package. - - 4. Type `make install' to install the programs and any data files and - documentation. - - 5. You can remove the program binaries and object files from the - source code directory by typing `make clean'. To also remove the - files that `configure' created (so you can compile the package for - a different kind of computer), type `make distclean'. There is - also a `make maintainer-clean' target, but that is intended mainly - for the package's developers. If you use it, you may have to get - all sorts of other programs in order to regenerate files that came - with the distribution. - -Compilers and Options -===================== - -Some systems require unusual options for compilation or linking that the -`configure' script does not know about. Run `./configure --help' for -details on some of the pertinent environment variables. - - You can give `configure' initial values for configuration parameters -by setting variables in the command line or in the environment. Here -is an example: - - ./configure CC=c89 CFLAGS=-O2 LIBS=-lposix - - *Note Defining Variables::, for more details. - -Compiling For Multiple Architectures -==================================== - -You can compile the package for more than one kind of computer at the -same time, by placing the object files for each architecture in their -own directory. To do this, you must use a version of `make' that -supports the `VPATH' variable, such as GNU `make'. `cd' to the -directory where you want the object files and executables to go and run -the `configure' script. `configure' automatically checks for the -source code in the directory that `configure' is in and in `..'. - - If you have to use a `make' that does not support the `VPATH' -variable, you have to compile the package for one architecture at a -time in the source code directory. After you have installed the -package for one architecture, use `make distclean' before reconfiguring -for another architecture. - -Installation Names -================== - -By default, `make install' installs the package's commands under -`/usr/local/bin', include files under `/usr/local/include', etc. You -can specify an installation prefix other than `/usr/local' by giving -`configure' the option `--prefix=PREFIX'. - - You can specify separate installation prefixes for -architecture-specific files and architecture-independent files. If you -pass the option `--exec-prefix=PREFIX' to `configure', the package uses -PREFIX as the prefix for installing programs and libraries. -Documentation and other data files still use the regular prefix. - - In addition, if you use an unusual directory layout you can give -options like `--bindir=DIR' to specify different values for particular -kinds of files. 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Or, you can set the -`CONFIG_SITE' environment variable to the location of the site script. -A warning: not all `configure' scripts look for a site script. - -Defining Variables -================== - -Variables not defined in a site shell script can be set in the -environment passed to `configure'. However, some packages may run -configure again during the build, and the customized values of these -variables may be lost. In order to avoid this problem, you should set -them in the `configure' command line, using `VAR=value'. For example: - - ./configure CC=/usr/local2/bin/gcc - -causes the specified `gcc' to be used as the C compiler (unless it is -overridden in the site shell script). Here is a another example: - - /bin/bash ./configure CONFIG_SHELL=/bin/bash - -Here the `CONFIG_SHELL=/bin/bash' operand causes subsequent -configuration-related scripts to be executed by `/bin/bash'. - -`configure' Invocation -====================== - -`configure' recognizes the following options to control how it operates. - -`--help' -`-h' - Print a summary of the options to `configure', and exit. - -`--version' -`-V' - Print the version of Autoconf used to generate the `configure' - script, and exit. - -`--cache-file=FILE' - Enable the cache: use and save the results of the tests in FILE, - traditionally `config.cache'. FILE defaults to `/dev/null' to - disable caching. - -`--config-cache' -`-C' - Alias for `--cache-file=config.cache'. - -`--quiet' -`--silent' -`-q' - Do not print messages saying which checks are being made. To - suppress all normal output, redirect it to `/dev/null' (any error - messages will still be shown). - -`--srcdir=DIR' - Look for the package's source code in directory DIR. Usually - `configure' can determine that directory automatically. - -`configure' also accepts some other, not widely useful, options. Run -`configure --help' for more details. - diff --git a/assembler/Makefile.am b/assembler/Makefile.am index 9e6147dd..59143560 100644 --- a/assembler/Makefile.am +++ b/assembler/Makefile.am @@ -1,13 +1,31 @@ -SUBDIRS = doc src test +SUBDIRS = doc test +bin_PROGRAMS = intel-gen4asm intel-gen4disasm + +AM_YFLAGS = -d --warnings=all +AM_CFLAGS= $(ASSEMBLER_WARN_CFLAGS) + +LEX = flex -i +BUILT_SOURCES = gram.h gram.c lex.c +gram.h: gram.c + +intel_gen4asm_SOURCES = \ + brw_defines.h \ + brw_structs.h \ + gen4asm.h \ + gram.y \ + lex.l \ + main.c \ + $(NULL) + +intel_gen4disasm_SOURCES = \ + disasm.c disasm-main.c + +pkgconfigdir = $(libdir)/pkgconfig +pkgconfig_DATA = intel-gen4asm.pc + +MAINTAINERCLEANFILES = $(BUILT_SOURCES) EXTRA_DIST = \ - AUTHORS \ - COPYING \ - INSTALL \ README \ TODO \ - autogen.sh \ intel-gen4asm.pc.in - -pkgconfigdir = $(libdir)/pkgconfig -pkgconfig_DATA = intel-gen4asm.pc diff --git a/assembler/autogen.sh b/assembler/autogen.sh deleted file mode 100755 index 904cd674..00000000 --- a/assembler/autogen.sh +++ /dev/null @@ -1,12 +0,0 @@ -#! /bin/sh - -srcdir=`dirname $0` -test -z "$srcdir" && srcdir=. - -ORIGDIR=`pwd` -cd $srcdir - -autoreconf -v --install || exit 1 -cd $ORIGDIR || exit $? - -$srcdir/configure --enable-maintainer-mode "$@" diff --git a/assembler/brw_defines.h b/assembler/brw_defines.h new file mode 100644 index 00000000..2ec8050c --- /dev/null +++ b/assembler/brw_defines.h @@ -0,0 +1,878 @@ + /************************************************************************** + * + * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#ifndef BRW_DEFINES_H +#define BRW_DEFINES_H + +/* + */ +#define MI_NOOP 0x00 +#define MI_USER_INTERRUPT 0x02 +#define MI_WAIT_FOR_EVENT 0x03 +#define MI_FLUSH 0x04 +#define MI_REPORT_HEAD 0x07 +#define MI_ARB_ON_OFF 0x08 +#define MI_BATCH_BUFFER_END 0x0A +#define MI_OVERLAY_FLIP 0x11 +#define MI_LOAD_SCAN_LINES_INCL 0x12 +#define MI_LOAD_SCAN_LINES_EXCL 0x13 +#define MI_DISPLAY_BUFFER_INFO 0x14 +#define MI_SET_CONTEXT 0x18 +#define MI_STORE_DATA_IMM 0x20 +#define MI_STORE_DATA_INDEX 0x21 +#define MI_LOAD_REGISTER_IMM 0x22 +#define MI_STORE_REGISTER_MEM 0x24 +#define MI_BATCH_BUFFER_START 0x31 + +#define MI_SYNCHRONOUS_FLIP 0x0 +#define MI_ASYNCHRONOUS_FLIP 0x1 + +#define MI_BUFFER_SECURE 0x0 +#define MI_BUFFER_NONSECURE 0x1 + +#define MI_ARBITRATE_AT_CHAIN_POINTS 0x0 +#define MI_ARBITRATE_BETWEEN_INSTS 0x1 +#define MI_NO_ARBITRATION 0x3 + +#define MI_CONDITION_CODE_WAIT_DISABLED 0x0 +#define MI_CONDITION_CODE_WAIT_0 0x1 +#define MI_CONDITION_CODE_WAIT_1 0x2 +#define MI_CONDITION_CODE_WAIT_2 0x3 +#define MI_CONDITION_CODE_WAIT_3 0x4 +#define MI_CONDITION_CODE_WAIT_4 0x5 + +#define MI_DISPLAY_PIPE_A 0x0 +#define MI_DISPLAY_PIPE_B 0x1 + +#define MI_DISPLAY_PLANE_A 0x0 +#define MI_DISPLAY_PLANE_B 0x1 +#define MI_DISPLAY_PLANE_C 0x2 + +#define MI_STANDARD_FLIP 0x0 +#define MI_ENQUEUE_FLIP_PERFORM_BASE_FRAME_NUMBER_LOAD 0x1 +#define MI_ENQUEUE_FLIP_TARGET_FRAME_NUMBER_RELATIVE 0x2 +#define MI_ENQUEUE_FLIP_ABSOLUTE_TARGET_FRAME_NUMBER 0x3 + +#define MI_PHYSICAL_ADDRESS 0x0 +#define MI_VIRTUAL_ADDRESS 0x1 + +#define MI_BUFFER_MEMORY_MAIN 0x0 +#define MI_BUFFER_MEMORY_GTT 0x2 +#define MI_BUFFER_MEMORY_PER_PROCESS_GTT 0x3 + +#define MI_FLIP_CONTINUE 0x0 +#define MI_FLIP_ON 0x1 +#define MI_FLIP_OFF 0x2 + +#define MI_UNTRUSTED_REGISTER_SPACE 0x0 +#define MI_TRUSTED_REGISTER_SPACE 0x1 + +/* 3D state: + */ +#define _3DOP_3DSTATE_PIPELINED 0x0 +#define _3DOP_3DSTATE_NONPIPELINED 0x1 +#define _3DOP_3DCONTROL 0x2 +#define _3DOP_3DPRIMITIVE 0x3 + +#define _3DSTATE_PIPELINED_POINTERS 0x00 +#define _3DSTATE_BINDING_TABLE_POINTERS 0x01 +#define _3DSTATE_VERTEX_BUFFERS 0x08 +#define _3DSTATE_VERTEX_ELEMENTS 0x09 +#define _3DSTATE_INDEX_BUFFER 0x0A +#define _3DSTATE_VF_STATISTICS 0x0B +#define _3DSTATE_DRAWING_RECTANGLE 0x00 +#define _3DSTATE_CONSTANT_COLOR 0x01 +#define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02 +#define _3DSTATE_CHROMA_KEY 0x04 +#define _3DSTATE_DEPTH_BUFFER 0x05 +#define _3DSTATE_POLY_STIPPLE_OFFSET 0x06 +#define _3DSTATE_POLY_STIPPLE_PATTERN 0x07 +#define _3DSTATE_LINE_STIPPLE 0x08 +#define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09 +#define _3DCONTROL 0x00 +#define _3DPRIMITIVE 0x00 + +#define PIPE_CONTROL_NOWRITE 0x00 +#define PIPE_CONTROL_WRITEIMMEDIATE 0x01 +#define PIPE_CONTROL_WRITEDEPTH 0x02 +#define PIPE_CONTROL_WRITETIMESTAMP 0x03 + +#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00 +#define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01 + +#define _3DPRIM_POINTLIST 0x01 +#define _3DPRIM_LINELIST 0x02 +#define _3DPRIM_LINESTRIP 0x03 +#define _3DPRIM_TRILIST 0x04 +#define _3DPRIM_TRISTRIP 0x05 +#define _3DPRIM_TRIFAN 0x06 +#define _3DPRIM_QUADLIST 0x07 +#define _3DPRIM_QUADSTRIP 0x08 +#define _3DPRIM_LINELIST_ADJ 0x09 +#define _3DPRIM_LINESTRIP_ADJ 0x0A +#define _3DPRIM_TRILIST_ADJ 0x0B +#define _3DPRIM_TRISTRIP_ADJ 0x0C +#define _3DPRIM_TRISTRIP_REVERSE 0x0D +#define _3DPRIM_POLYGON 0x0E +#define _3DPRIM_RECTLIST 0x0F +#define _3DPRIM_LINELOOP 0x10 +#define _3DPRIM_POINTLIST_BF 0x11 +#define _3DPRIM_LINESTRIP_CONT 0x12 +#define _3DPRIM_LINESTRIP_BF 0x13 +#define _3DPRIM_LINESTRIP_CONT_BF 0x14 +#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 + +#define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0 +#define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1 + +#define BRW_ANISORATIO_2 0 +#define BRW_ANISORATIO_4 1 +#define BRW_ANISORATIO_6 2 +#define BRW_ANISORATIO_8 3 +#define BRW_ANISORATIO_10 4 +#define BRW_ANISORATIO_12 5 +#define BRW_ANISORATIO_14 6 +#define BRW_ANISORATIO_16 7 + +#define BRW_BLENDFACTOR_ONE 0x1 +#define BRW_BLENDFACTOR_SRC_COLOR 0x2 +#define BRW_BLENDFACTOR_SRC_ALPHA 0x3 +#define BRW_BLENDFACTOR_DST_ALPHA 0x4 +#define BRW_BLENDFACTOR_DST_COLOR 0x5 +#define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 +#define BRW_BLENDFACTOR_CONST_COLOR 0x7 +#define BRW_BLENDFACTOR_CONST_ALPHA 0x8 +#define BRW_BLENDFACTOR_SRC1_COLOR 0x9 +#define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A +#define BRW_BLENDFACTOR_ZERO 0x11 +#define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12 +#define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13 +#define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14 +#define BRW_BLENDFACTOR_INV_DST_COLOR 0x15 +#define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17 +#define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18 +#define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19 +#define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A + +#define BRW_BLENDFUNCTION_ADD 0 +#define BRW_BLENDFUNCTION_SUBTRACT 1 +#define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2 +#define BRW_BLENDFUNCTION_MIN 3 +#define BRW_BLENDFUNCTION_MAX 4 + +#define BRW_ALPHATEST_FORMAT_UNORM8 0 +#define BRW_ALPHATEST_FORMAT_FLOAT32 1 + +#define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0 +#define BRW_CHROMAKEY_REPLACE_BLACK 1 + +#define BRW_CLIP_API_OGL 0 +#define BRW_CLIP_API_DX 1 + +#define BRW_CLIPMODE_NORMAL 0 +#define BRW_CLIPMODE_CLIP_ALL 1 +#define BRW_CLIPMODE_CLIP_NON_REJECTED 2 +#define BRW_CLIPMODE_REJECT_ALL 3 +#define BRW_CLIPMODE_ACCEPT_ALL 4 + +#define BRW_CLIP_NDCSPACE 0 +#define BRW_CLIP_SCREENSPACE 1 + +#define BRW_COMPAREFUNCTION_ALWAYS 0 +#define BRW_COMPAREFUNCTION_NEVER 1 +#define BRW_COMPAREFUNCTION_LESS 2 +#define BRW_COMPAREFUNCTION_EQUAL 3 +#define BRW_COMPAREFUNCTION_LEQUAL 4 +#define BRW_COMPAREFUNCTION_GREATER 5 +#define BRW_COMPAREFUNCTION_NOTEQUAL 6 +#define BRW_COMPAREFUNCTION_GEQUAL 7 + +#define BRW_COVERAGE_PIXELS_HALF 0 +#define BRW_COVERAGE_PIXELS_1 1 +#define BRW_COVERAGE_PIXELS_2 2 +#define BRW_COVERAGE_PIXELS_4 3 + +#define BRW_CULLMODE_BOTH 0 +#define BRW_CULLMODE_NONE 1 +#define BRW_CULLMODE_FRONT 2 +#define BRW_CULLMODE_BACK 3 + +#define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0 +#define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 + +#define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 +#define BRW_DEPTHFORMAT_D32_FLOAT 1 +#define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2 +#define BRW_DEPTHFORMAT_D16_UNORM 5 + +#define BRW_FLOATING_POINT_IEEE_754 0 +#define BRW_FLOATING_POINT_NON_IEEE_754 1 + +#define BRW_FRONTWINDING_CW 0 +#define BRW_FRONTWINDING_CCW 1 + +#define BRW_INDEX_BYTE 0 +#define BRW_INDEX_WORD 1 +#define BRW_INDEX_DWORD 2 + +#define BRW_LOGICOPFUNCTION_CLEAR 0 +#define BRW_LOGICOPFUNCTION_NOR 1 +#define BRW_LOGICOPFUNCTION_AND_INVERTED 2 +#define BRW_LOGICOPFUNCTION_COPY_INVERTED 3 +#define BRW_LOGICOPFUNCTION_AND_REVERSE 4 +#define BRW_LOGICOPFUNCTION_INVERT 5 +#define BRW_LOGICOPFUNCTION_XOR 6 +#define BRW_LOGICOPFUNCTION_NAND 7 +#define BRW_LOGICOPFUNCTION_AND 8 +#define BRW_LOGICOPFUNCTION_EQUIV 9 +#define BRW_LOGICOPFUNCTION_NOOP 10 +#define BRW_LOGICOPFUNCTION_OR_INVERTED 11 +#define BRW_LOGICOPFUNCTION_COPY 12 +#define BRW_LOGICOPFUNCTION_OR_REVERSE 13 +#define BRW_LOGICOPFUNCTION_OR 14 +#define BRW_LOGICOPFUNCTION_SET 15 + +#define BRW_MAPFILTER_NEAREST 0x0 +#define BRW_MAPFILTER_LINEAR 0x1 +#define BRW_MAPFILTER_ANISOTROPIC 0x2 + +#define BRW_MIPFILTER_NONE 0 +#define BRW_MIPFILTER_NEAREST 1 +#define BRW_MIPFILTER_LINEAR 3 + +#define BRW_POLYGON_FRONT_FACING 0 +#define BRW_POLYGON_BACK_FACING 1 + +#define BRW_PREFILTER_ALWAYS 0x0 +#define BRW_PREFILTER_NEVER 0x1 +#define BRW_PREFILTER_LESS 0x2 +#define BRW_PREFILTER_EQUAL 0x3 +#define BRW_PREFILTER_LEQUAL 0x4 +#define BRW_PREFILTER_GREATER 0x5 +#define BRW_PREFILTER_NOTEQUAL 0x6 +#define BRW_PREFILTER_GEQUAL 0x7 + +#define BRW_PROVOKING_VERTEX_0 0 +#define BRW_PROVOKING_VERTEX_1 1 +#define BRW_PROVOKING_VERTEX_2 2 + +#define BRW_RASTRULE_UPPER_LEFT 0 +#define BRW_RASTRULE_UPPER_RIGHT 1 + +#define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0 +#define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1 +#define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2 + +#define BRW_STENCILOP_KEEP 0 +#define BRW_STENCILOP_ZERO 1 +#define BRW_STENCILOP_REPLACE 2 +#define BRW_STENCILOP_INCRSAT 3 +#define BRW_STENCILOP_DECRSAT 4 +#define BRW_STENCILOP_INCR 5 +#define BRW_STENCILOP_DECR 6 +#define BRW_STENCILOP_INVERT 7 + +#define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0 +#define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1 + +#define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 +#define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001 +#define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002 +#define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 +#define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 +#define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005 +#define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 +#define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 +#define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 +#define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040 +#define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041 +#define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042 +#define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043 +#define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044 +#define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045 +#define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046 +#define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 +#define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 +#define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082 +#define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083 +#define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 +#define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 +#define BRW_SURFACEFORMAT_R32G32_SINT 0x086 +#define BRW_SURFACEFORMAT_R32G32_UINT 0x087 +#define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 +#define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 +#define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A +#define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B +#define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C +#define BRW_SURFACEFORMAT_R64_FLOAT 0x08D +#define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E +#define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F +#define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090 +#define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091 +#define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092 +#define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 +#define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 +#define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095 +#define BRW_SURFACEFORMAT_R32G32_USCALED 0x096 +#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 +#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 +#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 +#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 +#define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 +#define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 +#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 +#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 +#define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 +#define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA +#define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB +#define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC +#define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD +#define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE +#define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF +#define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0 +#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 +#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 +#define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 +#define BRW_SURFACEFORMAT_R32_SINT 0x0D6 +#define BRW_SURFACEFORMAT_R32_UINT 0x0D7 +#define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8 +#define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 +#define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA +#define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF +#define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0 +#define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1 +#define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2 +#define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3 +#define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4 +#define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5 +#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 +#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA +#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB +#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC +#define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED +#define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE +#define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0 +#define BRW_SURFACEFORMAT_R32_UNORM 0x0F1 +#define BRW_SURFACEFORMAT_R32_SNORM 0x0F2 +#define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 +#define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 +#define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 +#define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6 +#define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7 +#define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8 +#define BRW_SURFACEFORMAT_R32_USCALED 0x0F9 +#define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100 +#define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 +#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 +#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 +#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 +#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 +#define BRW_SURFACEFORMAT_R8G8_UNORM 0x106 +#define BRW_SURFACEFORMAT_R8G8_SNORM 0x107 +#define BRW_SURFACEFORMAT_R8G8_SINT 0x108 +#define BRW_SURFACEFORMAT_R8G8_UINT 0x109 +#define BRW_SURFACEFORMAT_R16_UNORM 0x10A +#define BRW_SURFACEFORMAT_R16_SNORM 0x10B +#define BRW_SURFACEFORMAT_R16_SINT 0x10C +#define BRW_SURFACEFORMAT_R16_UINT 0x10D +#define BRW_SURFACEFORMAT_R16_FLOAT 0x10E +#define BRW_SURFACEFORMAT_I16_UNORM 0x111 +#define BRW_SURFACEFORMAT_L16_UNORM 0x112 +#define BRW_SURFACEFORMAT_A16_UNORM 0x113 +#define BRW_SURFACEFORMAT_L8A8_UNORM 0x114 +#define BRW_SURFACEFORMAT_I16_FLOAT 0x115 +#define BRW_SURFACEFORMAT_L16_FLOAT 0x116 +#define BRW_SURFACEFORMAT_A16_FLOAT 0x117 +#define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 +#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A +#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B +#define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C +#define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D +#define BRW_SURFACEFORMAT_R16_SSCALED 0x11E +#define BRW_SURFACEFORMAT_R16_USCALED 0x11F +#define BRW_SURFACEFORMAT_R8_UNORM 0x140 +#define BRW_SURFACEFORMAT_R8_SNORM 0x141 +#define BRW_SURFACEFORMAT_R8_SINT 0x142 +#define BRW_SURFACEFORMAT_R8_UINT 0x143 +#define BRW_SURFACEFORMAT_A8_UNORM 0x144 +#define BRW_SURFACEFORMAT_I8_UNORM 0x145 +#define BRW_SURFACEFORMAT_L8_UNORM 0x146 +#define BRW_SURFACEFORMAT_P4A4_UNORM 0x147 +#define BRW_SURFACEFORMAT_A4P4_UNORM 0x148 +#define BRW_SURFACEFORMAT_R8_SSCALED 0x149 +#define BRW_SURFACEFORMAT_R8_USCALED 0x14A +#define BRW_SURFACEFORMAT_R1_UINT 0x181 +#define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182 +#define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 +#define BRW_SURFACEFORMAT_BC1_UNORM 0x186 +#define BRW_SURFACEFORMAT_BC2_UNORM 0x187 +#define BRW_SURFACEFORMAT_BC3_UNORM 0x188 +#define BRW_SURFACEFORMAT_BC4_UNORM 0x189 +#define BRW_SURFACEFORMAT_BC5_UNORM 0x18A +#define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B +#define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C +#define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D +#define BRW_SURFACEFORMAT_MONO8 0x18E +#define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F +#define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190 +#define BRW_SURFACEFORMAT_DXT1_RGB 0x191 +#define BRW_SURFACEFORMAT_FXT1 0x192 +#define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193 +#define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194 +#define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195 +#define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196 +#define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 +#define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198 +#define BRW_SURFACEFORMAT_BC4_SNORM 0x199 +#define BRW_SURFACEFORMAT_BC5_SNORM 0x19A +#define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C +#define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D +#define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E +#define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F + +#define BRW_SURFACERETURNFORMAT_FLOAT32 0 +#define BRW_SURFACERETURNFORMAT_S1 1 + +#define BRW_SURFACE_1D 0 +#define BRW_SURFACE_2D 1 +#define BRW_SURFACE_3D 2 +#define BRW_SURFACE_CUBE 3 +#define BRW_SURFACE_BUFFER 4 +#define BRW_SURFACE_NULL 7 + +#define BRW_TEXCOORDMODE_WRAP 0 +#define BRW_TEXCOORDMODE_MIRROR 1 +#define BRW_TEXCOORDMODE_CLAMP 2 +#define BRW_TEXCOORDMODE_CUBE 3 +#define BRW_TEXCOORDMODE_CLAMP_BORDER 4 +#define BRW_TEXCOORDMODE_MIRROR_ONCE 5 + +#define BRW_THREAD_PRIORITY_NORMAL 0 +#define BRW_THREAD_PRIORITY_HIGH 1 + +#define BRW_TILEWALK_XMAJOR 0 +#define BRW_TILEWALK_YMAJOR 1 + +#define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0 +#define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1 + +#define BRW_VERTEXBUFFER_ACCESS_VERTEXDATA 0 +#define BRW_VERTEXBUFFER_ACCESS_INSTANCEDATA 1 + +#define BRW_VFCOMPONENT_NOSTORE 0 +#define BRW_VFCOMPONENT_STORE_SRC 1 +#define BRW_VFCOMPONENT_STORE_0 2 +#define BRW_VFCOMPONENT_STORE_1_FLT 3 +#define BRW_VFCOMPONENT_STORE_1_INT 4 +#define BRW_VFCOMPONENT_STORE_VID 5 +#define BRW_VFCOMPONENT_STORE_IID 6 +#define BRW_VFCOMPONENT_STORE_PID 7 + + + +/* Execution Unit (EU) defines + */ + +#define BRW_ALIGN_1 0 +#define BRW_ALIGN_16 1 + +#define BRW_ADDRESS_DIRECT 0 +#define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1 + +#define BRW_CHANNEL_X 0 +#define BRW_CHANNEL_Y 1 +#define BRW_CHANNEL_Z 2 +#define BRW_CHANNEL_W 3 + +#define BRW_COMPRESSION_NONE 0 +#define BRW_COMPRESSION_2NDHALF 1 +#define BRW_COMPRESSION_COMPRESSED 2 + +#define BRW_CONDITIONAL_NONE 0 +#define BRW_CONDITIONAL_Z 1 +#define BRW_CONDITIONAL_NZ 2 +#define BRW_CONDITIONAL_EQ 1 /* Z */ +#define BRW_CONDITIONAL_NEQ 2 /* NZ */ +#define BRW_CONDITIONAL_G 3 +#define BRW_CONDITIONAL_GE 4 +#define BRW_CONDITIONAL_L 5 +#define BRW_CONDITIONAL_LE 6 +#define BRW_CONDITIONAL_C 7 +#define BRW_CONDITIONAL_R 7 /* round increment */ +#define BRW_CONDITIONAL_O 8 /* overflow */ +#define BRW_CONDITIONAL_U 9 /* unordered */ + +#define BRW_DEBUG_NONE 0 +#define BRW_DEBUG_BREAKPOINT 1 + +#define BRW_DEPENDENCY_NORMAL 0 +#define BRW_DEPENDENCY_NOTCLEARED 1 +#define BRW_DEPENDENCY_NOTCHECKED 2 +#define BRW_DEPENDENCY_DISABLE 3 + +#define BRW_EXECUTE_1 0 +#define BRW_EXECUTE_2 1 +#define BRW_EXECUTE_4 2 +#define BRW_EXECUTE_8 3 +#define BRW_EXECUTE_16 4 +#define BRW_EXECUTE_32 5 + +#define BRW_HORIZONTAL_STRIDE_0 0 +#define BRW_HORIZONTAL_STRIDE_1 1 +#define BRW_HORIZONTAL_STRIDE_2 2 +#define BRW_HORIZONTAL_STRIDE_4 3 + +#define BRW_INSTRUCTION_NORMAL 0 +#define BRW_INSTRUCTION_SATURATE 1 + +#define BRW_MASK_ENABLE 0 +#define BRW_MASK_DISABLE 1 + +#define BRW_ACCWRCTRL_NONE 0 +#define BRW_ACCWRCTRL_ACCWRCTRL 1 + +#define BRW_OPCODE_MOV 1 +#define BRW_OPCODE_SEL 2 +#define BRW_OPCODE_NOT 4 +#define BRW_OPCODE_AND 5 +#define BRW_OPCODE_OR 6 +#define BRW_OPCODE_XOR 7 +#define BRW_OPCODE_SHR 8 +#define BRW_OPCODE_SHL 9 +#define BRW_OPCODE_RSR 10 +#define BRW_OPCODE_RSL 11 +#define BRW_OPCODE_ASR 12 +#define BRW_OPCODE_CMP 16 +#define BRW_OPCODE_CMPN 17 +#define BRW_OPCODE_F32TO16 19 +#define BRW_OPCODE_F16TO32 20 +#define BRW_OPCODE_BFREV 23 +#define BRW_OPCODE_BFE 24 +#define BRW_OPCODE_BFI1 25 +#define BRW_OPCODE_BFI2 26 +#define BRW_OPCODE_JMPI 32 +#define BRW_OPCODE_BRD 33 +#define BRW_OPCODE_IF 34 +#define BRW_OPCODE_BRC 35 +#define BRW_OPCODE_IFF 35 +#define BRW_OPCODE_ELSE 36 +#define BRW_OPCODE_ENDIF 37 +#define BRW_OPCODE_DO 38 +#define BRW_OPCODE_WHILE 39 +#define BRW_OPCODE_BREAK 40 +#define BRW_OPCODE_CONTINUE 41 +#define BRW_OPCODE_HALT 42 +#define BRW_OPCODE_MSAVE 44 +#define BRW_OPCODE_CALL 44 +#define BRW_OPCODE_MRESTORE 45 +#define BRW_OPCODE_RET 45 +#define BRW_OPCODE_PUSH 46 +#define BRW_OPCODE_POP 47 +#define BRW_OPCODE_WAIT 48 +#define BRW_OPCODE_SEND 49 +#define BRW_OPCODE_SENDC 50 +#define BRW_OPCODE_MATH 56 +#define BRW_OPCODE_ADD 64 +#define BRW_OPCODE_MUL 65 +#define BRW_OPCODE_AVG 66 +#define BRW_OPCODE_FRC 67 +#define BRW_OPCODE_RNDU 68 +#define BRW_OPCODE_RNDD 69 +#define BRW_OPCODE_RNDE 70 +#define BRW_OPCODE_RNDZ 71 +#define BRW_OPCODE_MAC 72 +#define BRW_OPCODE_MACH 73 +#define BRW_OPCODE_LZD 74 +#define BRW_OPCODE_FBH 75 +#define BRW_OPCODE_FBL 76 +#define BRW_OPCODE_CBIT 77 +#define BRW_OPCODE_ADDC 78 +#define BRW_OPCODE_SUBB 79 +#define BRW_OPCODE_SAD2 80 +#define BRW_OPCODE_SADA2 81 +#define BRW_OPCODE_DP4 84 +#define BRW_OPCODE_DPH 85 +#define BRW_OPCODE_DP3 86 +#define BRW_OPCODE_DP2 87 +#define BRW_OPCODE_DPA2 88 +#define BRW_OPCODE_LINE 89 +#define BRW_OPCODE_PLN 90 +#define BRW_OPCODE_MAD 91 +#define BRW_OPCODE_LRP 92 +#define BRW_OPCODE_NOP 126 + +#define BRW_PREDICATE_NONE 0 +#define BRW_PREDICATE_NORMAL 1 +#define BRW_PREDICATE_ALIGN1_ANYV 2 +#define BRW_PREDICATE_ALIGN1_ALLV 3 +#define BRW_PREDICATE_ALIGN1_ANY2H 4 +#define BRW_PREDICATE_ALIGN1_ALL2H 5 +#define BRW_PREDICATE_ALIGN1_ANY4H 6 +#define BRW_PREDICATE_ALIGN1_ALL4H 7 +#define BRW_PREDICATE_ALIGN1_ANY8H 8 +#define BRW_PREDICATE_ALIGN1_ALL8H 9 +#define BRW_PREDICATE_ALIGN1_ANY16H 10 +#define BRW_PREDICATE_ALIGN1_ALL16H 11 +#define BRW_PREDICATE_ALIGN16_REPLICATE_X 2 +#define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3 +#define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4 +#define BRW_PREDICATE_ALIGN16_REPLICATE_W 5 +#define BRW_PREDICATE_ALIGN16_ANY4H 6 +#define BRW_PREDICATE_ALIGN16_ALL4H 7 + +#define BRW_ARCHITECTURE_REGISTER_FILE 0 +#define BRW_GENERAL_REGISTER_FILE 1 +#define BRW_MESSAGE_REGISTER_FILE 2 +#define BRW_IMMEDIATE_VALUE 3 + +#define BRW_REGISTER_TYPE_UD 0 +#define BRW_REGISTER_TYPE_D 1 +#define BRW_REGISTER_TYPE_UW 2 +#define BRW_REGISTER_TYPE_W 3 +#define BRW_REGISTER_TYPE_UB 4 +#define BRW_REGISTER_TYPE_B 5 +#define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ +#define BRW_REGISTER_TYPE_HF 6 +#define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ +#define BRW_REGISTER_TYPE_F 7 + +#define BRW_ARF_NULL 0x00 +#define BRW_ARF_ADDRESS 0x10 +#define BRW_ARF_ACCUMULATOR 0x20 +#define BRW_ARF_FLAG 0x30 +#define BRW_ARF_MASK 0x40 +#define BRW_ARF_MASK_STACK 0x50 +#define BRW_ARF_MASK_STACK_DEPTH 0x60 +#define BRW_ARF_STATE 0x70 +#define BRW_ARF_CONTROL 0x80 +#define BRW_ARF_NOTIFICATION_COUNT 0x90 +#define BRW_ARF_IP 0xA0 + +#define BRW_AMASK 0 +#define BRW_IMASK 1 +#define BRW_LMASK 2 +#define BRW_CMASK 3 + + + +#define BRW_THREAD_NORMAL 0 +#define BRW_THREAD_ATOMIC 1 +#define BRW_THREAD_SWITCH 2 + +#define BRW_VERTICAL_STRIDE_0 0 +#define BRW_VERTICAL_STRIDE_1 1 +#define BRW_VERTICAL_STRIDE_2 2 +#define BRW_VERTICAL_STRIDE_4 3 +#define BRW_VERTICAL_STRIDE_8 4 +#define BRW_VERTICAL_STRIDE_16 5 +#define BRW_VERTICAL_STRIDE_32 6 +#define BRW_VERTICAL_STRIDE_64 7 +#define BRW_VERTICAL_STRIDE_128 8 +#define BRW_VERTICAL_STRIDE_256 9 +#define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF + +#define BRW_WIDTH_1 0 +#define BRW_WIDTH_2 1 +#define BRW_WIDTH_4 2 +#define BRW_WIDTH_8 3 +#define BRW_WIDTH_16 4 + +#define BRW_STATELESS_BUFFER_BOUNDARY_1K 0 +#define BRW_STATELESS_BUFFER_BOUNDARY_2K 1 +#define BRW_STATELESS_BUFFER_BOUNDARY_4K 2 +#define BRW_STATELESS_BUFFER_BOUNDARY_8K 3 +#define BRW_STATELESS_BUFFER_BOUNDARY_16K 4 +#define BRW_STATELESS_BUFFER_BOUNDARY_32K 5 +#define BRW_STATELESS_BUFFER_BOUNDARY_64K 6 +#define BRW_STATELESS_BUFFER_BOUNDARY_128K 7 +#define BRW_STATELESS_BUFFER_BOUNDARY_256K 8 +#define BRW_STATELESS_BUFFER_BOUNDARY_512K 9 +#define BRW_STATELESS_BUFFER_BOUNDARY_1M 10 +#define BRW_STATELESS_BUFFER_BOUNDARY_2M 11 + +#define BRW_POLYGON_FACING_FRONT 0 +#define BRW_POLYGON_FACING_BACK 1 + +#define BRW_MESSAGE_TARGET_NULL 0 +#define BRW_MESSAGE_TARGET_MATH 1 +#define BRW_MESSAGE_TARGET_SAMPLER 2 +#define BRW_MESSAGE_TARGET_GATEWAY 3 +#define BRW_MESSAGE_TARGET_DATAPORT_READ 4 +#define BRW_MESSAGE_TARGET_DP_SC 4 /* data port sampler cache */ +#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5 +#define BRW_MESSAGE_TARGET_DP_RC 5 /* data port render cache */ +#define BRW_MESSAGE_TARGET_URB 6 +#define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7 +#define BRW_MESSAGE_TARGET_VME 8 +#define BRW_MESSAGE_TARGET_DP_CC 9 /* data port constant cache */ +#define BRW_MESSAGE_TARGET_DP_DC 10 /* data port data cache */ +#define BRW_MESSAGE_TARGET_CRE 0x0d /* check & refinement enginee */ + +#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 +#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 +#define BRW_SAMPLER_RETURN_FORMAT_SINT32 3 + +#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 +#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 +#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 +#define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 +#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 +#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 +#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 +#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 +#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 +#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 +#define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 +#define BRW_SAMPLER_MESSAGE_SIMD8_RESINFO 2 +#define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2 +#define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3 +#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 +#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 + +#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 +#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 +#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2 +#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3 +#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4 + +#define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 +#define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 + +#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 +#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 + +#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 +#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 +#define BRW_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2 +#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 + +#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0 +#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1 +#define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 + +#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 +#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 +#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 +#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 +#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 + +#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 +#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 +#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2 +#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 +#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 +#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 +#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 + +#define BRW_MATH_FUNCTION_INV 1 +#define BRW_MATH_FUNCTION_LOG 2 +#define BRW_MATH_FUNCTION_EXP 3 +#define BRW_MATH_FUNCTION_SQRT 4 +#define BRW_MATH_FUNCTION_RSQ 5 +#define BRW_MATH_FUNCTION_SIN 6 /* was 7 */ +#define BRW_MATH_FUNCTION_COS 7 /* was 8 */ +#define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */ +#define BRW_MATH_FUNCTION_TAN 9 +#define BRW_MATH_FUNCTION_POW 10 +#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 +#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 +#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13 + +#define BRW_MATH_INTEGER_UNSIGNED 0 +#define BRW_MATH_INTEGER_SIGNED 1 + +#define BRW_MATH_PRECISION_FULL 0 +#define BRW_MATH_PRECISION_PARTIAL 1 + +#define BRW_MATH_SATURATE_NONE 0 +#define BRW_MATH_SATURATE_SATURATE 1 + +#define BRW_MATH_DATA_VECTOR 0 +#define BRW_MATH_DATA_SCALAR 1 + +#define BRW_URB_OPCODE_WRITE 0 + +#define BRW_URB_SWIZZLE_NONE 0 +#define BRW_URB_SWIZZLE_INTERLEAVE 1 +#define BRW_URB_SWIZZLE_TRANSPOSE 2 + +#define BRW_SCRATCH_SPACE_SIZE_1K 0 +#define BRW_SCRATCH_SPACE_SIZE_2K 1 +#define BRW_SCRATCH_SPACE_SIZE_4K 2 +#define BRW_SCRATCH_SPACE_SIZE_8K 3 +#define BRW_SCRATCH_SPACE_SIZE_16K 4 +#define BRW_SCRATCH_SPACE_SIZE_32K 5 +#define BRW_SCRATCH_SPACE_SIZE_64K 6 +#define BRW_SCRATCH_SPACE_SIZE_128K 7 +#define BRW_SCRATCH_SPACE_SIZE_256K 8 +#define BRW_SCRATCH_SPACE_SIZE_512K 9 +#define BRW_SCRATCH_SPACE_SIZE_1M 10 +#define BRW_SCRATCH_SPACE_SIZE_2M 11 + + + + +#define CMD_URB_FENCE 0x6000 +#define CMD_CONST_BUFFER_STATE 0x6001 +#define CMD_CONST_BUFFER 0x6002 + +#define CMD_STATE_BASE_ADDRESS 0x6101 +#define CMD_STATE_INSN_POINTER 0x6102 +#define CMD_PIPELINE_SELECT 0x6104 + +#define CMD_PIPELINED_STATE_POINTERS 0x7800 +#define CMD_BINDING_TABLE_PTRS 0x7801 +#define CMD_VERTEX_BUFFER 0x7808 +#define CMD_VERTEX_ELEMENT 0x7809 +#define CMD_INDEX_BUFFER 0x780a +#define CMD_VF_STATISTICS 0x780b + +#define CMD_DRAW_RECT 0x7900 +#define CMD_BLEND_CONSTANT_COLOR 0x7901 +#define CMD_CHROMA_KEY 0x7904 +#define CMD_DEPTH_BUFFER 0x7905 +#define CMD_POLY_STIPPLE_OFFSET 0x7906 +#define CMD_POLY_STIPPLE_PATTERN 0x7907 +#define CMD_LINE_STIPPLE_PATTERN 0x7908 +#define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7908 + +#define CMD_PIPE_CONTROL 0x7a00 + +#define CMD_3D_PRIM 0x7b00 + +#define CMD_MI_FLUSH 0x0200 + + +/* Various values from the R0 vertex header: + */ +#define R02_PRIM_END 0x1 +#define R02_PRIM_START 0x2 + +#define EX_DESC_SFID_MASK 0xF +#define EX_DESC_EOT_MASK 0x20 + +#endif diff --git a/assembler/brw_structs.h b/assembler/brw_structs.h new file mode 100644 index 00000000..3a3b1601 --- /dev/null +++ b/assembler/brw_structs.h @@ -0,0 +1,1579 @@ + /************************************************************************** + * + * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#ifndef BRW_STRUCTS_H +#define BRW_STRUCTS_H + +/* Command packets: + */ +struct header +{ + GLuint length:16; + GLuint opcode:16; +} bits; + + +union header_union +{ + struct header bits; + GLuint dword; +}; + +struct brw_3d_control +{ + struct + { + GLuint length:8; + GLuint notify_enable:1; + GLuint pad:3; + GLuint wc_flush_enable:1; + GLuint depth_stall_enable:1; + GLuint operation:2; + GLuint opcode:16; + } header; + + struct + { + GLuint pad:2; + GLuint dest_addr_type:1; + GLuint dest_addr:29; + } dest; + + GLuint dword2; + GLuint dword3; +}; + + +struct brw_3d_primitive +{ + struct + { + GLuint length:8; + GLuint pad:2; + GLuint topology:5; + GLuint indexed:1; + GLuint opcode:16; + } header; + + GLuint verts_per_instance; + GLuint start_vert_location; + GLuint instance_count; + GLuint start_instance_location; + GLuint base_vert_location; +}; + +/* These seem to be passed around as function args, so it works out + * better to keep them as #defines: + */ +#define BRW_FLUSH_READ_CACHE 0x1 +#define BRW_FLUSH_STATE_CACHE 0x2 +#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 +#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 + +struct brw_mi_flush +{ + GLuint flags:4; + GLuint pad:12; + GLuint opcode:16; +}; + +struct brw_vf_statistics +{ + GLuint statistics_enable:1; + GLuint pad:15; + GLuint opcode:16; +}; + + + +struct brw_binding_table_pointers +{ + struct header header; + GLuint vs; + GLuint gs; + GLuint clp; + GLuint sf; + GLuint wm; +}; + + +struct brw_blend_constant_color +{ + struct header header; + GLfloat blend_constant_color[4]; +}; + + +struct brw_depthbuffer +{ + union header_union header; + + union { + struct { + GLuint pitch:18; + GLuint format:3; + GLuint pad:4; + GLuint depth_offset_disable:1; + GLuint tile_walk:1; + GLuint tiled_surface:1; + GLuint pad2:1; + GLuint surface_type:3; + } bits; + GLuint dword; + } dword1; + + GLuint dword2_base_addr; + + union { + struct { + GLuint pad:1; + GLuint mipmap_layout:1; + GLuint lod:4; + GLuint width:13; + GLuint height:13; + } bits; + GLuint dword; + } dword3; + + union { + struct { + GLuint pad:12; + GLuint min_array_element:9; + GLuint depth:11; + } bits; + GLuint dword; + } dword4; +}; + +struct brw_drawrect +{ + struct header header; + GLuint xmin:16; + GLuint ymin:16; + GLuint xmax:16; + GLuint ymax:16; + GLuint xorg:16; + GLuint yorg:16; +}; + + + + +struct brw_global_depth_offset_clamp +{ + struct header header; + GLfloat depth_offset_clamp; +}; + +struct brw_indexbuffer +{ + union { + struct + { + GLuint length:8; + GLuint index_format:2; + GLuint cut_index_enable:1; + GLuint pad:5; + GLuint opcode:16; + } bits; + GLuint dword; + + } header; + + GLuint buffer_start; + GLuint buffer_end; +}; + + +struct brw_line_stipple +{ + struct header header; + + struct + { + GLuint pattern:16; + GLuint pad:16; + } bits0; + + struct + { + GLuint repeat_count:9; + GLuint pad:7; + GLuint inverse_repeat_count:16; + } bits1; +}; + + +struct brw_pipelined_state_pointers +{ + struct header header; + + struct { + GLuint pad:5; + GLuint offset:27; + } vs; + + struct + { + GLuint enable:1; + GLuint pad:4; + GLuint offset:27; + } gs; + + struct + { + GLuint enable:1; + GLuint pad:4; + GLuint offset:27; + } clp; + + struct + { + GLuint pad:5; + GLuint offset:27; + } sf; + + struct + { + GLuint pad:5; + GLuint offset:27; + } wm; + + struct + { + GLuint pad:5; + GLuint offset:27; /* KW: check me! */ + } cc; +}; + + +struct brw_polygon_stipple_offset +{ + struct header header; + + struct { + GLuint y_offset:5; + GLuint pad:3; + GLuint x_offset:5; + GLuint pad0:19; + } bits0; +}; + + + +struct brw_polygon_stipple +{ + struct header header; + GLuint stipple[32]; +}; + + + +struct brw_pipeline_select +{ + struct + { + GLuint pipeline_select:1; + GLuint pad:15; + GLuint opcode:16; + } header; +}; + + +struct brw_pipe_control +{ + struct + { + GLuint length:8; + GLuint notify_enable:1; + GLuint pad:2; + GLuint instruction_state_cache_flush_enable:1; + GLuint write_cache_flush_enable:1; + GLuint depth_stall_enable:1; + GLuint post_sync_operation:2; + + GLuint opcode:16; + } header; + + struct + { + GLuint pad:2; + GLuint dest_addr_type:1; + GLuint dest_addr:29; + } bits1; + + GLuint data0; + GLuint data1; +}; + + +struct brw_urb_fence +{ + struct + { + GLuint length:8; + GLuint vs_realloc:1; + GLuint gs_realloc:1; + GLuint clp_realloc:1; + GLuint sf_realloc:1; + GLuint vfe_realloc:1; + GLuint cs_realloc:1; + GLuint pad:2; + GLuint opcode:16; + } header; + + struct + { + GLuint vs_fence:10; + GLuint gs_fence:10; + GLuint clp_fence:10; + GLuint pad:2; + } bits0; + + struct + { + GLuint sf_fence:10; + GLuint vf_fence:10; + GLuint cs_fence:10; + GLuint pad:2; + } bits1; +}; + +struct brw_constant_buffer_state /* previously brw_command_streamer */ +{ + struct header header; + + struct + { + GLuint nr_urb_entries:3; + GLuint pad:1; + GLuint urb_entry_size:5; + GLuint pad0:23; + } bits0; +}; + +struct brw_constant_buffer +{ + struct + { + GLuint length:8; + GLuint valid:1; + GLuint pad:7; + GLuint opcode:16; + } header; + + struct + { + GLuint buffer_length:6; + GLuint buffer_address:26; + } bits0; +}; + +struct brw_state_base_address +{ + struct header header; + + struct + { + GLuint modify_enable:1; + GLuint pad:4; + GLuint general_state_address:27; + } bits0; + + struct + { + GLuint modify_enable:1; + GLuint pad:4; + GLuint surface_state_address:27; + } bits1; + + struct + { + GLuint modify_enable:1; + GLuint pad:4; + GLuint indirect_object_state_address:27; + } bits2; + + struct + { + GLuint modify_enable:1; + GLuint pad:11; + GLuint general_state_upper_bound:20; + } bits3; + + struct + { + GLuint modify_enable:1; + GLuint pad:11; + GLuint indirect_object_state_upper_bound:20; + } bits4; +}; + +struct brw_state_prefetch +{ + struct header header; + + struct + { + GLuint prefetch_count:3; + GLuint pad:3; + GLuint prefetch_pointer:26; + } bits0; +}; + +struct brw_system_instruction_pointer +{ + struct header header; + + struct + { + GLuint pad:4; + GLuint system_instruction_pointer:28; + } bits0; +}; + + + + +/* State structs for the various fixed function units: + */ + + +struct thread0 +{ + GLuint pad0:1; + GLuint grf_reg_count:3; + GLuint pad1:2; + GLuint kernel_start_pointer:26; +}; + +struct thread1 +{ + GLuint ext_halt_exception_enable:1; + GLuint sw_exception_enable:1; + GLuint mask_stack_exception_enable:1; + GLuint timeout_exception_enable:1; + GLuint illegal_op_exception_enable:1; + GLuint pad0:3; + GLuint depth_coef_urb_read_offset:6; /* WM only */ + GLuint pad1:2; + GLuint floating_point_mode:1; + GLuint thread_priority:1; + GLuint binding_table_entry_count:8; + GLuint pad3:5; + GLuint single_program_flow:1; +}; + +struct thread2 +{ + GLuint per_thread_scratch_space:4; + GLuint pad0:6; + GLuint scratch_space_base_pointer:22; +}; + + +struct thread3 +{ + GLuint dispatch_grf_start_reg:4; + GLuint urb_entry_read_offset:6; + GLuint pad0:1; + GLuint urb_entry_read_length:6; + GLuint pad1:1; + GLuint const_urb_entry_read_offset:6; + GLuint pad2:1; + GLuint const_urb_entry_read_length:6; + GLuint pad3:1; +}; + + + +struct brw_clip_unit_state +{ + struct thread0 thread0; + struct thread1 thread1; + struct thread2 thread2; + struct thread3 thread3; + + struct + { + GLuint pad0:9; + GLuint gs_output_stats:1; /* not always */ + GLuint stats_enable:1; + GLuint nr_urb_entries:7; + GLuint pad1:1; + GLuint urb_entry_allocation_size:5; + GLuint pad2:1; + GLuint max_threads:6; /* may be less */ + GLuint pad3:1; + } thread4; + + struct + { + GLuint pad0:13; + GLuint clip_mode:3; + GLuint userclip_enable_flags:8; + GLuint userclip_must_clip:1; + GLuint pad1:1; + GLuint guard_band_enable:1; + GLuint viewport_z_clip_enable:1; + GLuint viewport_xy_clip_enable:1; + GLuint vertex_position_space:1; + GLuint api_mode:1; + GLuint pad2:1; + } clip5; + + struct + { + GLuint pad0:5; + GLuint clipper_viewport_state_ptr:27; + } clip6; + + + GLfloat viewport_xmin; + GLfloat viewport_xmax; + GLfloat viewport_ymin; + GLfloat viewport_ymax; +}; + + + +struct brw_cc_unit_state +{ + struct + { + GLuint pad0:3; + GLuint bf_stencil_pass_depth_pass_op:3; + GLuint bf_stencil_pass_depth_fail_op:3; + GLuint bf_stencil_fail_op:3; + GLuint bf_stencil_func:3; + GLuint bf_stencil_enable:1; + GLuint pad1:2; + GLuint stencil_write_enable:1; + GLuint stencil_pass_depth_pass_op:3; + GLuint stencil_pass_depth_fail_op:3; + GLuint stencil_fail_op:3; + GLuint stencil_func:3; + GLuint stencil_enable:1; + } cc0; + + + struct + { + GLuint bf_stencil_ref:8; + GLuint stencil_write_mask:8; + GLuint stencil_test_mask:8; + GLuint stencil_ref:8; + } cc1; + + + struct + { + GLuint logicop_enable:1; + GLuint pad0:10; + GLuint depth_write_enable:1; + GLuint depth_test_function:3; + GLuint depth_test:1; + GLuint bf_stencil_write_mask:8; + GLuint bf_stencil_test_mask:8; + } cc2; + + + struct + { + GLuint pad0:8; + GLuint alpha_test_func:3; + GLuint alpha_test:1; + GLuint blend_enable:1; + GLuint ia_blend_enable:1; + GLuint pad1:1; + GLuint alpha_test_format:1; + GLuint pad2:16; + } cc3; + + struct + { + GLuint pad0:5; + GLuint cc_viewport_state_offset:27; + } cc4; + + struct + { + GLuint pad0:2; + GLuint ia_dest_blend_factor:5; + GLuint ia_src_blend_factor:5; + GLuint ia_blend_function:3; + GLuint statistics_enable:1; + GLuint logicop_func:4; + GLuint pad1:11; + GLuint dither_enable:1; + } cc5; + + struct + { + GLuint clamp_post_alpha_blend:1; + GLuint clamp_pre_alpha_blend:1; + GLuint clamp_range:2; + GLuint pad0:11; + GLuint y_dither_offset:2; + GLuint x_dither_offset:2; + GLuint dest_blend_factor:5; + GLuint src_blend_factor:5; + GLuint blend_function:3; + } cc6; + + struct { + union { + GLfloat f; + GLubyte ub[4]; + } alpha_ref; + } cc7; +}; + + + +struct brw_sf_unit_state +{ + struct thread0 thread0; + struct thread1 thread1; + struct thread2 thread2; + struct thread3 thread3; + + struct + { + GLuint pad0:10; + GLuint stats_enable:1; + GLuint nr_urb_entries:7; + GLuint pad1:1; + GLuint urb_entry_allocation_size:5; + GLuint pad2:1; + GLuint max_threads:6; + GLuint pad3:1; + } thread4; + + struct + { + GLuint front_winding:1; + GLuint viewport_transform:1; + GLuint pad0:3; + GLuint sf_viewport_state_offset:27; + } sf5; + + struct + { + GLuint pad0:9; + GLuint dest_org_vbias:4; + GLuint dest_org_hbias:4; + GLuint scissor:1; + GLuint disable_2x2_trifilter:1; + GLuint disable_zero_pix_trifilter:1; + GLuint point_rast_rule:2; + GLuint line_endcap_aa_region_width:2; + GLuint line_width:4; + GLuint fast_scissor_disable:1; + GLuint cull_mode:2; + GLuint aa_enable:1; + } sf6; + + struct + { + GLuint point_size:11; + GLuint use_point_size_state:1; + GLuint subpixel_precision:1; + GLuint sprite_point:1; + GLuint pad0:11; + GLuint trifan_pv:2; + GLuint linestrip_pv:2; + GLuint tristrip_pv:2; + GLuint line_last_pixel_enable:1; + } sf7; + +}; + + +struct brw_gs_unit_state +{ + struct thread0 thread0; + struct thread1 thread1; + struct thread2 thread2; + struct thread3 thread3; + + struct + { + GLuint pad0:10; + GLuint stats_enable:1; + GLuint nr_urb_entries:7; + GLuint pad1:1; + GLuint urb_entry_allocation_size:5; + GLuint pad2:1; + GLuint max_threads:1; + GLuint pad3:6; + } thread4; + + struct + { + GLuint sampler_count:3; + GLuint pad0:2; + GLuint sampler_state_pointer:27; + } gs5; + + + struct + { + GLuint max_vp_index:4; + GLuint pad0:26; + GLuint reorder_enable:1; + GLuint pad1:1; + } gs6; +}; + + +struct brw_vs_unit_state +{ + struct thread0 thread0; + struct thread1 thread1; + struct thread2 thread2; + struct thread3 thread3; + + struct + { + GLuint pad0:10; + GLuint stats_enable:1; + GLuint nr_urb_entries:7; + GLuint pad1:1; + GLuint urb_entry_allocation_size:5; + GLuint pad2:1; + GLuint max_threads:4; + GLuint pad3:3; + } thread4; + + struct + { + GLuint sampler_count:3; + GLuint pad0:2; + GLuint sampler_state_pointer:27; + } vs5; + + struct + { + GLuint vs_enable:1; + GLuint vert_cache_disable:1; + GLuint pad0:30; + } vs6; +}; + + +struct brw_wm_unit_state +{ + struct thread0 thread0; + struct thread1 thread1; + struct thread2 thread2; + struct thread3 thread3; + + struct { + GLuint stats_enable:1; + GLuint pad0:1; + GLuint sampler_count:3; + GLuint sampler_state_pointer:27; + } wm4; + + struct + { + GLuint enable_8_pix:1; + GLuint enable_16_pix:1; + GLuint enable_32_pix:1; + GLuint pad0:7; + GLuint legacy_global_depth_bias:1; + GLuint line_stipple:1; + GLuint depth_offset:1; + GLuint polygon_stipple:1; + GLuint line_aa_region_width:2; + GLuint line_endcap_aa_region_width:2; + GLuint early_depth_test:1; + GLuint thread_dispatch_enable:1; + GLuint program_uses_depth:1; + GLuint program_computes_depth:1; + GLuint program_uses_killpixel:1; + GLuint legacy_line_rast: 1; + GLuint pad1:1; + GLuint max_threads:6; + GLuint pad2:1; + } wm5; + + GLfloat global_depth_offset_constant; + GLfloat global_depth_offset_scale; +}; + +struct brw_sampler_default_color { + GLfloat color[4]; +}; + +struct brw_sampler_state +{ + + struct + { + GLuint shadow_function:3; + GLuint lod_bias:11; + GLuint min_filter:3; + GLuint mag_filter:3; + GLuint mip_filter:2; + GLuint base_level:5; + GLuint pad:1; + GLuint lod_preclamp:1; + GLuint default_color_mode:1; + GLuint pad0:1; + GLuint disable:1; + } ss0; + + struct + { + GLuint r_wrap_mode:3; + GLuint t_wrap_mode:3; + GLuint s_wrap_mode:3; + GLuint pad:3; + GLuint max_lod:10; + GLuint min_lod:10; + } ss1; + + + struct + { + GLuint pad:5; + GLuint default_color_pointer:27; + } ss2; + + struct + { + GLuint pad:19; + GLuint max_aniso:3; + GLuint chroma_key_mode:1; + GLuint chroma_key_index:2; + GLuint chroma_key_enable:1; + GLuint monochrome_filter_width:3; + GLuint monochrome_filter_height:3; + } ss3; +}; + + +struct brw_clipper_viewport +{ + GLfloat xmin; + GLfloat xmax; + GLfloat ymin; + GLfloat ymax; +}; + +struct brw_cc_viewport +{ + GLfloat min_depth; + GLfloat max_depth; +}; + +struct brw_sf_viewport +{ + struct { + GLfloat m00; + GLfloat m11; + GLfloat m22; + GLfloat m30; + GLfloat m31; + GLfloat m32; + } viewport; + + struct { + GLshort xmin; + GLshort ymin; + GLshort xmax; + GLshort ymax; + } scissor; +}; + +/* Documented in the subsystem/shared-functions/sampler chapter... + */ +struct brw_surface_state +{ + struct { + GLuint cube_pos_z:1; + GLuint cube_neg_z:1; + GLuint cube_pos_y:1; + GLuint cube_neg_y:1; + GLuint cube_pos_x:1; + GLuint cube_neg_x:1; + GLuint pad:4; + GLuint mipmap_layout_mode:1; + GLuint vert_line_stride_ofs:1; + GLuint vert_line_stride:1; + GLuint color_blend:1; + GLuint writedisable_blue:1; + GLuint writedisable_green:1; + GLuint writedisable_red:1; + GLuint writedisable_alpha:1; + GLuint surface_format:9; + GLuint data_return_format:1; + GLuint pad0:1; + GLuint surface_type:3; + } ss0; + + struct { + GLuint base_addr; + } ss1; + + struct { + GLuint pad:2; + GLuint mip_count:4; + GLuint width:13; + GLuint height:13; + } ss2; + + struct { + GLuint tile_walk:1; + GLuint tiled_surface:1; + GLuint pad:1; + GLuint pitch:18; + GLuint depth:11; + } ss3; + + struct { + GLuint pad:19; + GLuint min_array_elt:9; + GLuint min_lod:4; + } ss4; +}; + + + +struct brw_vertex_buffer_state +{ + struct { + GLuint pitch:11; + GLuint pad:15; + GLuint access_type:1; + GLuint vb_index:5; + } vb0; + + GLuint start_addr; + GLuint max_index; +#if 1 + GLuint instance_data_step_rate; /* not included for sequential/random vertices? */ +#endif +}; + +#define BRW_VBP_MAX 17 + +struct brw_vb_array_state { + struct header header; + struct brw_vertex_buffer_state vb[BRW_VBP_MAX]; +}; + + +struct brw_vertex_element_state +{ + struct + { + GLuint src_offset:11; + GLuint pad:5; + GLuint src_format:9; + GLuint pad0:1; + GLuint valid:1; + GLuint vertex_buffer_index:5; + } ve0; + + struct + { + GLuint dst_offset:8; + GLuint pad:8; + GLuint vfcomponent3:4; + GLuint vfcomponent2:4; + GLuint vfcomponent1:4; + GLuint vfcomponent0:4; + } ve1; +}; + +#define BRW_VEP_MAX 18 + +struct brw_vertex_element_packet { + struct header header; + struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */ +}; + + +struct brw_urb_immediate { + GLuint opcode:4; + GLuint offset:6; + GLuint swizzle_control:2; + GLuint pad:1; + GLuint allocate:1; + GLuint used:1; + GLuint complete:1; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; +}; + +/* Instruction format for the execution units: + */ + +struct brw_instruction +{ + struct + { + GLuint opcode:7; /* 0x0000007f */ + GLuint pad:1; /* 0x00000080 */ /* reserved for Opcode */ + GLuint access_mode:1; /* 0x00000100 */ + GLuint mask_control:1; /* 0x00000200 */ + GLuint dependency_control:2; /* 0x00000c00 */ + GLuint compression_control:2; /* 0x00003000 */ + GLuint thread_control:2; /* 0x0000c000 */ + GLuint predicate_control:4; /* 0x000f0000 */ + GLuint predicate_inverse:1; /* 0x00100000 */ + GLuint execution_size:3; /* 0x00e00000 */ + GLuint sfid_destreg__conditionalmod:4; /* sfid - send on GEN6+, destreg - send on Prev GEN6, conditionalmod - others */ + GLuint acc_wr_control:1; /* 0x10000000 */ + GLuint pad0:1; /* 0x20000000 */ + GLuint debug_control:1; /* 0x40000000 */ + GLuint saturate:1; /* 0x80000000 */ + } header; + + union { + struct + { + GLuint dest_reg_file:2; /* 0x00000003 */ + GLuint dest_reg_type:3; /* 0x0000001c */ + GLuint src0_reg_file:2; /* 0x00000060 */ + GLuint src0_reg_type:3; /* 0x00000380 */ + GLuint src1_reg_file:2; /* 0x00000c00 */ + GLuint src1_reg_type:3; /* 0x00007000 */ + GLuint pad:1; /* 0x00008000 */ + GLuint dest_subreg_nr:5; /* 0x001f0000 */ + GLuint dest_reg_nr:8; /* 0x1f700000 */ + GLuint dest_horiz_stride:2; /* 0x60000000 */ + GLuint dest_address_mode:1; /* 0x80000000 */ + } da1; /* direct align1 */ + + struct + { + GLuint dest_reg_file:2; + GLuint dest_reg_type:3; + GLuint src0_reg_file:2; + GLuint src0_reg_type:3; + GLuint src1_reg_file:2; /* 0x00000c00 */ + GLuint src1_reg_type:3; /* 0x00007000 */ + GLuint pad:1; + GLint dest_indirect_offset:10; /* offset against the deref'd address reg */ + GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */ + GLuint dest_horiz_stride:2; + GLuint dest_address_mode:1; + } ia1; /* indirect align1 */ + + struct + { + GLuint dest_reg_file:2; + GLuint dest_reg_type:3; + GLuint src0_reg_file:2; + GLuint src0_reg_type:3; + GLuint src1_reg_file:2; + GLuint src1_reg_type:3; + GLuint pad0:1; + GLuint dest_writemask:4; + GLuint dest_subreg_nr:1; + GLuint dest_reg_nr:8; + GLuint dest_horiz_stride:2; + GLuint dest_address_mode:1; + } da16; /* direct align16 */ + + struct + { + GLuint dest_reg_file:2; + GLuint dest_reg_type:3; + GLuint src0_reg_file:2; + GLuint src0_reg_type:3; + GLuint pad0:6; + GLuint dest_writemask:4; + GLint dest_indirect_offset:6; + GLuint dest_subreg_nr:3; + GLuint dest_horiz_stride:2; + GLuint dest_address_mode:1; + } ia16; /* indirect align16 */ + + struct + { + GLuint dest_reg_file:1; /* used in Gen6, deleted in Gen7 */ + GLuint flag_subreg_nr:1; + GLuint flag_reg_nr:1; /* not in Gen6. Add in Gen7 */ + GLuint pad1:1; /* reserved */ + GLuint src0_modifier:2; + GLuint src1_modifier:2; + GLuint src2_modifier:2; + GLuint src_reg_type:2; + GLuint dest_reg_type:2; + GLuint pad2:1; /* reserved */ + GLuint nib_ctrl:1; + GLuint pad3:1; /* reserved */ + GLuint dest_writemask:4; + GLuint dest_subreg_nr:3; + GLuint dest_reg_nr:8; + } three_src_gen6; /* Three-source-operator instructions for Gen6+ */ + + struct + { + GLuint pad:16; + GLint JIP:16; + } branch; /* conditional branch JIP for Gen6 only */ + } bits1; + + + union { + struct + { + GLuint src0_subreg_nr:5; /* 0x0000001f */ + GLuint src0_reg_nr:8; /* 0x00001fe0 */ + GLuint src0_abs:1; /* 0x00002000 */ + GLuint src0_negate:1; /* 0x00004000 */ + GLuint src0_address_mode:1; /* 0x00008000 */ + GLuint src0_horiz_stride:2; /* 0x00030000 */ + GLuint src0_width:3; /* 0x001c0000 */ + GLuint src0_vert_stride:4; /* 0x01e00000 */ + GLuint flag_subreg_nr:1; /* 0x02000000 */ + GLuint flag_reg_nr:1; /* 0x04000000 */ + GLuint pad:5; /* 0xf8000000 */ + } da1; /* direct align1 */ + + struct + { + GLint src0_indirect_offset:10; + GLuint src0_subreg_nr:3; + GLuint src0_abs:1; + GLuint src0_negate:1; + GLuint src0_address_mode:1; + GLuint src0_horiz_stride:2; + GLuint src0_width:3; + GLuint src0_vert_stride:4; + GLuint flag_subreg_nr:1; + GLuint flag_reg_nr:1; + GLuint pad:5; + } ia1; /* indirect align1 */ + + struct + { + GLuint src0_swz_x:2; + GLuint src0_swz_y:2; + GLuint src0_subreg_nr:1; + GLuint src0_reg_nr:8; + GLuint src0_abs:1; + GLuint src0_negate:1; + GLuint src0_address_mode:1; + GLuint src0_swz_z:2; + GLuint src0_swz_w:2; + GLuint pad0:1; + GLuint src0_vert_stride:4; + GLuint flag_subreg_nr:1; + GLuint flag_reg_nr:1; + GLuint pad1:5; + } da16; /* direct align16 */ + + struct + { + GLuint src0_swz_x:2; + GLuint src0_swz_y:2; + GLint src0_indirect_offset:6; + GLuint src0_subreg_nr:3; + GLuint src0_abs:1; + GLuint src0_negate:1; + GLuint src0_address_mode:1; + GLuint src0_swz_z:2; + GLuint src0_swz_w:2; + GLuint pad0:1; + GLuint src0_vert_stride:4; + GLuint flag_subreg_nr:1; + GLuint flag_reg_nr:1; + GLuint pad1:5; + } ia16; /* indirect align16 */ + + struct + { + GLuint src0_rep_ctrl:1; + GLuint src0_swizzle:8; + GLuint src0_subreg_nr:3; + GLuint src0_reg_nr:8; + GLuint pad0:1; /* reserved */ + GLuint src1_rep_ctrl:1; + GLuint src1_swizzle:8; + GLuint src1_subreg_nr_low:2; /* src1_subreg_nr spans on two DWORDs */ + } three_src_gen6; /* Three-source-operator instructions for Gen6+ */ + + struct + { + GLuint pad:26; + GLuint end_of_thread:1; + GLuint pad1:1; + GLuint sfid:4; + } send_gen5; /* for GEN5 only */ + struct + { + GLuint pad:26; + GLuint msg_ext:6; + } msg_ext; + } bits2; + + union + { + struct + { + GLuint src1_subreg_nr:5; + GLuint src1_reg_nr:8; + GLuint src1_abs:1; + GLuint src1_negate:1; + GLuint src1_address_mode:1; + GLuint src1_horiz_stride:2; + GLuint src1_width:3; + GLuint src1_vert_stride:4; + GLuint pad0:7; + } da1; /* direct align1 */ + + struct + { + GLuint src1_swz_x:2; + GLuint src1_swz_y:2; + GLuint src1_subreg_nr:1; + GLuint src1_reg_nr:8; + GLuint src1_abs:1; + GLuint src1_negate:1; + GLuint src1_address_mode:1; + GLuint src1_swz_z:2; + GLuint src1_swz_w:2; + GLuint pad1:1; + GLuint src1_vert_stride:4; + GLuint pad2:7; + } da16; /* direct align16 */ + + struct + { + GLint src1_indirect_offset:10; + GLuint src1_subreg_nr:3; + GLuint src1_abs:1; + GLuint src1_negate:1; + GLuint src1_address_mode:1; + GLuint src1_horiz_stride:2; + GLuint src1_width:3; + GLuint src1_vert_stride:4; + GLuint pad1:7; + } ia1; /* indirect align1 */ + + struct + { + GLuint src1_swz_x:2; + GLuint src1_swz_y:2; + GLint src1_indirect_offset:6; + GLuint src1_subreg_nr:3; + GLuint src1_abs:1; + GLuint src1_negate:1; + GLuint src1_address_mode:1; + GLuint src1_swz_z:2; + GLuint src1_swz_w:2; + GLuint pad1:1; + GLuint src1_vert_stride:4; + GLuint pad2:7; + } ia16; /* indirect align16 */ + + struct + { + GLuint src1_subreg_nr_high:1; /* src1_subreg_nr spans on two DWORDs */ + GLuint src1_reg_nr:8; + GLuint pad0:1; /* reserved */ + GLuint src2_rep_ctrl:1; + GLuint src2_swizzle:8; + GLuint src2_subreg_nr:3; + GLuint src2_reg_nr:8; + GLuint pad1:2; /* reserved */ + } three_src_gen6; /* Three-source-operator instructions for Gen6+ */ + + struct + { + GLint JIP:16; /* Gen7 bspec: both the JIP and UIP are signed 16-bit numbers */ + GLint UIP:16; + } branch_2_offset; /* for Gen6, Gen7 2-offsets branch; for Gen7 1-offset branch */ + + GLint JIP; /* used by Gen6 CALL instructions; Gen7 JMPI */ + + struct { + GLuint function:4; + GLuint int_type:1; + GLuint precision:1; + GLuint saturate:1; + GLuint data_type:1; + GLuint pad0:8; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } math; + + struct { + GLuint binding_table_index:8; + GLuint sampler:4; + GLuint return_format:2; + GLuint msg_type:2; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } sampler; + + struct brw_urb_immediate urb; + + struct { + GLuint binding_table_index:8; + GLuint msg_control:4; + GLuint msg_type:2; + GLuint target_cache:2; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } dp_read; + + struct { + GLuint binding_table_index:8; + GLuint msg_control:3; + GLuint pixel_scoreboard_clear:1; + GLuint msg_type:3; + GLuint send_commit_msg:1; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } dp_write; + + struct { + GLuint opcode:1; + GLuint requester_type:1; + GLuint pad:2; + GLuint resource_select:1; + GLuint pad1:11; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad2:3; + GLuint end_of_thread:1; + } thread_spawner; + + struct { + GLuint pad:16; + GLuint response_length:4; + GLuint msg_length:4; + GLuint msg_target:4; + GLuint pad1:3; + GLuint end_of_thread:1; + } generic; + + struct { + GLuint function:4; + GLuint int_type:1; + GLuint precision:1; + GLuint saturate:1; + GLuint data_type:1; + GLuint snapshot:1; + GLuint pad0:10; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } math_gen5; + + struct { + GLuint opcode:4; + GLuint offset:6; + GLuint swizzle_control:2; + GLuint pad:1; + GLuint allocate:1; + GLuint used:1; + GLuint complete:1; + GLuint pad0:3; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } urb_gen5; + + struct { + GLuint binding_table_index:8; + GLuint sampler:4; + GLuint msg_type:4; + GLuint simd_mode:2; + GLuint pad0:1; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } sampler_gen5; + + struct { + GLuint binding_table_index:8; + GLuint sampler:4; + GLuint msg_type:5; + GLuint simd_mode:2; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } sampler_gen7; + + struct { + GLuint binding_table_index:8; + GLuint msg_control:4; + GLuint msg_type:2; + GLuint target_cache:2; + GLuint pad0:3; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } dp_read_gen5; + + struct { + GLuint binding_table_index:8; + GLuint msg_control:5; + GLuint msg_type:3; + GLuint pad0:3; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } dp_read_gen6; + + struct { + GLuint binding_table_index:8; + GLuint msg_control:3; + GLuint pixel_scoreboard_clear:1; + GLuint msg_type:3; + GLuint send_commit_msg:1; + GLuint pad0:3; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } dp_write_gen5; + + struct { + GLuint binding_table_index:8; + GLuint msg_control:5; + GLuint msg_type:4; + GLuint send_commit_msg:1; + GLuint pad0:1; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } dp_write_gen6; + + struct { + GLuint binding_table_index:8; + GLuint msg_control:5; + GLuint msg_type:4; + GLuint send_commit_msg:1; /* ignore on read message */ + GLuint pad0:1; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } dp_gen6; + + struct { + GLuint binding_table_index:8; + GLuint msg_control:6; + GLuint msg_type:4; + GLuint category:1; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } dp_gen7; + + struct { + GLuint opcode:1; + GLuint requester_type:1; + GLuint pad0:2; + GLuint resource_select:1; + GLuint pad1:14; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad2:2; + GLuint end_of_thread:1; + } thread_spawner_gen5; + + struct { + GLuint binding_table_index:8; + GLuint search_path_index:3; + GLuint lut_subindex:2; + GLuint message_type:2; + GLuint pad0:4; + GLuint header_present:1; + } vme_gen6; + struct { + GLuint binding_table_index:8; + GLuint pad0:5; + GLuint message_type:2; + GLuint pad1:4; + GLuint header_present:1; + } cre_gen75; + struct { + GLuint pad:19; + GLuint header_present:1; + GLuint response_length:5; + GLuint msg_length:4; + GLuint pad1:2; + GLuint end_of_thread:1; + } generic_gen5; + + GLuint ud; + GLint id; + GLfloat fd; + } bits3; + + char *first_reloc_target, *second_reloc_target; // first for JIP, second for UIP + GLint first_reloc_offset, second_reloc_offset; // in number of instructions +}; + + +#endif diff --git a/assembler/configure.ac b/assembler/configure.ac deleted file mode 100644 index 0b4427c3..00000000 --- a/assembler/configure.ac +++ /dev/null @@ -1,41 +0,0 @@ -# -*- Autoconf -*- -# Process this file with autoconf to produce a configure script. - -AC_PREREQ(2.57) -AC_INIT([intel-gen4asm], - 1.3, - [eric@anholt.net], - intel-gen4asm) - -AC_CONFIG_SRCDIR([Makefile.am]) -AM_INIT_AUTOMAKE([dist-bzip2 foreign]) - -AM_MAINTAINER_MODE - -# Checks for programs. -AC_PROG_CC -AM_PROG_LEX -AC_PROG_YACC - -WARN_CFLAGS="" -if test "x$GCC" = "xyes"; then - WARN_CFLAGS="-Wall -Wpointer-arith -Wstrict-prototypes \ - -Wmissing-prototypes -Wmissing-declarations \ - -Wnested-externs -fno-strict-aliasing" - AC_DEFINE_UNQUOTED(HAVE_WARNING_CPP_DIRECTIVE,1, - [Can use #warning in C files]) -fi -AC_SUBST(WARN_CFLAGS) - -# Checks for libraries. - -# Checks for header files. -AC_HEADER_STDC - -AC_OUTPUT([ - Makefile - doc/Makefile - src/Makefile - test/Makefile - intel-gen4asm.pc -]) diff --git a/assembler/disasm-main.c b/assembler/disasm-main.c new file mode 100644 index 00000000..5cc1e7d1 --- /dev/null +++ b/assembler/disasm-main.c @@ -0,0 +1,158 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "gen4asm.h" + +static const struct option longopts[] = { + { NULL, 0, NULL, 0 } +}; + +static struct brw_program * +read_program (FILE *input) +{ + uint32_t inst[4]; + struct brw_program *program; + struct brw_program_instruction *entry, **prev; + int c; + int n = 0; + + program = malloc (sizeof (struct brw_program)); + program->first = NULL; + prev = &program->first; + while ((c = getc (input)) != EOF) { + if (c == '0') { + if (fscanf (input, "x%x", &inst[n]) == 1) { + ++n; + if (n == 4) { + entry = malloc (sizeof (struct brw_program_instruction)); + memcpy (&entry->instruction, inst, 4 * sizeof (uint32_t)); + entry->next = NULL; + *prev = entry; + prev = &entry->next; + n = 0; + } + } + } + } + return program; +} + +static struct brw_program * +read_program_binary (FILE *input) +{ + uint32_t temp; + uint8_t inst[16]; + struct brw_program *program; + struct brw_program_instruction *entry, **prev; + int c; + int n = 0; + + program = malloc (sizeof (struct brw_program)); + program->first = NULL; + prev = &program->first; + while ((c = getc (input)) != EOF) { + if (c == '0') { + if (fscanf (input, "x%2x", &temp) == 1) { + inst[n++] = (uint8_t)temp; + if (n == 16) { + entry = malloc (sizeof (struct brw_program_instruction)); + memcpy (&entry->instruction, inst, 16 * sizeof (uint8_t)); + entry->next = NULL; + *prev = entry; + prev = &entry->next; + n = 0; + } + } + } + } + return program; +} + +static void usage(void) +{ + fprintf(stderr, "usage: intel-gen4disasm [-o outputfile] [-b] inputfile\n"); +} + +int main(int argc, char **argv) +{ + struct brw_program *program; + FILE *input = stdin; + FILE *output = stdout; + char *input_filename = NULL; + char *output_file = NULL; + int byte_array_input = 0; + int o; + struct brw_program_instruction *inst; + + while ((o = getopt_long(argc, argv, "o:b", longopts, NULL)) != -1) { + switch (o) { + case 'o': + if (strcmp(optarg, "-") != 0) + output_file = optarg; + break; + case 'b': + byte_array_input = 1; + break; + default: + usage(); + exit(1); + } + } + argc -= optind; + argv += optind; + if (argc != 1) { + usage(); + exit(1); + } + + if (strcmp(argv[0], "-") != 0) { + input_filename = argv[0]; + input = fopen(input_filename, "r"); + if (input == NULL) { + perror("Couldn't open input file"); + exit(1); + } + } + if (byte_array_input) + program = read_program_binary (input); + else + program = read_program (input); + if (!program) + exit (1); + if (output_file) { + output = fopen (output_file, "w"); + if (output == NULL) { + perror("Couldn't open output file"); + exit(1); + } + } + + for (inst = program->first; inst; inst = inst->next) + disasm (output, &inst->instruction); + exit (0); +} diff --git a/assembler/disasm.c b/assembler/disasm.c new file mode 100644 index 00000000..1ec6ae59 --- /dev/null +++ b/assembler/disasm.c @@ -0,0 +1,906 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include + +#include "gen4asm.h" +#include "brw_defines.h" + +struct { + char *name; + int nsrc; + int ndst; +} opcode[128] = { + [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 }, + + [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1}, + + [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 }, + [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 }, + + [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 }, + [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 }, + [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 }, + [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 1, .ndst = 01 }, + [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 1, .ndst = 0 }, + [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 }, + [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 1, .ndst = 0 }, + [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 }, + [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 }, + [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 }, + [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 }, + [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 }, + [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 }, + [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 }, +}; + +char *conditional_modifier[16] = { + [BRW_CONDITIONAL_NONE] = "", + [BRW_CONDITIONAL_Z] = ".e", + [BRW_CONDITIONAL_NZ] = ".ne", + [BRW_CONDITIONAL_G] = ".g", + [BRW_CONDITIONAL_GE] = ".ge", + [BRW_CONDITIONAL_L] = ".l", + [BRW_CONDITIONAL_LE] = ".le", + [BRW_CONDITIONAL_R] = ".r", + [BRW_CONDITIONAL_O] = ".o", + [BRW_CONDITIONAL_U] = ".u", +}; + +char *negate[2] = { + [0] = "", + [1] = "-", +}; + +char *_abs[2] = { + [0] = "", + [1] = "(abs)", +}; + +char *vert_stride[16] = { + [0] = "0", + [1] = "1", + [2] = "2", + [3] = "4", + [4] = "8", + [5] = "16", + [6] = "32", + [15] = "VxH", +}; + +char *width[8] = { + [0] = "1", + [1] = "2", + [2] = "4", + [3] = "8", + [4] = "16", +}; + +char *horiz_stride[4] = { + [0] = "0", + [1] = "1", + [2] = "2", + [3] = "4" +}; + +char *chan_sel[4] = { + [0] = "x", + [1] = "y", + [2] = "z", + [3] = "w", +}; + +char *dest_condmod[16] = { +}; + +char *debug_ctrl[2] = { + [0] = "", + [1] = ".breakpoint" +}; + +char *saturate[2] = { + [0] = "", + [1] = ".sat" +}; + +char *exec_size[8] = { + [0] = "1", + [1] = "2", + [2] = "4", + [3] = "8", + [4] = "16", + [5] = "32" +}; + +char *pred_inv[2] = { + [0] = "+", + [1] = "-" +}; + +char *pred_ctrl_align16[16] = { + [1] = "", + [2] = ".x", + [3] = ".y", + [4] = ".z", + [5] = ".w", + [6] = ".any4h", + [7] = ".all4h", +}; + +char *pred_ctrl_align1[16] = { + [1] = "", + [2] = ".anyv", + [3] = ".allv", + [4] = ".any2h", + [5] = ".all2h", + [6] = ".any4h", + [7] = ".all4h", + [8] = ".any8h", + [9] = ".all8h", + [10] = ".any16h", + [11] = ".all16h", +}; + +char *thread_ctrl[4] = { + [0] = "", + [2] = "switch" +}; + +char *compr_ctrl[4] = { + [0] = "", + [1] = "sechalf", + [2] = "compr", +}; + +char *dep_ctrl[4] = { + [0] = "", + [1] = "NoDDClr", + [2] = "NoDDChk", + [3] = "NoDDClr,NoDDChk", +}; + +char *mask_ctrl[4] = { + [0] = "", + [1] = "nomask", +}; + +char *access_mode[2] = { + [0] = "align1", + [1] = "align16", +}; + +char *reg_encoding[8] = { + [0] = "UD", + [1] = "D", + [2] = "UW", + [3] = "W", + [4] = "UB", + [5] = "B", + [7] = "F" +}; + +char *imm_encoding[8] = { + [0] = "UD", + [1] = "D", + [2] = "UW", + [3] = "W", + [5] = "VF", + [6] = "V", + [7] = "F" +}; + +char *reg_file[4] = { + [0] = "A", + [1] = "g", + [2] = "m", + [3] = "imm", +}; + +char *writemask[16] = { + [0x0] = ".", + [0x1] = ".x", + [0x2] = ".y", + [0x3] = ".xy", + [0x4] = ".z", + [0x5] = ".xz", + [0x6] = ".yz", + [0x7] = ".xyz", + [0x8] = ".w", + [0x9] = ".xw", + [0xa] = ".yw", + [0xb] = ".xyw", + [0xc] = ".zw", + [0xd] = ".xzw", + [0xe] = ".yzw", + [0xf] = "", +}; + +char *end_of_thread[2] = { + [0] = "", + [1] = "EOT" +}; + +char *target_function[16] = { + [BRW_MESSAGE_TARGET_NULL] = "null", + [BRW_MESSAGE_TARGET_MATH] = "math", + [BRW_MESSAGE_TARGET_SAMPLER] = "sampler", + [BRW_MESSAGE_TARGET_GATEWAY] = "gateway", + [BRW_MESSAGE_TARGET_DATAPORT_READ] = "read", + [BRW_MESSAGE_TARGET_DATAPORT_WRITE] = "write", + [BRW_MESSAGE_TARGET_URB] = "urb", + [BRW_MESSAGE_TARGET_THREAD_SPAWNER] = "thread_spawner" +}; + +char *math_function[16] = { + [BRW_MATH_FUNCTION_INV] = "inv", + [BRW_MATH_FUNCTION_LOG] = "log", + [BRW_MATH_FUNCTION_EXP] = "exp", + [BRW_MATH_FUNCTION_SQRT] = "sqrt", + [BRW_MATH_FUNCTION_RSQ] = "rsq", + [BRW_MATH_FUNCTION_SIN] = "sin", + [BRW_MATH_FUNCTION_COS] = "cos", + [BRW_MATH_FUNCTION_SINCOS] = "sincos", + [BRW_MATH_FUNCTION_TAN] = "tan", + [BRW_MATH_FUNCTION_POW] = "pow", + [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod", + [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intmod", + [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intdiv", +}; + +char *math_saturate[2] = { + [0] = "", + [1] = "sat" +}; + +char *math_signed[2] = { + [0] = "", + [1] = "signed" +}; + +char *math_scalar[2] = { + [0] = "", + [1] = "scalar" +}; + +char *math_precision[2] = { + [0] = "", + [1] = "partial_precision" +}; + +char *urb_swizzle[4] = { + [BRW_URB_SWIZZLE_NONE] = "", + [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave", + [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose", +}; + +char *urb_allocate[2] = { + [0] = "", + [1] = "allocate" +}; + +char *urb_used[2] = { + [0] = "", + [1] = "used" +}; + +char *urb_complete[2] = { + [0] = "", + [1] = "complete" +}; + +char *sampler_target_format[4] = { + [0] = "F", + [2] = "UD", + [3] = "D" +}; + + +static int column; + +static int string (FILE *file, char *string) +{ + fputs (string, file); + column += strlen (string); + return 0; +} + +static int format (FILE *f, char *format, ...) +{ + char buf[1024]; + va_list args; + va_start (args, format); + + vsnprintf (buf, sizeof (buf) - 1, format, args); + string (f, buf); + return 0; +} + +static int newline (FILE *f) +{ + putc ('\n', f); + column = 0; + return 0; +} + +static int pad (FILE *f, int c) +{ + do + string (f, " "); + while (column < c); + return 0; +} + +static int control (FILE *file, char *name, char *ctrl[], GLuint id, int *space) +{ + if (!ctrl[id]) { + fprintf (file, "*** invalid %s value %d ", + name, id); + return 1; + } + if (ctrl[id][0]) + { + if (space && *space) + string (file, " "); + string (file, ctrl[id]); + if (space) + *space = 1; + } + return 0; +} + +static int print_opcode (FILE *file, int id) +{ + if (!opcode[id].name) { + format (file, "*** invalid opcode value %d ", id); + return 1; + } + string (file, opcode[id].name); + return 0; +} + +static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr) +{ + int err = 0; + if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) { + switch (_reg_nr & 0xf0) { + case BRW_ARF_NULL: + string (file, "null"); + return -1; + case BRW_ARF_ADDRESS: + format (file, "a%d", _reg_nr & 0x0f); + break; + case BRW_ARF_ACCUMULATOR: + format (file, "acc%d", _reg_nr & 0x0f); + break; + case BRW_ARF_MASK: + format (file, "mask%d", _reg_nr & 0x0f); + break; + case BRW_ARF_MASK_STACK: + format (file, "msd%d", _reg_nr & 0x0f); + break; + case BRW_ARF_STATE: + format (file, "sr%d", _reg_nr & 0x0f); + break; + case BRW_ARF_CONTROL: + format (file, "cr%d", _reg_nr & 0x0f); + break; + case BRW_ARF_NOTIFICATION_COUNT: + format (file, "n%d", _reg_nr & 0x0f); + break; + case BRW_ARF_IP: + string (file, "ip"); + return -1; + break; + default: + format (file, "ARF%d", _reg_nr); + break; + } + } else { + err |= control (file, "src reg file", reg_file, _reg_file, NULL); + format (file, "%d", _reg_nr); + } + return err; +} + +static int dest (FILE *file, struct brw_instruction *inst) +{ + int err = 0; + + if (inst->header.access_mode == BRW_ALIGN_1) + { + if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT) + { + err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr); + if (err == -1) + return 0; + if (inst->bits1.da1.dest_subreg_nr) + format (file, ".%d", inst->bits1.da1.dest_subreg_nr); + format (file, "<%d>", inst->bits1.da1.dest_horiz_stride); + err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL); + } + else + { + string (file, "g[a0"); + if (inst->bits1.ia1.dest_subreg_nr) + format (file, ".%d", inst->bits1.ia1.dest_subreg_nr); + if (inst->bits1.ia1.dest_indirect_offset) + format (file, " %d", inst->bits1.ia1.dest_indirect_offset); + string (file, "]"); + format (file, "<%d>", inst->bits1.ia1.dest_horiz_stride); + err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.ia1.dest_reg_type, NULL); + } + } + else + { + if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT) + { + err |= reg (file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr); + if (err == -1) + return 0; + if (inst->bits1.da16.dest_subreg_nr) + format (file, ".%d", inst->bits1.da16.dest_subreg_nr); + string (file, "<1>"); + err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL); + err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL); + } + else + { + err = 1; + string (file, "Indirect align16 address mode not supported"); + } + } + + return 0; +} + +static int src_align1_region (FILE *file, + GLuint _vert_stride, GLuint _width, GLuint _horiz_stride) +{ + int err = 0; + string (file, "<"); + err |= control (file, "vert stride", vert_stride, _vert_stride, NULL); + string (file, ","); + err |= control (file, "width", width, _width, NULL); + string (file, ","); + err |= control (file, "horiz_stride", horiz_stride, _horiz_stride, NULL); + string (file, ">"); + return err; +} + +static int src_da1 (FILE *file, GLuint type, GLuint _reg_file, + GLuint _vert_stride, GLuint _width, GLuint _horiz_stride, + GLuint reg_num, GLuint sub_reg_num, GLuint __abs, GLuint _negate) +{ + int err = 0; + err |= control (file, "negate", negate, _negate, NULL); + err |= control (file, "abs", _abs, __abs, NULL); + + err |= reg (file, _reg_file, reg_num); + if (err == -1) + return 0; + if (sub_reg_num) + format (file, ".%d", sub_reg_num); + src_align1_region (file, _vert_stride, _width, _horiz_stride); + err |= control (file, "src reg encoding", reg_encoding, type, NULL); + return err; +} + +static int src_ia1 (FILE *file, + GLuint type, + GLuint _reg_file, + GLint _addr_imm, + GLuint _addr_subreg_nr, + GLuint _negate, + GLuint __abs, + GLuint _addr_mode, + GLuint _horiz_stride, + GLuint _width, + GLuint _vert_stride) +{ + int err = 0; + err |= control (file, "negate", negate, _negate, NULL); + err |= control (file, "abs", _abs, __abs, NULL); + + string (file, "g[a0"); + if (_addr_subreg_nr) + format (file, ".%d", _addr_subreg_nr); + if (_addr_imm) + format (file, " %d", _addr_imm); + string (file, "]"); + src_align1_region (file, _vert_stride, _width, _horiz_stride); + err |= control (file, "src reg encoding", reg_encoding, type, NULL); + return err; +} + +static int src_da16 (FILE *file, + GLuint _reg_type, + GLuint _reg_file, + GLuint _vert_stride, + GLuint _reg_nr, + GLuint _subreg_nr, + GLuint __abs, + GLuint _negate, + GLuint swz_x, + GLuint swz_y, + GLuint swz_z, + GLuint swz_w) +{ + int err = 0; + err |= control (file, "negate", negate, _negate, NULL); + err |= control (file, "abs", _abs, __abs, NULL); + + err |= reg (file, _reg_file, _reg_nr); + if (err == -1) + return 0; + if (_subreg_nr) + format (file, ".%d", _subreg_nr); + string (file, "<"); + err |= control (file, "vert stride", vert_stride, _vert_stride, NULL); + string (file, ",1,1>"); + err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL); + /* + * Three kinds of swizzle display: + * identity - nothing printed + * 1->all - print the single channel + * 1->1 - print the mapping + */ + if (swz_x == BRW_CHANNEL_X && + swz_y == BRW_CHANNEL_Y && + swz_z == BRW_CHANNEL_Z && + swz_w == BRW_CHANNEL_W) + { + ; + } + else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w) + { + string (file, "."); + err |= control (file, "channel select", chan_sel, swz_x, NULL); + } + else + { + string (file, "."); + err |= control (file, "channel select", chan_sel, swz_x, NULL); + err |= control (file, "channel select", chan_sel, swz_y, NULL); + err |= control (file, "channel select", chan_sel, swz_z, NULL); + err |= control (file, "channel select", chan_sel, swz_w, NULL); + } + return err; +} + + +static int imm (FILE *file, GLuint type, struct brw_instruction *inst) { + switch (type) { + case BRW_REGISTER_TYPE_UD: + format (file, "0x%08xUD", inst->bits3.ud); + break; + case BRW_REGISTER_TYPE_D: + format (file, "%dD", inst->bits3.id); + break; + case BRW_REGISTER_TYPE_UW: + format (file, "0x%04xUW", (uint16_t) inst->bits3.ud); + break; + case BRW_REGISTER_TYPE_W: + format (file, "%dW", (int16_t) inst->bits3.id); + break; + case BRW_REGISTER_TYPE_UB: + format (file, "0x%02xUB", (int8_t) inst->bits3.ud); + break; + case BRW_REGISTER_TYPE_VF: + format (file, "Vector Float"); + break; + case BRW_REGISTER_TYPE_V: + format (file, "0x%08xV", inst->bits3.ud); + break; + case BRW_REGISTER_TYPE_F: + format (file, "%-gF", inst->bits3.fd); + } + return 0; +} + +static int src0 (FILE *file, struct brw_instruction *inst) +{ + if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE) + return imm (file, inst->bits1.da1.src0_reg_type, + inst); + else if (inst->header.access_mode == BRW_ALIGN_1) + { + if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT) + { + return src_da1 (file, + inst->bits1.da1.src0_reg_type, + inst->bits1.da1.src0_reg_file, + inst->bits2.da1.src0_vert_stride, + inst->bits2.da1.src0_width, + inst->bits2.da1.src0_horiz_stride, + inst->bits2.da1.src0_reg_nr, + inst->bits2.da1.src0_subreg_nr, + inst->bits2.da1.src0_abs, + inst->bits2.da1.src0_negate); + } + else + { + return src_ia1 (file, + inst->bits1.ia1.src0_reg_type, + inst->bits1.ia1.src0_reg_file, + inst->bits2.ia1.src0_indirect_offset, + inst->bits2.ia1.src0_subreg_nr, + inst->bits2.ia1.src0_negate, + inst->bits2.ia1.src0_abs, + inst->bits2.ia1.src0_address_mode, + inst->bits2.ia1.src0_horiz_stride, + inst->bits2.ia1.src0_width, + inst->bits2.ia1.src0_vert_stride); + } + } + else + { + if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT) + { + return src_da16 (file, + inst->bits1.da16.src0_reg_type, + inst->bits1.da16.src0_reg_file, + inst->bits2.da16.src0_vert_stride, + inst->bits2.da16.src0_reg_nr, + inst->bits2.da16.src0_subreg_nr, + inst->bits2.da16.src0_abs, + inst->bits2.da16.src0_negate, + inst->bits2.da16.src0_swz_x, + inst->bits2.da16.src0_swz_y, + inst->bits2.da16.src0_swz_z, + inst->bits2.da16.src0_swz_w); + } + else + { + string (file, "Indirect align16 address mode not supported"); + return 1; + } + } +} + +static int src1 (FILE *file, struct brw_instruction *inst) +{ + if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE) + return imm (file, inst->bits1.da1.src1_reg_type, + inst); + else if (inst->header.access_mode == BRW_ALIGN_1) + { + if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT) + { + return src_da1 (file, + inst->bits1.da1.src1_reg_type, + inst->bits1.da1.src1_reg_file, + inst->bits3.da1.src1_vert_stride, + inst->bits3.da1.src1_width, + inst->bits3.da1.src1_horiz_stride, + inst->bits3.da1.src1_reg_nr, + inst->bits3.da1.src1_subreg_nr, + inst->bits3.da1.src1_abs, + inst->bits3.da1.src1_negate); + } + else + { + return src_ia1 (file, + inst->bits1.ia1.src1_reg_type, + inst->bits1.ia1.src1_reg_file, + inst->bits3.ia1.src1_indirect_offset, + inst->bits3.ia1.src1_subreg_nr, + inst->bits3.ia1.src1_negate, + inst->bits3.ia1.src1_abs, + inst->bits3.ia1.src1_address_mode, + inst->bits3.ia1.src1_horiz_stride, + inst->bits3.ia1.src1_width, + inst->bits3.ia1.src1_vert_stride); + } + } + else + { + if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT) + { + return src_da16 (file, + inst->bits1.da16.src1_reg_type, + inst->bits1.da16.src1_reg_file, + inst->bits3.da16.src1_vert_stride, + inst->bits3.da16.src1_reg_nr, + inst->bits3.da16.src1_subreg_nr, + inst->bits3.da16.src1_abs, + inst->bits3.da16.src1_negate, + inst->bits3.da16.src1_swz_x, + inst->bits3.da16.src1_swz_y, + inst->bits3.da16.src1_swz_z, + inst->bits3.da16.src1_swz_w); + } + else + { + string (file, "Indirect align16 address mode not supported"); + return 1; + } + } +} + +int disasm (FILE *file, struct brw_instruction *inst) +{ + int err = 0; + int space = 0; + + if (inst->header.predicate_control) { + string (file, "("); + err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL); + format (file, "f%d", inst->bits2.da1.flag_reg_nr); + if (inst->bits2.da1.flag_subreg_nr) + format (file, ".%d", inst->bits2.da1.flag_subreg_nr); + if (inst->header.access_mode == BRW_ALIGN_1) + err |= control (file, "predicate control align1", pred_ctrl_align1, + inst->header.predicate_control, NULL); + else + err |= control (file, "predicate control align16", pred_ctrl_align16, + inst->header.predicate_control, NULL); + string (file, ") "); + } + + err |= print_opcode (file, inst->header.opcode); + err |= control (file, "saturate", saturate, inst->header.saturate, NULL); + err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL); + + if (inst->header.opcode != BRW_OPCODE_SEND && + inst->header.opcode != BRW_OPCODE_SENDC) + err |= control (file, "conditional modifier", conditional_modifier, + inst->header.sfid_destreg__conditionalmod, NULL); + + if (inst->header.opcode != BRW_OPCODE_NOP) { + string (file, "("); + err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL); + string (file, ")"); + } + + if (inst->header.opcode == BRW_OPCODE_SEND || + inst->header.opcode == BRW_OPCODE_SENDC) + format (file, " %d", inst->header.sfid_destreg__conditionalmod); + + if (opcode[inst->header.opcode].ndst > 0) { + pad (file, 16); + err |= dest (file, inst); + } + if (opcode[inst->header.opcode].nsrc > 0) { + pad (file, 32); + err |= src0 (file, inst); + } + if (opcode[inst->header.opcode].nsrc > 1) { + pad (file, 48); + err |= src1 (file, inst); + } + + if (inst->header.opcode == BRW_OPCODE_SEND || + inst->header.opcode == BRW_OPCODE_SENDC) { + newline (file); + pad (file, 16); + space = 0; + err |= control (file, "target function", target_function, + inst->header.sfid_destreg__conditionalmod, &space); + switch (inst->header.sfid_destreg__conditionalmod) { + case BRW_MESSAGE_TARGET_MATH: + err |= control (file, "math function", math_function, + inst->bits3.math.function, &space); + err |= control (file, "math saturate", math_saturate, + inst->bits3.math.saturate, &space); + err |= control (file, "math signed", math_signed, + inst->bits3.math.int_type, &space); + err |= control (file, "math scalar", math_scalar, + inst->bits3.math.data_type, &space); + err |= control (file, "math precision", math_precision, + inst->bits3.math.precision, &space); + break; + case BRW_MESSAGE_TARGET_SAMPLER: + format (file, " (%d, %d, ", + inst->bits3.sampler.binding_table_index, + inst->bits3.sampler.sampler); + err |= control (file, "sampler target format", sampler_target_format, + inst->bits3.sampler.return_format, NULL); + string (file, ")"); + break; + case BRW_MESSAGE_TARGET_DATAPORT_WRITE: + format (file, " (%d, %d, %d, %d)", + inst->bits3.dp_write.binding_table_index, + (inst->bits3.dp_write.pixel_scoreboard_clear << 3) | + inst->bits3.dp_write.msg_control, + inst->bits3.dp_write.msg_type, + inst->bits3.dp_write.send_commit_msg); + break; + case BRW_MESSAGE_TARGET_URB: + format (file, " %d", inst->bits3.urb.offset); + space = 1; + err |= control (file, "urb swizzle", urb_swizzle, + inst->bits3.urb.swizzle_control, &space); + err |= control (file, "urb allocate", urb_allocate, + inst->bits3.urb.allocate, &space); + err |= control (file, "urb used", urb_used, + inst->bits3.urb.used, &space); + err |= control (file, "urb complete", urb_complete, + inst->bits3.urb.complete, &space); + break; + case BRW_MESSAGE_TARGET_THREAD_SPAWNER: + break; + default: + format (file, "unsupported target %d", inst->bits3.generic.msg_target); + break; + } + if (space) + string (file, " "); + format (file, "mlen %d", + inst->bits3.generic.msg_length); + format (file, " rlen %d", + inst->bits3.generic.response_length); + } + pad (file, 64); + if (inst->header.opcode != BRW_OPCODE_NOP) { + string (file, "{"); + space = 1; + err |= control(file, "access mode", access_mode, inst->header.access_mode, &space); + err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space); + err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space); + err |= control (file, "compression control", compr_ctrl, inst->header.compression_control, &space); + err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space); + if (inst->header.opcode == BRW_OPCODE_SEND) + err |= control (file, "end of thread", end_of_thread, + inst->bits3.generic.end_of_thread, &space); + if (space) + string (file, " "); + string (file, "}"); + } + string (file, ";"); + newline (file); + return err; +} diff --git a/assembler/gen4asm.h b/assembler/gen4asm.h new file mode 100644 index 00000000..f9ed161d --- /dev/null +++ b/assembler/gen4asm.h @@ -0,0 +1,202 @@ +/* -*- c-basic-offset: 8 -*- */ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include + +typedef unsigned char GLubyte; +typedef short GLshort; +typedef unsigned int GLuint; +typedef int GLint; +typedef float GLfloat; + +extern long int gen_level; + +/* Predicate for Gen X and above */ +#define IS_GENp(x) (gen_level >= (x)*10) + +/* Predicate for Gen X exactly */ +#define IS_GENx(x) (gen_level >= (x)*10 && gen_level < ((x)+1)*10) + +/* Predicate to match Haswell processors */ +#define IS_HASWELL(x) (gen_level == 75) + +#include "brw_defines.h" +#include "brw_structs.h" + +void yyerror (char *msg); + +/** + * This structure is the internal representation of directly-addressed + * registers in the parser. + */ +struct direct_reg { + int reg_file, reg_nr, subreg_nr; +}; + +struct condition { + int cond; + int flag_reg_nr; + int flag_subreg_nr; +}; + +struct region { + int vert_stride, width, horiz_stride; + int is_default; +}; +struct regtype { + int type; + int is_default; +}; +/** + * This structure is the internal representation of register-indirect addressed + * registers in the parser. + */ + +struct indirect_reg { + int reg_file, address_subreg_nr, indirect_offset; +}; + +/** + * This structure is the internal representation of destination operands in the + * parser. + */ +struct dst_operand { + int reg_file, reg_nr, subreg_nr, reg_type; + + int writemask_set; + int writemask; + + int horiz_stride; + int address_mode; /* 0 if direct, 1 if register-indirect */ + + /* Indirect addressing */ + int address_subreg_nr; + int indirect_offset; +}; + +/** + * This structure is the internal representation of source operands in the + * parser. + */ +struct src_operand { + int reg_file, reg_nr, subreg_nr, reg_type; + + int abs, negate; + + int horiz_stride, width, vert_stride; + int default_region; + + int address_mode; /* 0 if direct, 1 if register-indirect */ + int address_subreg_nr; + int indirect_offset; /* XXX */ + + int swizzle_set; + int swizzle_x, swizzle_y, swizzle_z, swizzle_w; + + uint32_t imm32; /* set if reg_file == BRW_IMMEDIATE_VALUE or it is expressing a branch offset */ + char *reloc_target; /* bspec: branching instructions JIP and UIP are source operands */ +} src_operand; + +typedef struct { + enum { + imm32_d, imm32_f + } r; + union { + uint32_t d; + float f; + int32_t signed_d; + } u; +} imm32_t; + +/** + * This structure is just the list container for instructions accumulated by + * the parser and labels. + */ +struct brw_program_instruction { + struct brw_instruction instruction; + struct brw_program_instruction *next; + GLuint islabel; + GLuint inst_offset; + char *string; +}; + +/** + * This structure is a list of instructions. It is the final output of the + * parser. + */ +struct brw_program { + struct brw_program_instruction *first; + struct brw_program_instruction *last; +}; + +extern struct brw_program compiled_program; + +#define TYPE_B_INDEX 0 +#define TYPE_UB_INDEX 1 +#define TYPE_W_INDEX 2 +#define TYPE_UW_INDEX 3 +#define TYPE_D_INDEX 4 +#define TYPE_UD_INDEX 5 +#define TYPE_F_INDEX 6 + +#define TOTAL_TYPES 7 + +struct program_defaults { + int execute_size; + int execute_type[TOTAL_TYPES]; + int register_type; + int register_type_regfile; + struct region source_region; + struct region source_region_type[TOTAL_TYPES]; + struct region dest_region; + struct region dest_region_type[TOTAL_TYPES]; +}; +extern struct program_defaults program_defaults; + +struct declared_register { + char *name; + struct direct_reg base; + int element_size; + struct region src_region; + int dst_region; + int type; +}; +struct declared_register *find_register(char *name); +void insert_register(struct declared_register *reg); +void add_label(char *name, int addr); +int label_to_addr(char *name, int start_addr); + +int yyparse(void); +int yylex(void); +int yylex_destroy(void); + +char * +lex_text(void); + +int +disasm (FILE *output, struct brw_instruction *inst); diff --git a/assembler/gram.y b/assembler/gram.y new file mode 100644 index 00000000..2ed79c13 --- /dev/null +++ b/assembler/gram.y @@ -0,0 +1,3167 @@ +%{ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include +#include +#include +#include "gen4asm.h" +#include "brw_defines.h" + +#define DEFAULT_EXECSIZE (ffs(program_defaults.execute_size) - 1) +#define DEFAULT_DSTREGION -1 + +extern long int gen_level; +extern int advanced_flag; +extern int yylineno; +extern int need_export; +static struct src_operand src_null_reg = +{ + .reg_file = BRW_ARCHITECTURE_REGISTER_FILE, + .reg_nr = BRW_ARF_NULL, + .reg_type = BRW_REGISTER_TYPE_UD, +}; +static struct dst_operand dst_null_reg = +{ + .reg_file = BRW_ARCHITECTURE_REGISTER_FILE, + .reg_nr = BRW_ARF_NULL, +}; +static struct dst_operand ip_dst = +{ + .reg_file = BRW_ARCHITECTURE_REGISTER_FILE, + .reg_nr = BRW_ARF_IP, + .reg_type = BRW_REGISTER_TYPE_UD, + .address_mode = BRW_ADDRESS_DIRECT, + .horiz_stride = 1, + .writemask = 0xF, +}; +static struct src_operand ip_src = +{ + .reg_file = BRW_ARCHITECTURE_REGISTER_FILE, + .reg_nr = BRW_ARF_IP, + .reg_type = BRW_REGISTER_TYPE_UD, + .address_mode = BRW_ADDRESS_DIRECT, + .swizzle_x = BRW_CHANNEL_X, + .swizzle_y = BRW_CHANNEL_Y, + .swizzle_z = BRW_CHANNEL_Z, + .swizzle_w = BRW_CHANNEL_W, +}; + +static int get_type_size(GLuint type); +int set_instruction_dest(struct brw_instruction *instr, + struct dst_operand *dest); +int set_instruction_src0(struct brw_instruction *instr, + struct src_operand *src); +int set_instruction_src1(struct brw_instruction *instr, + struct src_operand *src); +int set_instruction_dest_three_src(struct brw_instruction *instr, + struct dst_operand *dest); +int set_instruction_src0_three_src(struct brw_instruction *instr, + struct src_operand *src); +int set_instruction_src1_three_src(struct brw_instruction *instr, + struct src_operand *src); +int set_instruction_src2_three_src(struct brw_instruction *instr, + struct src_operand *src); +void set_instruction_options(struct brw_instruction *instr, + struct brw_instruction *options); +void set_instruction_predicate(struct brw_instruction *instr, + struct brw_instruction *predicate); +void set_direct_dst_operand(struct dst_operand *dst, struct direct_reg *reg, + int type); +void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg, + int type); + +%} + +%start ROOT + +%union { + char *string; + int integer; + double number; + struct brw_instruction instruction; + struct brw_program program; + struct region region; + struct regtype regtype; + struct direct_reg direct_reg; + struct indirect_reg indirect_reg; + struct condition condition; + struct declared_register symbol_reg; + imm32_t imm32; + + struct dst_operand dst_operand; + struct src_operand src_operand; +} + +%token COLON +%token SEMICOLON +%token LPAREN RPAREN +%token LANGLE RANGLE +%token LCURLY RCURLY +%token LSQUARE RSQUARE +%token COMMA EQ +%token ABS DOT +%token PLUS MINUS MULTIPLY DIVIDE + +%token TYPE_UD TYPE_D TYPE_UW TYPE_W TYPE_UB TYPE_B +%token TYPE_VF TYPE_HF TYPE_V TYPE_F + +%token ALIGN1 ALIGN16 SECHALF COMPR SWITCH ATOMIC NODDCHK NODDCLR +%token MASK_DISABLE BREAKPOINT ACCWRCTRL EOT + +%token SEQ ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H ANYV ALLV +%token ZERO EQUAL NOT_ZERO NOT_EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL +%token ROUND_INCREMENT OVERFLOW UNORDERED +%token GENREG MSGREG ADDRESSREG ACCREG FLAGREG +%token MASKREG AMASK IMASK LMASK CMASK +%token MASKSTACKREG LMS IMS MASKSTACKDEPTHREG IMSD LMSD +%token NOTIFYREG STATEREG CONTROLREG IPREG +%token GENREGFILE MSGREGFILE + +%token MOV FRC RNDU RNDD RNDE RNDZ NOT LZD +%token MUL MAC MACH LINE SAD2 SADA2 DP4 DPH DP3 DP2 +%token AVG ADD SEL AND OR XOR SHR SHL ASR CMP CMPN PLN +%token ADDC BFI1 BFREV CBIT F16TO32 F32TO16 FBH FBL +%token SEND NOP JMPI IF IFF WHILE ELSE BREAK CONT HALT MSAVE +%token PUSH MREST POP WAIT DO ENDIF ILLEGAL +%token MATH_INST +%token MAD LRP BFE BFI2 SUBB +%token CALL RET +%token BRD BRC + +%token NULL_TOKEN MATH SAMPLER GATEWAY READ WRITE URB THREAD_SPAWNER VME DATA_PORT CRE + +%token MSGLEN RETURNLEN +%token ALLOCATE USED COMPLETE TRANSPOSE INTERLEAVE +%token SATURATE + +%token INTEGER +%token STRING +%token NUMBER + +%token INV LOG EXP SQRT RSQ POW SIN COS SINCOS INTDIV INTMOD +%token INTDIVMOD +%token SIGNED SCALAR + +%token X Y Z W + +%token KERNEL_PRAGMA END_KERNEL_PRAGMA CODE_PRAGMA END_CODE_PRAGMA +%token REG_COUNT_PAYLOAD_PRAGMA REG_COUNT_TOTAL_PRAGMA DECLARE_PRAGMA +%token BASE ELEMENTSIZE SRCREGION DSTREGION TYPE + +%token DEFAULT_EXEC_SIZE_PRAGMA DEFAULT_REG_TYPE_PRAGMA +%nonassoc SUBREGNUM +%nonassoc SNDOPR +%left PLUS MINUS +%left MULTIPLY DIVIDE +%right UMINUS +%nonassoc DOT +%nonassoc STR_SYMBOL_REG +%nonassoc EMPTEXECSIZE +%nonassoc LPAREN + +%type exp sndopr +%type simple_int +%type instruction unaryinstruction binaryinstruction +%type binaryaccinstruction trinaryinstruction sendinstruction +%type jumpinstruction +%type breakinstruction syncinstruction +%type msgtarget +%type instoptions instoption_list predicate +%type mathinstruction +%type subroutineinstruction +%type multibranchinstruction +%type nopinstruction loopinstruction ifelseinstruction haltinstruction +%type label +%type instrseq +%type instoption +%type unaryop binaryop binaryaccop breakop +%type trinaryop +%type conditionalmodifier +%type condition saturate negate abs chansel +%type writemask_x writemask_y writemask_z writemask_w +%type srcimmtype execsize dstregion immaddroffset +%type subregnum sampler_datatype +%type urb_swizzle urb_allocate urb_used urb_complete +%type math_function math_signed math_scalar +%type predctrl predstate +%type region region_wh indirectregion declare_srcregion; +%type regtype +%type directgenreg directmsgreg addrreg accreg flagreg maskreg +%type maskstackreg notifyreg +/* %type maskstackdepthreg */ +%type statereg controlreg ipreg nullreg +%type dstoperandex_typed srcarchoperandex_typed +%type sendleadreg +%type indirectgenreg indirectmsgreg addrparam +%type mask_subreg maskstack_subreg +%type declare_elementsize declare_dstregion declare_type +/* %type maskstackdepth_subreg */ +%type symbol_reg symbol_reg_p; +%type imm32 +%type dst dstoperand dstoperandex dstreg post_dst writemask +%type declare_base +%type directsrcoperand srcarchoperandex directsrcaccoperand +%type indirectsrcoperand +%type src srcimm imm32reg payload srcacc srcaccimm swizzle +%type relativelocation relativelocation2 +%% +simple_int: INTEGER { $$ = $1; } + | MINUS INTEGER { $$ = -$2;} +; + +exp: INTEGER { $$ = $1; } + | exp PLUS exp { $$ = $1 + $3; } + | exp MINUS exp { $$ = $1 - $3; } + | exp MULTIPLY exp { $$ = $1 * $3; } + | exp DIVIDE exp { if ($3) $$ = $1 / $3; else YYERROR;} + | MINUS exp %prec UMINUS { $$ = -$2;} + | LPAREN exp RPAREN { $$ = $2; } + ; + +ROOT: instrseq + { + compiled_program = $1; + } +; + + +label: STRING COLON +; + +declare_base: BASE EQ dstreg + { + $$ = $3; + } +; +declare_elementsize: ELEMENTSIZE EQ exp + { + $$ = $3; + } +; +declare_srcregion: /* empty */ + { + /* XXX is this default correct?*/ + memset (&$$, '\0', sizeof ($$)); + $$.vert_stride = ffs(0); + $$.width = ffs(1) - 1; + $$.horiz_stride = ffs(0); + } + | SRCREGION EQ region + { + $$ = $3; + } +; +declare_dstregion: /* empty */ + { + $$ = 1; + } + | DSTREGION EQ dstregion + { + $$ = $3; + } +; +declare_type: TYPE EQ regtype + { + $$ = $3.type; + } +; +declare_pragma: DECLARE_PRAGMA STRING declare_base declare_elementsize declare_srcregion declare_dstregion declare_type + { + struct declared_register *reg; + int defined; + defined = (reg = find_register($2)) != NULL; + if (defined) { + fprintf(stderr, "WARNING: %s already defined\n", $2); + free($2); // $2 has been malloc'ed by strdup + } else { + reg = calloc(sizeof(struct declared_register), 1); + reg->name = $2; + } + reg->base.reg_file = $3.reg_file; + reg->base.reg_nr = $3.reg_nr; + reg->base.subreg_nr = $3.subreg_nr; + reg->element_size = $4; + reg->src_region = $5; + reg->dst_region = $6; + reg->type = $7; + if (!defined) { + insert_register(reg); + } + } +; + +reg_count_total_pragma: REG_COUNT_TOTAL_PRAGMA exp +; +reg_count_payload_pragma: REG_COUNT_PAYLOAD_PRAGMA exp +; + +default_exec_size_pragma: DEFAULT_EXEC_SIZE_PRAGMA exp + { + program_defaults.execute_size = $2; + } +; +default_reg_type_pragma: DEFAULT_REG_TYPE_PRAGMA regtype + { + program_defaults.register_type = $2.type; + } +; +pragma: reg_count_total_pragma + |reg_count_payload_pragma + |default_exec_size_pragma + |default_reg_type_pragma + |declare_pragma +; + +instrseq: instrseq pragma + { + $$ = $1; + } + | instrseq instruction SEMICOLON + { + struct brw_program_instruction *list_entry = + calloc(sizeof(struct brw_program_instruction), 1); + list_entry->instruction = $2; + list_entry->next = NULL; + if ($1.last) { + $1.last->next = list_entry; + } else { + $1.first = list_entry; + } + $1.last = list_entry; + $$ = $1; + } + | instruction SEMICOLON + { + struct brw_program_instruction *list_entry = + calloc(sizeof(struct brw_program_instruction), 1); + list_entry->instruction = $1; + + list_entry->next = NULL; + + $$.first = list_entry; + $$.last = list_entry; + } + | instrseq SEMICOLON + { + $$ = $1; + } + | instrseq label + { + struct brw_program_instruction *list_entry = + calloc(sizeof(struct brw_program_instruction), 1); + list_entry->string = strdup($2); + list_entry->islabel = 1; + list_entry->next = NULL; + if ($1.last) { + $1.last->next = list_entry; + } else { + $1.first = list_entry; + } + $1.last = list_entry; + $$ = $1; + } + | label + { + struct brw_program_instruction *list_entry = + calloc(sizeof(struct brw_program_instruction), 1); + list_entry->string = strdup($1); + list_entry->islabel = 1; + + list_entry->next = NULL; + + $$.first = list_entry; + $$.last = list_entry; + } + | pragma + { + $$.first = NULL; + $$.last = NULL; + } + | instrseq error SEMICOLON { + $$ = $1; + } +; + +/* 1.4.1: Instruction groups */ +// binaryinstruction: Source operands cannot be accumulators +// binaryaccinstruction: Source operands can be accumulators +instruction: unaryinstruction + | binaryinstruction + | binaryaccinstruction + | trinaryinstruction + | sendinstruction + | jumpinstruction + | ifelseinstruction + | breakinstruction + | syncinstruction + | mathinstruction + | subroutineinstruction + | multibranchinstruction + | nopinstruction + | haltinstruction + | loopinstruction +; + +ifelseinstruction: ENDIF + { + // for Gen4 + if(IS_GENp(6)) { // For gen6+. + fprintf(stderr, "ENDIF Syntax error: should be 'ENDIF execsize relativelocation'\n"); + YYERROR; + } + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $1; + $$.header.thread_control |= BRW_THREAD_SWITCH; + $$.bits1.da1.dest_horiz_stride = 1; + $$.bits1.da1.src1_reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.bits1.da1.src1_reg_type = BRW_REGISTER_TYPE_UD; + } + | ENDIF execsize relativelocation instoptions + { + // for Gen6+ + /* Gen6, Gen7 bspec: predication is prohibited */ + if(!IS_GENp(6)) { // for gen6- + fprintf(stderr, "ENDIF Syntax error: should be 'ENDIF'\n"); + YYERROR; + } + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $1; + $$.header.execution_size = $2; + $$.first_reloc_target = $3.reloc_target; + $$.first_reloc_offset = $3.imm32; + } + | ELSE execsize relativelocation instoptions + { + if(!IS_GENp(6)) { + // for Gen4, Gen5. gen_level < 60 + /* Set the istack pop count, which must always be 1. */ + $3.imm32 |= (1 << 16); + + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $1; + $$.header.execution_size = $2; + $$.header.thread_control |= BRW_THREAD_SWITCH; + set_instruction_dest(&$$, &ip_dst); + set_instruction_src0(&$$, &ip_src); + set_instruction_src1(&$$, &$3); + $$.first_reloc_target = $3.reloc_target; + $$.first_reloc_offset = $3.imm32; + } else if(IS_GENp(6)) { + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $1; + $$.header.execution_size = $2; + $$.first_reloc_target = $3.reloc_target; + $$.first_reloc_offset = $3.imm32; + } else { + fprintf(stderr, "'ELSE' instruction is not implemented.\n"); + YYERROR; + } + } + | predicate IF execsize relativelocation + { + /* for Gen4, Gen5 */ + /* The branch instructions require that the IP register + * be the destination and first source operand, while the + * offset is the second source operand. The offset is added + * to the pre-incremented IP. + */ + /* for Gen6 */ + if(IS_GENp(7)) { + /* Error in Gen7+. */ + fprintf(stderr, "Syntax error: IF should be 'IF execsize JIP UIP'\n"); + YYERROR; + } + memset(&$$, 0, sizeof($$)); + set_instruction_predicate(&$$, &$1); + $$.header.opcode = $2; + $$.header.execution_size = $3; + if(!IS_GENp(6)) { + $$.header.thread_control |= BRW_THREAD_SWITCH; + set_instruction_dest(&$$, &ip_dst); + set_instruction_src0(&$$, &ip_src); + set_instruction_src1(&$$, &$4); + } + $$.first_reloc_target = $4.reloc_target; + $$.first_reloc_offset = $4.imm32; + } + | predicate IF execsize relativelocation relativelocation + { + /* for Gen7+ */ + if(!IS_GENp(7)) { + fprintf(stderr, "Syntax error: IF should be 'IF execsize relativelocation'\n"); + YYERROR; + } + memset(&$$, 0, sizeof($$)); + set_instruction_predicate(&$$, &$1); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.first_reloc_target = $4.reloc_target; + $$.first_reloc_offset = $4.imm32; + $$.second_reloc_target = $5.reloc_target; + $$.second_reloc_offset = $5.imm32; + } +; + +loopinstruction: predicate WHILE execsize relativelocation instoptions + { + if(!IS_GENp(6)) { + /* The branch instructions require that the IP register + * be the destination and first source operand, while the + * offset is the second source operand. The offset is added + * to the pre-incremented IP. + */ + set_instruction_dest(&$$, &ip_dst); + memset(&$$, 0, sizeof($$)); + set_instruction_predicate(&$$, &$1); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.thread_control |= BRW_THREAD_SWITCH; + set_instruction_src0(&$$, &ip_src); + set_instruction_src1(&$$, &$4); + $$.first_reloc_target = $4.reloc_target; + $$.first_reloc_offset = $4.imm32; + } else if (IS_GENp(6)) { + /* Gen6 spec: + dest must have the same element size as src0. + dest horizontal stride must be 1. */ + memset(&$$, 0, sizeof($$)); + set_instruction_predicate(&$$, &$1); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.first_reloc_target = $4.reloc_target; + $$.first_reloc_offset = $4.imm32; + } else { + fprintf(stderr, "'WHILE' instruction is not implemented!\n"); + YYERROR; + } + } + | DO + { + // deprecated + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $1; + }; + +haltinstruction: predicate HALT execsize relativelocation relativelocation instoptions + { + // for Gen6, Gen7 + /* Gen6, Gen7 bspec: dst and src0 must be the null reg. */ + memset(&$$, 0, sizeof($$)); + set_instruction_predicate(&$$, &$1); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.first_reloc_target = $4.reloc_target; + $$.first_reloc_offset = $4.imm32; + $$.second_reloc_target = $5.reloc_target; + $$.second_reloc_offset = $5.imm32; + set_instruction_dest(&$$, &dst_null_reg); + set_instruction_src0(&$$, &src_null_reg); + }; + +multibranchinstruction: + predicate BRD execsize relativelocation instoptions + { + /* Gen7 bspec: dest must be null. use Switch option */ + memset(&$$, 0, sizeof($$)); + set_instruction_predicate(&$$, &$1); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.thread_control |= BRW_THREAD_SWITCH; + $$.first_reloc_target = $4.reloc_target; + $$.first_reloc_offset = $4.imm32; + set_instruction_dest(&$$, &dst_null_reg); + } + | predicate BRC execsize relativelocation relativelocation instoptions + { + /* Gen7 bspec: dest must be null. src0 must be null. use Switch option */ + memset(&$$, 0, sizeof($$)); + set_instruction_predicate(&$$, &$1); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.thread_control |= BRW_THREAD_SWITCH; + $$.first_reloc_target = $4.reloc_target; + $$.first_reloc_offset = $4.imm32; + $$.second_reloc_target = $5.reloc_target; + $$.second_reloc_offset = $5.imm32; + set_instruction_dest(&$$, &dst_null_reg); + set_instruction_src0(&$$, &src_null_reg); + } +; + +subroutineinstruction: + predicate CALL execsize dst relativelocation instoptions + { + /* + Gen6 bspec: + source, dest type should be DWORD. + dest must be QWord aligned. + source0 region control must be <2,2,1>. + execution size must be 2. + QtrCtrl is prohibited. + JIP is an immediate operand, must be of type W. + Gen7 bspec: + source, dest type should be DWORD. + dest must be QWord aligned. + source0 region control must be <2,2,1>. + execution size must be 2. + */ + memset(&$$, 0, sizeof($$)); + set_instruction_predicate(&$$, &$1); + $$.header.opcode = $2; + $$.header.execution_size = 1; /* execution size must be 2. Here 1 is encoded 2. */ + + $4.reg_type = BRW_REGISTER_TYPE_D; /* dest type should be DWORD */ + set_instruction_dest(&$$, &$4); + + struct src_operand src0; + memset(&src0, 0, sizeof(src0)); + src0.reg_type = BRW_REGISTER_TYPE_D; /* source type should be DWORD */ + /* source0 region control must be <2,2,1>. */ + src0.horiz_stride = 1; /*encoded 1*/ + src0.width = 1; /*encoded 2*/ + src0.vert_stride = 2; /*encoded 2*/ + set_instruction_src0(&$$, &src0); + + $$.first_reloc_target = $5.reloc_target; + $$.first_reloc_offset = $5.imm32; + } + | predicate RET execsize dstoperandex src instoptions + { + /* + Gen6, 7: + source cannot be accumulator. + dest must be null. + src0 region control must be <2,2,1> (not specified clearly. should be same as CALL) + */ + memset(&$$, 0, sizeof($$)); + set_instruction_predicate(&$$, &$1); + $$.header.opcode = $2; + $$.header.execution_size = 1; /* execution size of RET should be 2 */ + set_instruction_dest(&$$, &dst_null_reg); + $5.reg_type = BRW_REGISTER_TYPE_D; + $5.horiz_stride = 1; /*encoded 1*/ + $5.width = 1; /*encoded 2*/ + $5.vert_stride = 2; /*encoded 2*/ + set_instruction_src0(&$$, &$5); + } +; + +unaryinstruction: + predicate unaryop conditionalmodifier saturate execsize + dst srcaccimm instoptions + { + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.sfid_destreg__conditionalmod = $3.cond; + $$.header.saturate = $4; + $$.header.execution_size = $5; + set_instruction_options(&$$, &$8); + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$6) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$7) != 0) + YYERROR; + + if ($3.flag_subreg_nr != -1) { + if ($$.header.predicate_control != BRW_PREDICATE_NONE && + ($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr || + $1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) + fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n"); + + $$.bits2.da1.flag_reg_nr = $3.flag_reg_nr; + $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; + } + + if (!IS_GENp(6) && + get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) + $$.header.compression_control = BRW_COMPRESSION_COMPRESSED; + } +; + +unaryop: MOV | FRC | RNDU | RNDD | RNDE | RNDZ | NOT | LZD | BFREV | CBIT + | F16TO32 | F32TO16 | FBH | FBL +; + +// Source operands cannot be accumulators +binaryinstruction: + predicate binaryop conditionalmodifier saturate execsize + dst src srcimm instoptions + { + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.sfid_destreg__conditionalmod = $3.cond; + $$.header.saturate = $4; + $$.header.execution_size = $5; + set_instruction_options(&$$, &$9); + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$6) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$7) != 0) + YYERROR; + if (set_instruction_src1(&$$, &$8) != 0) + YYERROR; + + if ($3.flag_subreg_nr != -1) { + if ($$.header.predicate_control != BRW_PREDICATE_NONE && + ($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr || + $1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) + fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n"); + + $$.bits2.da1.flag_reg_nr = $3.flag_reg_nr; + $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; + } + + if (!IS_GENp(6) && + get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) + $$.header.compression_control = BRW_COMPRESSION_COMPRESSED; + } +; + +/* bspec: BFI1 should not access accumulator. */ +binaryop: MUL | MAC | MACH | LINE | SAD2 | SADA2 | DP4 | DPH | DP3 | DP2 | PLN | BFI1 +; + +// Source operands can be accumulators +binaryaccinstruction: + predicate binaryaccop conditionalmodifier saturate execsize + dst srcacc srcimm instoptions + { + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.sfid_destreg__conditionalmod = $3.cond; + $$.header.saturate = $4; + $$.header.execution_size = $5; + set_instruction_options(&$$, &$9); + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$6) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$7) != 0) + YYERROR; + if (set_instruction_src1(&$$, &$8) != 0) + YYERROR; + + if ($3.flag_subreg_nr != -1) { + if ($$.header.predicate_control != BRW_PREDICATE_NONE && + ($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr || + $1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) + fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n"); + + $$.bits2.da1.flag_reg_nr = $3.flag_reg_nr; + $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; + } + + if (!IS_GENp(6) && + get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) + $$.header.compression_control = BRW_COMPRESSION_COMPRESSED; + } +; + +/* TODO: bspec says ADDC/SUBB/CMP/CMPN/SHL/BFI1 cannot use accumulator as dest. */ +binaryaccop: AVG | ADD | SEL | AND | OR | XOR | SHR | SHL | ASR | CMP | CMPN | ADDC | SUBB +; + +trinaryop: MAD | LRP | BFE | BFI2 +; + +trinaryinstruction: + predicate trinaryop conditionalmodifier saturate execsize + dst src src src instoptions +{ + memset(&$$, 0, sizeof($$)); + + $$.header.predicate_control = $1.header.predicate_control; + $$.header.predicate_inverse = $1.header.predicate_inverse; + $$.bits1.three_src_gen6.flag_reg_nr = $1.bits2.da1.flag_reg_nr; + $$.bits1.three_src_gen6.flag_subreg_nr = $1.bits2.da1.flag_subreg_nr; + + $$.header.opcode = $2; + $$.header.sfid_destreg__conditionalmod = $3.cond; + $$.header.saturate = $4; + $$.header.execution_size = $5; + + if (set_instruction_dest_three_src(&$$, &$6)) + YYERROR; + if (set_instruction_src0_three_src(&$$, &$7)) + YYERROR; + if (set_instruction_src1_three_src(&$$, &$8)) + YYERROR; + if (set_instruction_src2_three_src(&$$, &$9)) + YYERROR; + set_instruction_options(&$$, &$10); + + if ($3.flag_subreg_nr != -1) { + if ($$.header.predicate_control != BRW_PREDICATE_NONE && + ($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr || + $1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) + fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n"); + } +} +; + +sendinstruction: predicate SEND execsize exp post_dst payload msgtarget + MSGLEN exp RETURNLEN exp instoptions + { + /* Send instructions are messy. The first argument is the + * post destination -- the grf register that the response + * starts from. The second argument is the current + * destination, which is the start of the message arguments + * to the shared function, and where src0 payload is loaded + * to if not null. The payload is typically based on the + * grf 0 thread payload of your current thread, and is + * implicitly loaded if non-null. + */ + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */ + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$5) != 0) + YYERROR; + + if (IS_GENp(6)) { + struct src_operand src0; + + memset(&src0, 0, sizeof(src0)); + src0.address_mode = BRW_ADDRESS_DIRECT; + + if (IS_GENp(7)) + src0.reg_file = BRW_GENERAL_REGISTER_FILE; + else + src0.reg_file = BRW_MESSAGE_REGISTER_FILE; + + src0.reg_type = BRW_REGISTER_TYPE_D; + src0.reg_nr = $4; + src0.subreg_nr = 0; + set_instruction_src0(&$$, &src0); + } else { + if (set_instruction_src0(&$$, &$6) != 0) + YYERROR; + } + + $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; + $$.bits1.da1.src1_reg_type = BRW_REGISTER_TYPE_D; + + if (IS_GENp(5)) { + if (IS_GENp(6)) { + $$.header.sfid_destreg__conditionalmod = $7.bits2.send_gen5.sfid; + } else { + $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */ + $$.bits2.send_gen5.sfid = $7.bits2.send_gen5.sfid; + $$.bits2.send_gen5.end_of_thread = $12.bits3.generic_gen5.end_of_thread; + } + + $$.bits3.generic_gen5 = $7.bits3.generic_gen5; + $$.bits3.generic_gen5.msg_length = $9; + $$.bits3.generic_gen5.response_length = $11; + $$.bits3.generic_gen5.end_of_thread = + $12.bits3.generic_gen5.end_of_thread; + } else { + $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */ + $$.bits3.generic = $7.bits3.generic; + $$.bits3.generic.msg_length = $9; + $$.bits3.generic.response_length = $11; + $$.bits3.generic.end_of_thread = + $12.bits3.generic.end_of_thread; + } + } + | predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions + { + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ + + set_instruction_predicate(&$$, &$1); + + if (set_instruction_dest(&$$, &$4) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$6) != 0) + YYERROR; + /* XXX is this correct? */ + if (set_instruction_src1(&$$, &$7) != 0) + YYERROR; + } + | predicate SEND execsize dst sendleadreg payload imm32reg instoptions + { + if ($7.reg_type != BRW_REGISTER_TYPE_UD && + $7.reg_type != BRW_REGISTER_TYPE_D && + $7.reg_type != BRW_REGISTER_TYPE_V) { + fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $7.imm32, $7.reg_type); + YYERROR; + } + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ + + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$4) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$6) != 0) + YYERROR; + $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; + $$.bits1.da1.src1_reg_type = $7.reg_type; + $$.bits3.ud = $7.imm32; + } + | predicate SEND execsize dst sendleadreg sndopr imm32reg instoptions + { + struct src_operand src0; + + if (!IS_GENp(6)) { + fprintf(stderr, "error: the syntax of send instruction\n"); + YYERROR; + } + + if ($7.reg_type != BRW_REGISTER_TYPE_UD && + $7.reg_type != BRW_REGISTER_TYPE_D && + $7.reg_type != BRW_REGISTER_TYPE_V) { + fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $7.imm32, $7.reg_type); + YYERROR; + } + + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.sfid_destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ + set_instruction_predicate(&$$, &$1); + + if (set_instruction_dest(&$$, &$4) != 0) + YYERROR; + + memset(&src0, 0, sizeof(src0)); + src0.address_mode = BRW_ADDRESS_DIRECT; + + if (IS_GENp(7)) { + src0.reg_file = BRW_GENERAL_REGISTER_FILE; + src0.reg_type = BRW_REGISTER_TYPE_UB; + } else { + src0.reg_file = BRW_MESSAGE_REGISTER_FILE; + src0.reg_type = BRW_REGISTER_TYPE_D; + } + + src0.reg_nr = $5.reg_nr; + src0.subreg_nr = 0; + set_instruction_src0(&$$, &src0); + + $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; + $$.bits1.da1.src1_reg_type = $7.reg_type; + $$.bits3.ud = $7.imm32; + $$.bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); + } + | predicate SEND execsize dst sendleadreg sndopr directsrcoperand instoptions + { + struct src_operand src0; + + if (!IS_GENp(6)) { + fprintf(stderr, "error: the syntax of send instruction\n"); + YYERROR; + } + + if ($7.reg_file != BRW_ARCHITECTURE_REGISTER_FILE || + ($7.reg_nr & 0xF0) != BRW_ARF_ADDRESS || + ($7.reg_nr & 0x0F) != 0 || + $7.subreg_nr != 0) { + fprintf (stderr, "%d: scalar register must be a0.0<0;1,0>:ud\n", yylineno); + YYERROR; + } + + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.sfid_destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ + set_instruction_predicate(&$$, &$1); + + if (set_instruction_dest(&$$, &$4) != 0) + YYERROR; + + memset(&src0, 0, sizeof(src0)); + src0.address_mode = BRW_ADDRESS_DIRECT; + + if (IS_GENp(7)) { + src0.reg_file = BRW_GENERAL_REGISTER_FILE; + src0.reg_type = BRW_REGISTER_TYPE_UB; + } else { + src0.reg_file = BRW_MESSAGE_REGISTER_FILE; + src0.reg_type = BRW_REGISTER_TYPE_D; + } + + src0.reg_nr = $5.reg_nr; + src0.subreg_nr = 0; + set_instruction_src0(&$$, &src0); + + set_instruction_src1(&$$, &$7); + $$.bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); + } + | predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions + { + if ($8.reg_type != BRW_REGISTER_TYPE_UD && + $8.reg_type != BRW_REGISTER_TYPE_D && + $8.reg_type != BRW_REGISTER_TYPE_V) { + fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $8.imm32, $8.reg_type); + YYERROR; + } + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ + + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$4) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$6) != 0) + YYERROR; + $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; + $$.bits1.da1.src1_reg_type = $8.reg_type; + if (IS_GENx(5)) { + $$.bits2.send_gen5.sfid = ($7 & EX_DESC_SFID_MASK); + $$.bits3.ud = $8.imm32; + $$.bits3.generic_gen5.end_of_thread = !!($7 & EX_DESC_EOT_MASK); + } + else + $$.bits3.ud = $8.imm32; + } + | predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions + { + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ + + set_instruction_predicate(&$$, &$1); + + if (set_instruction_dest(&$$, &$4) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$6) != 0) + YYERROR; + /* XXX is this correct? */ + if (set_instruction_src1(&$$, &$8) != 0) + YYERROR; + if (IS_GENx(5)) { + $$.bits2.send_gen5.sfid = $7; + } + } + +; + +sndopr: exp %prec SNDOPR + { + $$ = $1; + } +; + +jumpinstruction: predicate JMPI execsize relativelocation2 + { + /* The jump instruction requires that the IP register + * be the destination and first source operand, while the + * offset is the second source operand. The next instruction + * is the post-incremented IP plus the offset. + */ + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.execution_size = ffs(1) - 1; + if(advanced_flag) + $$.header.mask_control = BRW_MASK_DISABLE; + set_instruction_predicate(&$$, &$1); + set_instruction_dest(&$$, &ip_dst); + set_instruction_src0(&$$, &ip_src); + set_instruction_src1(&$$, &$4); + $$.first_reloc_target = $4.reloc_target; + $$.first_reloc_offset = $4.imm32; + } +; + +mathinstruction: predicate MATH_INST execsize dst src srcimm math_function instoptions + { + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.sfid_destreg__conditionalmod = $7; + $$.header.execution_size = $3; + set_instruction_options(&$$, &$8); + set_instruction_predicate(&$$, &$1); + if (set_instruction_dest(&$$, &$4) != 0) + YYERROR; + if (set_instruction_src0(&$$, &$5) != 0) + YYERROR; + if (set_instruction_src1(&$$, &$6) != 0) + YYERROR; + } +; + +breakinstruction: predicate breakop execsize relativelocation relativelocation instoptions + { + // for Gen6, Gen7 + memset(&$$, 0, sizeof($$)); + set_instruction_predicate(&$$, &$1); + $$.header.opcode = $2; + $$.header.execution_size = $3; + $$.first_reloc_target = $4.reloc_target; + $$.first_reloc_offset = $4.imm32; + $$.second_reloc_target = $5.reloc_target; + $$.second_reloc_offset = $5.imm32; + } +; + +breakop: BREAK | CONT +; + +/* +maskpushop: MSAVE | PUSH +; + */ + +syncinstruction: predicate WAIT notifyreg + { + struct dst_operand notify_dst; + struct src_operand notify_src; + + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $2; + $$.header.execution_size = ffs(1) - 1; + set_direct_dst_operand(¬ify_dst, &$3, BRW_REGISTER_TYPE_D); + set_instruction_dest(&$$, ¬ify_dst); + set_direct_src_operand(¬ify_src, &$3, BRW_REGISTER_TYPE_D); + set_instruction_src0(&$$, ¬ify_src); + set_instruction_src1(&$$, &src_null_reg); + } + +; + +nopinstruction: NOP + { + memset(&$$, 0, sizeof($$)); + $$.header.opcode = $1; + }; + +/* XXX! */ +payload: directsrcoperand +; + +post_dst: dst +; + +msgtarget: NULL_TOKEN + { + if (IS_GENp(5)) { + $$.bits2.send_gen5.sfid= BRW_MESSAGE_TARGET_NULL; + $$.bits3.generic_gen5.header_present = 0; /* ??? */ + } else { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_NULL; + } + } + | SAMPLER LPAREN INTEGER COMMA INTEGER COMMA + sampler_datatype RPAREN + { + if (IS_GENp(7)) { + $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_SAMPLER; + $$.bits3.generic_gen5.header_present = 1; /* ??? */ + $$.bits3.sampler_gen7.binding_table_index = $3; + $$.bits3.sampler_gen7.sampler = $5; + $$.bits3.sampler_gen7.simd_mode = 2; /* SIMD16, maybe we should add a new parameter */ + } else if (IS_GENp(5)) { + $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_SAMPLER; + $$.bits3.generic_gen5.header_present = 1; /* ??? */ + $$.bits3.sampler_gen5.binding_table_index = $3; + $$.bits3.sampler_gen5.sampler = $5; + $$.bits3.sampler_gen5.simd_mode = 2; /* SIMD16, maybe we should add a new parameter */ + } else { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_SAMPLER; + $$.bits3.sampler.binding_table_index = $3; + $$.bits3.sampler.sampler = $5; + switch ($7) { + case TYPE_F: + $$.bits3.sampler.return_format = + BRW_SAMPLER_RETURN_FORMAT_FLOAT32; + break; + case TYPE_UD: + $$.bits3.sampler.return_format = + BRW_SAMPLER_RETURN_FORMAT_UINT32; + break; + case TYPE_D: + $$.bits3.sampler.return_format = + BRW_SAMPLER_RETURN_FORMAT_SINT32; + break; + } + } + } + | MATH math_function saturate math_signed math_scalar + { + if (IS_GENp(6)) { + fprintf (stderr, "Gen6+ doesn't have math function\n"); + YYERROR; + } else if (IS_GENx(5)) { + $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_MATH; + $$.bits3.generic_gen5.header_present = 0; + $$.bits3.math_gen5.function = $2; + if ($3 == BRW_INSTRUCTION_SATURATE) + $$.bits3.math_gen5.saturate = 1; + else + $$.bits3.math_gen5.saturate = 0; + $$.bits3.math_gen5.int_type = $4; + $$.bits3.math_gen5.precision = BRW_MATH_PRECISION_FULL; + $$.bits3.math_gen5.data_type = $5; + } else { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_MATH; + $$.bits3.math.function = $2; + if ($3 == BRW_INSTRUCTION_SATURATE) + $$.bits3.math.saturate = 1; + else + $$.bits3.math.saturate = 0; + $$.bits3.math.int_type = $4; + $$.bits3.math.precision = BRW_MATH_PRECISION_FULL; + $$.bits3.math.data_type = $5; + } + } + | GATEWAY + { + if (IS_GENp(5)) { + $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_GATEWAY; + $$.bits3.generic_gen5.header_present = 0; /* ??? */ + } else { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_GATEWAY; + } + } + | READ LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA + INTEGER RPAREN + { + if (IS_GENx(7)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_DP_SC; + $$.bits3.generic_gen5.header_present = 1; + $$.bits3.dp_gen7.binding_table_index = $3; + $$.bits3.dp_gen7.msg_control = $7; + $$.bits3.dp_gen7.msg_type = $9; + } else if (IS_GENx(6)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_DP_SC; + $$.bits3.generic_gen5.header_present = 1; + $$.bits3.dp_read_gen6.binding_table_index = $3; + $$.bits3.dp_read_gen6.msg_control = $7; + $$.bits3.dp_read_gen6.msg_type = $9; + } else if (IS_GENx(5)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_DATAPORT_READ; + $$.bits3.generic_gen5.header_present = 1; + $$.bits3.dp_read_gen5.binding_table_index = $3; + $$.bits3.dp_read_gen5.target_cache = $5; + $$.bits3.dp_read_gen5.msg_control = $7; + $$.bits3.dp_read_gen5.msg_type = $9; + } else { + $$.bits3.generic.msg_target = + BRW_MESSAGE_TARGET_DATAPORT_READ; + $$.bits3.dp_read.binding_table_index = $3; + $$.bits3.dp_read.target_cache = $5; + $$.bits3.dp_read.msg_control = $7; + $$.bits3.dp_read.msg_type = $9; + } + } + | WRITE LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA + INTEGER RPAREN + { + if (IS_GENx(7)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_DP_RC; + $$.bits3.generic_gen5.header_present = 1; + $$.bits3.dp_gen7.binding_table_index = $3; + $$.bits3.dp_gen7.msg_control = $5; + $$.bits3.dp_gen7.msg_type = $7; + } else if (IS_GENx(6)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_DP_RC; + /* Sandybridge supports headerlesss message for render target write. + * Currently the GFX assembler doesn't support it. so the program must provide + * message header + */ + $$.bits3.generic_gen5.header_present = 1; + $$.bits3.dp_write_gen6.binding_table_index = $3; + $$.bits3.dp_write_gen6.msg_control = $5; + $$.bits3.dp_write_gen6.msg_type = $7; + $$.bits3.dp_write_gen6.send_commit_msg = $9; + } else if (IS_GENx(5)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_DATAPORT_WRITE; + $$.bits3.generic_gen5.header_present = 1; + $$.bits3.dp_write_gen5.binding_table_index = $3; + $$.bits3.dp_write_gen5.pixel_scoreboard_clear = ($5 & 0x8) >> 3; + $$.bits3.dp_write_gen5.msg_control = $5 & 0x7; + $$.bits3.dp_write_gen5.msg_type = $7; + $$.bits3.dp_write_gen5.send_commit_msg = $9; + } else { + $$.bits3.generic.msg_target = + BRW_MESSAGE_TARGET_DATAPORT_WRITE; + $$.bits3.dp_write.binding_table_index = $3; + /* The msg control field of brw_struct.h is split into + * msg control and pixel_scoreboard_clear, even though + * pixel_scoreboard_clear isn't common to all write messages. + */ + $$.bits3.dp_write.pixel_scoreboard_clear = ($5 & 0x8) >> 3; + $$.bits3.dp_write.msg_control = $5 & 0x7; + $$.bits3.dp_write.msg_type = $7; + $$.bits3.dp_write.send_commit_msg = $9; + } + } + | WRITE LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA + INTEGER COMMA INTEGER RPAREN + { + if (IS_GENx(7)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_DP_RC; + $$.bits3.generic_gen5.header_present = ($11 != 0); + $$.bits3.dp_gen7.binding_table_index = $3; + $$.bits3.dp_gen7.msg_control = $5; + $$.bits3.dp_gen7.msg_type = $7; + } else if (IS_GENx(6)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_DP_RC; + $$.bits3.generic_gen5.header_present = ($11 != 0); + $$.bits3.dp_write_gen6.binding_table_index = $3; + $$.bits3.dp_write_gen6.msg_control = $5; + $$.bits3.dp_write_gen6.msg_type = $7; + $$.bits3.dp_write_gen6.send_commit_msg = $9; + } else if (IS_GENx(5)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_DATAPORT_WRITE; + $$.bits3.generic_gen5.header_present = ($11 != 0); + $$.bits3.dp_write_gen5.binding_table_index = $3; + $$.bits3.dp_write_gen5.pixel_scoreboard_clear = ($5 & 0x8) >> 3; + $$.bits3.dp_write_gen5.msg_control = $5 & 0x7; + $$.bits3.dp_write_gen5.msg_type = $7; + $$.bits3.dp_write_gen5.send_commit_msg = $9; + } else { + $$.bits3.generic.msg_target = + BRW_MESSAGE_TARGET_DATAPORT_WRITE; + $$.bits3.dp_write.binding_table_index = $3; + /* The msg control field of brw_struct.h is split into + * msg control and pixel_scoreboard_clear, even though + * pixel_scoreboard_clear isn't common to all write messages. + */ + $$.bits3.dp_write.pixel_scoreboard_clear = ($5 & 0x8) >> 3; + $$.bits3.dp_write.msg_control = $5 & 0x7; + $$.bits3.dp_write.msg_type = $7; + $$.bits3.dp_write.send_commit_msg = $9; + } + } + | URB INTEGER urb_swizzle urb_allocate urb_used urb_complete + { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_URB; + if (IS_GENp(5)) { + $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB; + $$.bits3.generic_gen5.header_present = 1; + $$.bits3.urb_gen5.opcode = BRW_URB_OPCODE_WRITE; + $$.bits3.urb_gen5.offset = $2; + $$.bits3.urb_gen5.swizzle_control = $3; + $$.bits3.urb_gen5.pad = 0; + $$.bits3.urb_gen5.allocate = $4; + $$.bits3.urb_gen5.used = $5; + $$.bits3.urb_gen5.complete = $6; + } else { + $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_URB; + $$.bits3.urb.opcode = BRW_URB_OPCODE_WRITE; + $$.bits3.urb.offset = $2; + $$.bits3.urb.swizzle_control = $3; + $$.bits3.urb.pad = 0; + $$.bits3.urb.allocate = $4; + $$.bits3.urb.used = $5; + $$.bits3.urb.complete = $6; + } + } + | THREAD_SPAWNER LPAREN INTEGER COMMA INTEGER COMMA + INTEGER RPAREN + { + $$.bits3.generic.msg_target = + BRW_MESSAGE_TARGET_THREAD_SPAWNER; + if (IS_GENp(5)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_THREAD_SPAWNER; + $$.bits3.generic_gen5.header_present = 0; + $$.bits3.thread_spawner_gen5.opcode = $3; + $$.bits3.thread_spawner_gen5.requester_type = $5; + $$.bits3.thread_spawner_gen5.resource_select = $7; + } else { + $$.bits3.generic.msg_target = + BRW_MESSAGE_TARGET_THREAD_SPAWNER; + $$.bits3.thread_spawner.opcode = $3; + $$.bits3.thread_spawner.requester_type = $5; + $$.bits3.thread_spawner.resource_select = $7; + } + } + | VME LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA INTEGER RPAREN + { + $$.bits3.generic.msg_target = + BRW_MESSAGE_TARGET_VME; + + if (IS_GENp(6)) { + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_VME; + $$.bits3.vme_gen6.binding_table_index = $3; + $$.bits3.vme_gen6.search_path_index = $5; + $$.bits3.vme_gen6.lut_subindex = $7; + $$.bits3.vme_gen6.message_type = $9; + $$.bits3.generic_gen5.header_present = 1; + } else { + fprintf (stderr, "Gen6- doesn't have vme function\n"); + YYERROR; + } + } + | CRE LPAREN INTEGER COMMA INTEGER RPAREN + { + if (gen_level < 75) { + fprintf (stderr, "Below Gen7.5 doesn't have CRE function\n"); + YYERROR; + } + $$.bits3.generic.msg_target = + BRW_MESSAGE_TARGET_CRE; + + $$.bits2.send_gen5.sfid = + BRW_MESSAGE_TARGET_CRE; + $$.bits3.cre_gen75.binding_table_index = $3; + $$.bits3.cre_gen75.message_type = $5; + $$.bits3.generic_gen5.header_present = 1; + } + + | DATA_PORT LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA + INTEGER COMMA INTEGER COMMA INTEGER RPAREN + { + $$.bits2.send_gen5.sfid = $3; + $$.bits3.generic_gen5.header_present = ($13 != 0); + + if (IS_GENp(7)) { + if ($3 != BRW_MESSAGE_TARGET_DP_SC && + $3 != BRW_MESSAGE_TARGET_DP_RC && + $3 != BRW_MESSAGE_TARGET_DP_CC && + $3 != BRW_MESSAGE_TARGET_DP_DC) { + fprintf (stderr, "error: wrong cache type\n"); + YYERROR; + } + + $$.bits3.dp_gen7.category = $11; + $$.bits3.dp_gen7.binding_table_index = $9; + $$.bits3.dp_gen7.msg_control = $7; + $$.bits3.dp_gen7.msg_type = $5; + } else if (IS_GENx(6)) { + if ($3 != BRW_MESSAGE_TARGET_DP_SC && + $3 != BRW_MESSAGE_TARGET_DP_RC && + $3 != BRW_MESSAGE_TARGET_DP_CC) { + fprintf (stderr, "error: wrong cache type\n"); + YYERROR; + } + + $$.bits3.dp_gen6.send_commit_msg = $11; + $$.bits3.dp_gen6.binding_table_index = $9; + $$.bits3.dp_gen6.msg_control = $7; + $$.bits3.dp_gen6.msg_type = $5; + } else if (!IS_GENp(5)) { + fprintf (stderr, "Gen6- doesn't support data port for sampler/render/constant/data cache\n"); + YYERROR; + } + } +; + +urb_allocate: ALLOCATE { $$ = 1; } + | /* empty */ { $$ = 0; } +; + +urb_used: USED { $$ = 1; } + | /* empty */ { $$ = 0; } +; + +urb_complete: COMPLETE { $$ = 1; } + | /* empty */ { $$ = 0; } +; + +urb_swizzle: TRANSPOSE { $$ = BRW_URB_SWIZZLE_TRANSPOSE; } + | INTERLEAVE { $$ = BRW_URB_SWIZZLE_INTERLEAVE; } + | /* empty */ { $$ = BRW_URB_SWIZZLE_NONE; } +; + +sampler_datatype: + TYPE_F + | TYPE_UD + | TYPE_D +; + +math_function: INV | LOG | EXP | SQRT | POW | SIN | COS | SINCOS | INTDIV + | INTMOD | INTDIVMOD +; + +math_signed: /* empty */ { $$ = 0; } + | SIGNED { $$ = 1; } +; + +math_scalar: /* empty */ { $$ = 0; } + | SCALAR { $$ = 1; } +; + +/* 1.4.2: Destination register */ + +dst: dstoperand | dstoperandex +; + +dstoperand: symbol_reg dstregion + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = $1.base.reg_file; + $$.reg_nr = $1.base.reg_nr; + $$.subreg_nr = $1.base.subreg_nr; + if ($2 == DEFAULT_DSTREGION) { + $$.horiz_stride = $1.dst_region; + } else { + $$.horiz_stride = $2; + } + $$.reg_type = $1.type; + } + | dstreg dstregion writemask regtype + { + /* Returns an instruction with just the destination register + * filled in. + */ + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.address_mode = $1.address_mode; + $$.address_subreg_nr = $1.address_subreg_nr; + $$.indirect_offset = $1.indirect_offset; + $$.horiz_stride = $2; + $$.writemask_set = $3.writemask_set; + $$.writemask = $3.writemask; + $$.reg_type = $4.type; + } +; + +/* The dstoperandex returns an instruction with just the destination register + * filled in. + */ +dstoperandex: dstoperandex_typed dstregion regtype + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = $2; + $$.reg_type = $3.type; + } + | maskstackreg + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = 1; + $$.reg_type = BRW_REGISTER_TYPE_UW; + } + | controlreg + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = 1; + $$.reg_type = BRW_REGISTER_TYPE_UD; + } + | ipreg + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = 1; + $$.reg_type = BRW_REGISTER_TYPE_UD; + } + | nullreg dstregion regtype + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.horiz_stride = $2; + $$.reg_type = $3.type; + } +; + +dstoperandex_typed: accreg | flagreg | addrreg | maskreg +; + +symbol_reg: STRING %prec STR_SYMBOL_REG + { + struct declared_register *dcl_reg = find_register($1); + + if (dcl_reg == NULL) { + fprintf(stderr, "can't find register %s\n", $1); + YYERROR; + } + + memcpy(&$$, dcl_reg, sizeof(*dcl_reg)); + free($1); // $1 has been malloc'ed by strdup + } + | symbol_reg_p + { + $$=$1; + } +; + +symbol_reg_p: STRING LPAREN exp RPAREN + { + struct declared_register *dcl_reg = find_register($1); + + if (dcl_reg == NULL) { + fprintf(stderr, "can't find register %s\n", $1); + YYERROR; + } + + memcpy(&$$, dcl_reg, sizeof(*dcl_reg)); + $$.base.reg_nr += $3; + free($1); + } + | STRING LPAREN exp COMMA exp RPAREN + { + struct declared_register *dcl_reg = find_register($1); + + if (dcl_reg == NULL) { + fprintf(stderr, "can't find register %s\n", $1); + YYERROR; + } + + memcpy(&$$, dcl_reg, sizeof(*dcl_reg)); + $$.base.reg_nr += $3; + $$.base.subreg_nr += $5; + if(advanced_flag) { + $$.base.reg_nr += $$.base.subreg_nr / (32 / get_type_size(dcl_reg->type)); + $$.base.subreg_nr = $$.base.subreg_nr % (32 / get_type_size(dcl_reg->type)); + } else { + $$.base.reg_nr += $$.base.subreg_nr / 32; + $$.base.subreg_nr = $$.base.subreg_nr % 32; + } + free($1); + } +; +/* Returns a partially complete destination register consisting of the + * direct or indirect register addressing fields, but not stride or writemask. + */ +dstreg: directgenreg + { + memset (&$$, '\0', sizeof ($$)); + $$.address_mode = BRW_ADDRESS_DIRECT; + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + } + | directmsgreg + { + memset (&$$, '\0', sizeof ($$)); + $$.address_mode = BRW_ADDRESS_DIRECT; + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + } + | indirectgenreg + { + memset (&$$, '\0', sizeof ($$)); + $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + $$.reg_file = $1.reg_file; + $$.address_subreg_nr = $1.address_subreg_nr; + $$.indirect_offset = $1.indirect_offset; + } + | indirectmsgreg + { + memset (&$$, '\0', sizeof ($$)); + $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + $$.reg_file = $1.reg_file; + $$.address_subreg_nr = $1.address_subreg_nr; + $$.indirect_offset = $1.indirect_offset; + } +; + +/* 1.4.3: Source register */ +srcaccimm: srcacc | imm32reg +; + +srcacc: directsrcaccoperand | indirectsrcoperand +; + +srcimm: directsrcoperand | indirectsrcoperand| imm32reg +; + +imm32reg: imm32 srcimmtype + { + union { + int i; + float f; + } intfloat; + uint32_t d; + + switch ($2) { + case BRW_REGISTER_TYPE_UD: + case BRW_REGISTER_TYPE_D: + case BRW_REGISTER_TYPE_V: + case BRW_REGISTER_TYPE_VF: + switch ($1.r) { + case imm32_d: + d = $1.u.d; + break; + default: + fprintf (stderr, "%d: non-int D/UD/V/VF representation: %d,type=%d\n", yylineno, $1.r, $2); + YYERROR; + } + break; + case BRW_REGISTER_TYPE_UW: + case BRW_REGISTER_TYPE_W: + switch ($1.r) { + case imm32_d: + d = $1.u.d; + break; + default: + fprintf (stderr, "non-int W/UW representation\n"); + YYERROR; + } + d &= 0xffff; + d |= d << 16; + break; + case BRW_REGISTER_TYPE_F: + switch ($1.r) { + case imm32_f: + intfloat.f = $1.u.f; + break; + case imm32_d: + intfloat.f = (float) $1.u.d; + break; + default: + fprintf (stderr, "non-float F representation\n"); + YYERROR; + } + d = intfloat.i; + break; +#if 0 + case BRW_REGISTER_TYPE_VF: + fprintf (stderr, "Immediate type VF not supported yet\n"); + YYERROR; +#endif + default: + fprintf(stderr, "unknown immediate type %d\n", $2); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_IMMEDIATE_VALUE; + $$.reg_type = $2; + $$.imm32 = d; + } +; + +directsrcaccoperand: directsrcoperand + | accreg region regtype + { + set_direct_src_operand(&$$, &$1, $3.type); + $$.vert_stride = $2.vert_stride; + $$.width = $2.width; + $$.horiz_stride = $2.horiz_stride; + $$.default_region = $2.is_default; + } +; + +/* Returns a source operand in the src0 fields of an instruction. */ +srcarchoperandex: srcarchoperandex_typed region regtype + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = $1.reg_file; + $$.reg_type = $3.type; + $$.subreg_nr = $1.subreg_nr; + $$.reg_nr = $1.reg_nr; + $$.vert_stride = $2.vert_stride; + $$.width = $2.width; + $$.horiz_stride = $2.horiz_stride; + $$.default_region = $2.is_default; + $$.negate = 0; + $$.abs = 0; + } + | maskstackreg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UB); + } + | controlreg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + } +/* | statereg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + }*/ + | notifyreg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + } + | ipreg + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + } + | nullreg region regtype + { + if ($3.is_default) { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + } else { + set_direct_src_operand(&$$, &$1, $3.type); + } + $$.default_region = 1; + } +; + +srcarchoperandex_typed: flagreg | addrreg | maskreg +; + +sendleadreg: symbol_reg + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = $1.base.reg_file; + $$.reg_nr = $1.base.reg_nr; + $$.subreg_nr = $1.base.subreg_nr; + } + | directgenreg | directmsgreg +; + +src: directsrcoperand | indirectsrcoperand +; + +directsrcoperand: negate abs symbol_reg region regtype + { + memset (&$$, '\0', sizeof ($$)); + $$.address_mode = BRW_ADDRESS_DIRECT; + $$.reg_file = $3.base.reg_file; + $$.reg_nr = $3.base.reg_nr; + $$.subreg_nr = $3.base.subreg_nr; + if ($5.is_default) { + $$.reg_type = $3.type; + } else { + $$.reg_type = $5.type; + } + if ($4.is_default) { + $$.vert_stride = $3.src_region.vert_stride; + $$.width = $3.src_region.width; + $$.horiz_stride = $3.src_region.horiz_stride; + } else { + $$.vert_stride = $4.vert_stride; + $$.width = $4.width; + $$.horiz_stride = $4.horiz_stride; + } + $$.negate = $1; + $$.abs = $2; + } + | statereg region regtype + { + if($2.is_default ==1 && $3.is_default == 1) + { + set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); + } + else{ + memset (&$$, '\0', sizeof ($$)); + $$.address_mode = BRW_ADDRESS_DIRECT; + $$.reg_file = $1.reg_file; + $$.reg_nr = $1.reg_nr; + $$.subreg_nr = $1.subreg_nr; + $$.vert_stride = $2.vert_stride; + $$.width = $2.width; + $$.horiz_stride = $2.horiz_stride; + $$.reg_type = $3.type; + } + } + | negate abs directgenreg region regtype swizzle + { + memset (&$$, '\0', sizeof ($$)); + $$.address_mode = BRW_ADDRESS_DIRECT; + $$.reg_file = $3.reg_file; + $$.reg_nr = $3.reg_nr; + $$.subreg_nr = $3.subreg_nr; + $$.reg_type = $5.type; + $$.vert_stride = $4.vert_stride; + $$.width = $4.width; + $$.horiz_stride = $4.horiz_stride; + $$.default_region = $4.is_default; + $$.negate = $1; + $$.abs = $2; + $$.swizzle_set = $6.swizzle_set; + $$.swizzle_x = $6.swizzle_x; + $$.swizzle_y = $6.swizzle_y; + $$.swizzle_z = $6.swizzle_z; + $$.swizzle_w = $6.swizzle_w; + } + | srcarchoperandex +; + +indirectsrcoperand: + negate abs indirectgenreg indirectregion regtype swizzle + { + memset (&$$, '\0', sizeof ($$)); + $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + $$.reg_file = $3.reg_file; + $$.address_subreg_nr = $3.address_subreg_nr; + $$.indirect_offset = $3.indirect_offset; + $$.reg_type = $5.type; + $$.vert_stride = $4.vert_stride; + $$.width = $4.width; + $$.horiz_stride = $4.horiz_stride; + $$.negate = $1; + $$.abs = $2; + $$.swizzle_set = $6.swizzle_set; + $$.swizzle_x = $6.swizzle_x; + $$.swizzle_y = $6.swizzle_y; + $$.swizzle_z = $6.swizzle_z; + $$.swizzle_w = $6.swizzle_w; + } +; + +/* 1.4.4: Address Registers */ +/* Returns a partially-completed indirect_reg consisting of the address + * register fields for register-indirect access. + */ +addrparam: addrreg COMMA immaddroffset + { + if ($3 < -512 || $3 > 511) { + fprintf(stderr, "Address immediate offset %d out of" + "range %d\n", $3, yylineno); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.address_subreg_nr = $1.subreg_nr; + $$.indirect_offset = $3; + } + | addrreg + { + memset (&$$, '\0', sizeof ($$)); + $$.address_subreg_nr = $1.subreg_nr; + $$.indirect_offset = 0; + } +; + +/* The immaddroffset provides an immediate offset value added to the addresses + * from the address register in register-indirect register access. + */ +immaddroffset: /* empty */ { $$ = 0; } + | exp +; + + +/* 1.4.5: Register files and register numbers */ +subregnum: DOT exp + { + $$ = $2; + } + | %prec SUBREGNUM + { + /* Default to subreg 0 if unspecified. */ + $$ = 0; + } +; + +directgenreg: GENREG subregnum + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_GENERAL_REGISTER_FILE; + $$.reg_nr = $1; + $$.subreg_nr = $2; + } +; + +indirectgenreg: GENREGFILE LSQUARE addrparam RSQUARE + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_GENERAL_REGISTER_FILE; + $$.address_subreg_nr = $3.address_subreg_nr; + $$.indirect_offset = $3.indirect_offset; + } +; + +directmsgreg: MSGREG subregnum + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_MESSAGE_REGISTER_FILE; + $$.reg_nr = $1; + $$.subreg_nr = $2; + } +; + +indirectmsgreg: MSGREGFILE LSQUARE addrparam RSQUARE + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_MESSAGE_REGISTER_FILE; + $$.address_subreg_nr = $3.address_subreg_nr; + $$.indirect_offset = $3.indirect_offset; + } +; + +addrreg: ADDRESSREG subregnum + { + if ($1 != 0) { + fprintf(stderr, + "address register number %d out of range", $1); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_ADDRESS | $1; + $$.subreg_nr = $2; + } +; + +accreg: ACCREG subregnum + { + if ($1 > 1) { + fprintf(stderr, + "accumulator register number %d out of range", $1); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_ACCUMULATOR | $1; + $$.subreg_nr = $2; + } +; + +flagreg: FLAGREG subregnum + { + if ((!IS_GENp(7) && $1) > 0 || + (IS_GENp(7) && $1 > 1)) { + fprintf(stderr, + "flag register number %d out of range\n", $1); + YYERROR; + } + + if ($2 > 1) { + fprintf(stderr, + "flag subregister number %d out of range\n", $1); + YYERROR; + } + + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_FLAG | $1; + $$.subreg_nr = $2; + } +; + +maskreg: MASKREG subregnum + { + if ($1 > 0) { + fprintf(stderr, + "mask register number %d out of range", $1); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK; + $$.subreg_nr = $2; + } + | mask_subreg + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK; + $$.subreg_nr = $1; + } +; + +mask_subreg: AMASK | IMASK | LMASK | CMASK +; + +maskstackreg: MASKSTACKREG subregnum + { + if ($1 > 0) { + fprintf(stderr, + "mask stack register number %d out of range", $1); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK_STACK; + $$.subreg_nr = $2; + } + | maskstack_subreg + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK_STACK; + $$.subreg_nr = $1; + } +; + +maskstack_subreg: IMS | LMS +; + +/* +maskstackdepthreg: MASKSTACKDEPTHREG subregnum + { + if ($1 > 0) { + fprintf(stderr, + "mask stack register number %d out of range", $1); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK_STACK_DEPTH; + $$.subreg_nr = $2; + } + | maskstackdepth_subreg + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_MASK_STACK_DEPTH; + $$.subreg_nr = $1; + } +; + +maskstackdepth_subreg: IMSD | LMSD +; + */ + +notifyreg: NOTIFYREG regtype + { + int num_notifyreg = (IS_GENp(6)) ? 3 : 2; + + if ($1 > num_notifyreg) { + fprintf(stderr, + "notification register number %d out of range", + $1); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + + if (IS_GENp(6)) { + $$.reg_nr = BRW_ARF_NOTIFICATION_COUNT; + $$.subreg_nr = $1; + } else { + $$.reg_nr = BRW_ARF_NOTIFICATION_COUNT | $1; + $$.subreg_nr = 0; + } + } +/* + | NOTIFYREG regtype + { + if ($1 > 1) { + fprintf(stderr, + "notification register number %d out of range", + $1); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_NOTIFICATION_COUNT; + $$.subreg_nr = 0; + } +*/ +; + +statereg: STATEREG subregnum + { + if ($1 > 0) { + fprintf(stderr, + "state register number %d out of range", $1); + YYERROR; + } + if ($2 > 1) { + fprintf(stderr, + "state subregister number %d out of range", $1); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_STATE | $1; + $$.subreg_nr = $2; + } +; + +controlreg: CONTROLREG subregnum + { + if ($1 > 0) { + fprintf(stderr, + "control register number %d out of range", $1); + YYERROR; + } + if ($2 > 2) { + fprintf(stderr, + "control subregister number %d out of range", $1); + YYERROR; + } + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_CONTROL | $1; + $$.subreg_nr = $2; + } +; + +ipreg: IPREG regtype + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_IP; + $$.subreg_nr = 0; + } +; + +nullreg: NULL_TOKEN + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; + $$.reg_nr = BRW_ARF_NULL; + $$.subreg_nr = 0; + } +; + +/* 1.4.6: Relative locations */ +relativelocation: + simple_int + { + if (($1 > 32767) || ($1 < -32768)) { + fprintf(stderr, + "error: relative offset %d out of range \n", + $1); + YYERROR; + } + + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_IMMEDIATE_VALUE; + $$.reg_type = BRW_REGISTER_TYPE_D; + $$.imm32 = $1 & 0x0000ffff; + } + | STRING + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_IMMEDIATE_VALUE; + $$.reg_type = BRW_REGISTER_TYPE_D; + $$.reloc_target = $1; + } +; + +relativelocation2: + STRING + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_IMMEDIATE_VALUE; + $$.reg_type = BRW_REGISTER_TYPE_D; + $$.reloc_target = $1; + } + | exp + { + memset (&$$, '\0', sizeof ($$)); + $$.reg_file = BRW_IMMEDIATE_VALUE; + $$.reg_type = BRW_REGISTER_TYPE_D; + $$.imm32 = $1; + } + | directgenreg region regtype + { + set_direct_src_operand(&$$, &$1, $3.type); + $$.vert_stride = $2.vert_stride; + $$.width = $2.width; + $$.horiz_stride = $2.horiz_stride; + $$.default_region = $2.is_default; + } + | symbol_reg_p + { + memset (&$$, '\0', sizeof ($$)); + $$.address_mode = BRW_ADDRESS_DIRECT; + $$.reg_file = $1.base.reg_file; + $$.reg_nr = $1.base.reg_nr; + $$.subreg_nr = $1.base.subreg_nr; + $$.reg_type = $1.type; + $$.vert_stride = $1.src_region.vert_stride; + $$.width = $1.src_region.width; + $$.horiz_stride = $1.src_region.horiz_stride; + } + | indirectgenreg indirectregion regtype + { + memset (&$$, '\0', sizeof ($$)); + $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; + $$.reg_file = $1.reg_file; + $$.address_subreg_nr = $1.address_subreg_nr; + $$.indirect_offset = $1.indirect_offset; + $$.reg_type = $3.type; + $$.vert_stride = $2.vert_stride; + $$.width = $2.width; + $$.horiz_stride = $2.horiz_stride; + } +; + +/* 1.4.7: Regions */ +dstregion: /* empty */ + { + $$ = DEFAULT_DSTREGION; + } + |LANGLE exp RANGLE + { + /* Returns a value for a horiz_stride field of an + * instruction. + */ + if ($2 != 1 && $2 != 2 && $2 != 4) { + fprintf(stderr, "Invalid horiz size %d\n", $2); + } + $$ = ffs($2); + } +; + +region: /* empty */ + { + /* XXX is this default value correct?*/ + memset (&$$, '\0', sizeof ($$)); + $$.vert_stride = ffs(0); + $$.width = ffs(1) - 1; + $$.horiz_stride = ffs(0); + $$.is_default = 1; + } + |LANGLE exp RANGLE + { + /* XXX is this default value correct for accreg?*/ + memset (&$$, '\0', sizeof ($$)); + $$.vert_stride = ffs($2); + $$.width = ffs(1) - 1; + $$.horiz_stride = ffs(0); + } + |LANGLE exp COMMA exp COMMA exp RANGLE + { + memset (&$$, '\0', sizeof ($$)); + $$.vert_stride = ffs($2); + $$.width = ffs($4) - 1; + $$.horiz_stride = ffs($6); + } + | LANGLE exp SEMICOLON exp COMMA exp RANGLE + { + memset (&$$, '\0', sizeof ($$)); + $$.vert_stride = ffs($2); + $$.width = ffs($4) - 1; + $$.horiz_stride = ffs($6); + } + +; +/* region_wh is used in specifying indirect operands where rather than having + * a vertical stride, you use subsequent address registers to get a new base + * offset for the next row. + */ +region_wh: LANGLE exp COMMA exp RANGLE + { + memset (&$$, '\0', sizeof ($$)); + $$.vert_stride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL; + $$.width = ffs($2) - 1; + $$.horiz_stride = ffs($4); + } +; + +indirectregion: region | region_wh +; + +/* 1.4.8: Types */ + +/* regtype returns an integer register type suitable for inserting into an + * instruction. + */ +regtype: /* empty */ + { $$.type = program_defaults.register_type;$$.is_default = 1;} + | TYPE_F { $$.type = BRW_REGISTER_TYPE_F;$$.is_default = 0; } + | TYPE_UD { $$.type = BRW_REGISTER_TYPE_UD;$$.is_default = 0; } + | TYPE_D { $$.type = BRW_REGISTER_TYPE_D;$$.is_default = 0; } + | TYPE_UW { $$.type = BRW_REGISTER_TYPE_UW;$$.is_default = 0; } + | TYPE_W { $$.type = BRW_REGISTER_TYPE_W;$$.is_default = 0; } + | TYPE_UB { $$.type = BRW_REGISTER_TYPE_UB;$$.is_default = 0; } + | TYPE_B { $$.type = BRW_REGISTER_TYPE_B;$$.is_default = 0; } +; + +srcimmtype: /* empty */ + { + /* XXX change to default when pragma parse is done */ + $$ = BRW_REGISTER_TYPE_D; + } + |TYPE_F { $$ = BRW_REGISTER_TYPE_F; } + | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; } + | TYPE_D { $$ = BRW_REGISTER_TYPE_D; } + | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; } + | TYPE_W { $$ = BRW_REGISTER_TYPE_W; } + | TYPE_V { $$ = BRW_REGISTER_TYPE_V; } + | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; } +; + +/* 1.4.10: Swizzle control */ +/* Returns the swizzle control for an align16 instruction's source operand + * in the src0 fields. + */ +swizzle: /* empty */ + { + $$.swizzle_set = 0; + $$.swizzle_x = BRW_CHANNEL_X; + $$.swizzle_y = BRW_CHANNEL_Y; + $$.swizzle_z = BRW_CHANNEL_Z; + $$.swizzle_w = BRW_CHANNEL_W; + } + | DOT chansel + { + $$.swizzle_set = 1; + $$.swizzle_x = $2; + $$.swizzle_y = $2; + $$.swizzle_z = $2; + $$.swizzle_w = $2; + } + | DOT chansel chansel chansel chansel + { + $$.swizzle_set = 1; + $$.swizzle_x = $2; + $$.swizzle_y = $3; + $$.swizzle_z = $4; + $$.swizzle_w = $5; + } +; + +chansel: X | Y | Z | W +; + +/* 1.4.9: Write mask */ +/* Returns a partially completed dst_operand, with just the writemask bits + * filled out. + */ +writemask: /* empty */ + { + $$.writemask_set = 0; + $$.writemask = 0xf; + } + | DOT writemask_x writemask_y writemask_z writemask_w + { + $$.writemask_set = 1; + $$.writemask = $2 | $3 | $4 | $5; + } +; + +writemask_x: /* empty */ { $$ = 0; } + | X { $$ = 1 << BRW_CHANNEL_X; } +; + +writemask_y: /* empty */ { $$ = 0; } + | Y { $$ = 1 << BRW_CHANNEL_Y; } +; + +writemask_z: /* empty */ { $$ = 0; } + | Z { $$ = 1 << BRW_CHANNEL_Z; } +; + +writemask_w: /* empty */ { $$ = 0; } + | W { $$ = 1 << BRW_CHANNEL_W; } +; + +/* 1.4.11: Immediate values */ +imm32: exp { $$.r = imm32_d; $$.u.d = $1; } + | NUMBER { $$.r = imm32_f; $$.u.f = $1; } +; + +/* 1.4.12: Predication and modifiers */ +predicate: /* empty */ + { + $$.header.predicate_control = BRW_PREDICATE_NONE; + $$.bits2.da1.flag_reg_nr = 0; + $$.bits2.da1.flag_subreg_nr = 0; + $$.header.predicate_inverse = 0; + } + | LPAREN predstate flagreg predctrl RPAREN + { + $$.header.predicate_control = $4; + /* XXX: Should deal with erroring when the user tries to + * set a predicate for one flag register and conditional + * modification on the other flag register. + */ + $$.bits2.da1.flag_reg_nr = ($3.reg_nr & 0xF); + $$.bits2.da1.flag_subreg_nr = $3.subreg_nr; + $$.header.predicate_inverse = $2; + } +; + +predstate: /* empty */ { $$ = 0; } + | PLUS { $$ = 0; } + | MINUS { $$ = 1; } +; + +predctrl: /* empty */ { $$ = BRW_PREDICATE_NORMAL; } + | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; } + | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; } + | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; } + | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; } + | ANYV { $$ = BRW_PREDICATE_ALIGN1_ANYV; } + | ALLV { $$ = BRW_PREDICATE_ALIGN1_ALLV; } + | ANY2H { $$ = BRW_PREDICATE_ALIGN1_ANY2H; } + | ALL2H { $$ = BRW_PREDICATE_ALIGN1_ALL2H; } + | ANY4H { $$ = BRW_PREDICATE_ALIGN1_ANY4H; } + | ALL4H { $$ = BRW_PREDICATE_ALIGN1_ALL4H; } + | ANY8H { $$ = BRW_PREDICATE_ALIGN1_ANY8H; } + | ALL8H { $$ = BRW_PREDICATE_ALIGN1_ALL8H; } + | ANY16H { $$ = BRW_PREDICATE_ALIGN1_ANY16H; } + | ALL16H { $$ = BRW_PREDICATE_ALIGN1_ALL16H; } +; + +negate: /* empty */ { $$ = 0; } + | MINUS { $$ = 1; } +; + +abs: /* empty */ { $$ = 0; } + | ABS { $$ = 1; } +; + +execsize: /* empty */ %prec EMPTEXECSIZE + { + $$ = ffs(program_defaults.execute_size) - 1; + } + |LPAREN exp RPAREN + { + /* Returns a value for the execution_size field of an + * instruction. + */ + if ($2 != 1 && $2 != 2 && $2 != 4 && $2 != 8 && $2 != 16 && + $2 != 32) { + fprintf(stderr, "Invalid execution size %d\n", $2); + YYERROR; + } + $$ = ffs($2) - 1; + } +; + +saturate: /* empty */ { $$ = BRW_INSTRUCTION_NORMAL; } + | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; } +; +conditionalmodifier: condition + { + $$.cond = $1; + $$.flag_reg_nr = 0; + $$.flag_subreg_nr = -1; + } + | condition DOT flagreg + { + $$.cond = $1; + $$.flag_reg_nr = ($3.reg_nr & 0xF); + $$.flag_subreg_nr = $3.subreg_nr; + } + +condition: /* empty */ { $$ = BRW_CONDITIONAL_NONE; } + | ZERO + | EQUAL + | NOT_ZERO + | NOT_EQUAL + | GREATER + | GREATER_EQUAL + | LESS + | LESS_EQUAL + | ROUND_INCREMENT + | OVERFLOW + | UNORDERED +; + +/* 1.4.13: Instruction options */ +instoptions: /* empty */ + { memset(&$$, 0, sizeof($$)); } + | LCURLY instoption_list RCURLY + { $$ = $2; } +; + +instoption_list:instoption_list COMMA instoption + { + $$ = $1; + switch ($3) { + case ALIGN1: + $$.header.access_mode = BRW_ALIGN_1; + break; + case ALIGN16: + $$.header.access_mode = BRW_ALIGN_16; + break; + case SECHALF: + $$.header.compression_control |= BRW_COMPRESSION_2NDHALF; + break; + case COMPR: + if (!IS_GENp(6)) { + $$.header.compression_control |= + BRW_COMPRESSION_COMPRESSED; + } + break; + case SWITCH: + $$.header.thread_control |= BRW_THREAD_SWITCH; + break; + case ATOMIC: + $$.header.thread_control |= BRW_THREAD_ATOMIC; + break; + case NODDCHK: + $$.header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED; + break; + case NODDCLR: + $$.header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED; + break; + case MASK_DISABLE: + $$.header.mask_control = BRW_MASK_DISABLE; + break; + case BREAKPOINT: + $$.header.debug_control = BRW_DEBUG_BREAKPOINT; + break; + case ACCWRCTRL: + $$.header.acc_wr_control = BRW_ACCWRCTRL_ACCWRCTRL; + } + } + | instoption_list instoption + { + $$ = $1; + switch ($2) { + case ALIGN1: + $$.header.access_mode = BRW_ALIGN_1; + break; + case ALIGN16: + $$.header.access_mode = BRW_ALIGN_16; + break; + case SECHALF: + $$.header.compression_control |= BRW_COMPRESSION_2NDHALF; + break; + case COMPR: + if (!IS_GENp(6)) { + $$.header.compression_control |= + BRW_COMPRESSION_COMPRESSED; + } + break; + case SWITCH: + $$.header.thread_control |= BRW_THREAD_SWITCH; + break; + case ATOMIC: + $$.header.thread_control |= BRW_THREAD_ATOMIC; + break; + case NODDCHK: + $$.header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED; + break; + case NODDCLR: + $$.header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED; + break; + case MASK_DISABLE: + $$.header.mask_control = BRW_MASK_DISABLE; + break; + case BREAKPOINT: + $$.header.debug_control = BRW_DEBUG_BREAKPOINT; + break; + case EOT: + /* XXX: EOT shouldn't be an instoption, I don't think */ + $$.bits3.generic.end_of_thread = 1; + break; + } + } + | /* empty, header defaults to zeroes. */ + { + memset(&$$, 0, sizeof($$)); + } +; + +instoption: ALIGN1 { $$ = ALIGN1; } + | ALIGN16 { $$ = ALIGN16; } + | SECHALF { $$ = SECHALF; } + | COMPR { $$ = COMPR; } + | SWITCH { $$ = SWITCH; } + | ATOMIC { $$ = ATOMIC; } + | NODDCHK { $$ = NODDCHK; } + | NODDCLR { $$ = NODDCLR; } + | MASK_DISABLE { $$ = MASK_DISABLE; } + | BREAKPOINT { $$ = BREAKPOINT; } + | ACCWRCTRL { $$ = ACCWRCTRL; } + | EOT { $$ = EOT; } +; + +%% +extern int yylineno; +extern char *input_filename; + +int errors; + +void yyerror (char *msg) +{ + fprintf(stderr, "%s: %d: %s at \"%s\"\n", + input_filename, yylineno, msg, lex_text()); + ++errors; +} + +static int get_type_size(GLuint type) +{ + int size = 1; + + switch (type) { + case BRW_REGISTER_TYPE_F: + case BRW_REGISTER_TYPE_UD: + case BRW_REGISTER_TYPE_D: + size = 4; + break; + + case BRW_REGISTER_TYPE_UW: + case BRW_REGISTER_TYPE_W: + size = 2; + break; + + case BRW_REGISTER_TYPE_UB: + case BRW_REGISTER_TYPE_B: + size = 1; + break; + + default: + assert(0); + size = 1; + break; + } + + return size; +} + +static int get_subreg_address(GLuint regfile, GLuint type, GLuint subreg, GLuint address_mode) +{ + int unit_size = 1; + + if (address_mode == BRW_ADDRESS_DIRECT) { + if (advanced_flag == 1) { + if ((regfile == BRW_GENERAL_REGISTER_FILE || + regfile == BRW_MESSAGE_REGISTER_FILE || + regfile == BRW_ARCHITECTURE_REGISTER_FILE)) { + + unit_size = get_type_size(type); + } + } + } else { + unit_size = 1; + } + + return subreg * unit_size; +} + +/* only used in indirect address mode. + * input: sub-register number of an address register + * output: the value of AddrSubRegNum in the instruction binary code + * + * input output(advanced_flag==0) output(advanced_flag==1) + * a0.0 0 0 + * a0.1 invalid input 1 + * a0.2 1 2 + * a0.3 invalid input 3 + * a0.4 2 4 + * a0.5 invalid input 5 + * a0.6 3 6 + * a0.7 invalid input 7 + * a0.8 4 invalid input + * a0.10 5 invalid input + * a0.12 6 invalid input + * a0.14 7 invalid input + */ +static int get_indirect_subreg_address(GLuint subreg) +{ + return advanced_flag == 0 ? subreg / 2 : subreg; +} + +static void reset_instruction_src_region(struct brw_instruction *instr, + struct src_operand *src) +{ + if (!src->default_region) + return; + + if (src->reg_file == BRW_ARCHITECTURE_REGISTER_FILE && + ((src->reg_nr & 0xF0) == BRW_ARF_ADDRESS)) { + src->vert_stride = ffs(0); + src->width = ffs(1) - 1; + src->horiz_stride = ffs(0); + } else if (src->reg_file == BRW_ARCHITECTURE_REGISTER_FILE && + ((src->reg_nr & 0xF0) == BRW_ARF_ACCUMULATOR)) { + int horiz_stride = 1, width, vert_stride; + if (instr->header.compression_control == BRW_COMPRESSION_COMPRESSED) { + width = 16; + } else { + width = 8; + } + + if (width > (1 << instr->header.execution_size)) + width = (1 << instr->header.execution_size); + + vert_stride = horiz_stride * width; + src->vert_stride = ffs(vert_stride); + src->width = ffs(width) - 1; + src->horiz_stride = ffs(horiz_stride); + } else if ((src->reg_file == BRW_ARCHITECTURE_REGISTER_FILE) && + (src->reg_nr == BRW_ARF_NULL) && + (instr->header.opcode == BRW_OPCODE_SEND)) { + src->vert_stride = ffs(8); + src->width = ffs(8) - 1; + src->horiz_stride = ffs(1); + } else { + + int horiz_stride = 1, width, vert_stride; + + if (instr->header.execution_size == 0) { /* scalar */ + horiz_stride = 0; + width = 1; + vert_stride = 0; + } else { + if ((instr->header.opcode == BRW_OPCODE_MUL) || + (instr->header.opcode == BRW_OPCODE_MAC) || + (instr->header.opcode == BRW_OPCODE_CMP) || + (instr->header.opcode == BRW_OPCODE_ASR) || + (instr->header.opcode == BRW_OPCODE_ADD) || + (instr->header.opcode == BRW_OPCODE_SHL)) { + horiz_stride = 0; + width = 1; + vert_stride = 0; + } else { + width = (1 << instr->header.execution_size) / horiz_stride; + vert_stride = horiz_stride * width; + + if (get_type_size(src->reg_type) * (width + src->subreg_nr) > 32) { + horiz_stride = 0; + width = 1; + vert_stride = 0; + } + } + } + + src->vert_stride = ffs(vert_stride); + src->width = ffs(width) - 1; + src->horiz_stride = ffs(horiz_stride); + } +} + +/** + * Fills in the destination register information in instr from the bits in dst. + */ +int set_instruction_dest(struct brw_instruction *instr, + struct dst_operand *dest) +{ + if (dest->horiz_stride == DEFAULT_DSTREGION) + dest->horiz_stride = ffs(1); + if (dest->address_mode == BRW_ADDRESS_DIRECT && + instr->header.access_mode == BRW_ALIGN_1) { + instr->bits1.da1.dest_reg_file = dest->reg_file; + instr->bits1.da1.dest_reg_type = dest->reg_type; + instr->bits1.da1.dest_subreg_nr = get_subreg_address(dest->reg_file, dest->reg_type, dest->subreg_nr, dest->address_mode); + instr->bits1.da1.dest_reg_nr = dest->reg_nr; + instr->bits1.da1.dest_horiz_stride = dest->horiz_stride; + instr->bits1.da1.dest_address_mode = dest->address_mode; + if (dest->writemask_set) { + fprintf(stderr, "error: write mask set in align1 " + "instruction\n"); + return 1; + } + } else if (dest->address_mode == BRW_ADDRESS_DIRECT) { + instr->bits1.da16.dest_reg_file = dest->reg_file; + instr->bits1.da16.dest_reg_type = dest->reg_type; + instr->bits1.da16.dest_subreg_nr = get_subreg_address(dest->reg_file, dest->reg_type, dest->subreg_nr, dest->address_mode); + instr->bits1.da16.dest_reg_nr = dest->reg_nr; + instr->bits1.da16.dest_address_mode = dest->address_mode; + instr->bits1.da16.dest_horiz_stride = ffs(1); + instr->bits1.da16.dest_writemask = dest->writemask; + } else if (instr->header.access_mode == BRW_ALIGN_1) { + instr->bits1.ia1.dest_reg_file = dest->reg_file; + instr->bits1.ia1.dest_reg_type = dest->reg_type; + instr->bits1.ia1.dest_subreg_nr = get_indirect_subreg_address(dest->address_subreg_nr); + instr->bits1.ia1.dest_horiz_stride = dest->horiz_stride; + instr->bits1.ia1.dest_indirect_offset = dest->indirect_offset; + instr->bits1.ia1.dest_address_mode = dest->address_mode; + if (dest->writemask_set) { + fprintf(stderr, "error: write mask set in align1 " + "instruction\n"); + return 1; + } + } else { + instr->bits1.ia16.dest_reg_file = dest->reg_file; + instr->bits1.ia16.dest_reg_type = dest->reg_type; + instr->bits1.ia16.dest_subreg_nr = get_indirect_subreg_address(dest->address_subreg_nr); + instr->bits1.ia16.dest_writemask = dest->writemask; + instr->bits1.ia16.dest_horiz_stride = ffs(1); + instr->bits1.ia16.dest_indirect_offset = (dest->indirect_offset >> 4); /* half register aligned */ + instr->bits1.ia16.dest_address_mode = dest->address_mode; + } + + return 0; +} + +/* Sets the first source operand for the instruction. Returns 0 on success. */ +int set_instruction_src0(struct brw_instruction *instr, + struct src_operand *src) +{ + if (advanced_flag) { + reset_instruction_src_region(instr, src); + } + instr->bits1.da1.src0_reg_file = src->reg_file; + instr->bits1.da1.src0_reg_type = src->reg_type; + if (src->reg_file == BRW_IMMEDIATE_VALUE) { + instr->bits3.ud = src->imm32; + } else if (src->address_mode == BRW_ADDRESS_DIRECT) { + if (instr->header.access_mode == BRW_ALIGN_1) { + instr->bits2.da1.src0_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode); + instr->bits2.da1.src0_reg_nr = src->reg_nr; + instr->bits2.da1.src0_vert_stride = src->vert_stride; + instr->bits2.da1.src0_width = src->width; + instr->bits2.da1.src0_horiz_stride = src->horiz_stride; + instr->bits2.da1.src0_negate = src->negate; + instr->bits2.da1.src0_abs = src->abs; + instr->bits2.da1.src0_address_mode = src->address_mode; + if (src->swizzle_set) { + fprintf(stderr, "error: swizzle bits set in align1 " + "instruction\n"); + return 1; + } + } else { + instr->bits2.da16.src0_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode); + instr->bits2.da16.src0_reg_nr = src->reg_nr; + instr->bits2.da16.src0_vert_stride = src->vert_stride; + instr->bits2.da16.src0_negate = src->negate; + instr->bits2.da16.src0_abs = src->abs; + instr->bits2.da16.src0_swz_x = src->swizzle_x; + instr->bits2.da16.src0_swz_y = src->swizzle_y; + instr->bits2.da16.src0_swz_z = src->swizzle_z; + instr->bits2.da16.src0_swz_w = src->swizzle_w; + instr->bits2.da16.src0_address_mode = src->address_mode; + } + } else { + if (instr->header.access_mode == BRW_ALIGN_1) { + instr->bits2.ia1.src0_indirect_offset = src->indirect_offset; + instr->bits2.ia1.src0_subreg_nr = get_indirect_subreg_address(src->address_subreg_nr); + instr->bits2.ia1.src0_abs = src->abs; + instr->bits2.ia1.src0_negate = src->negate; + instr->bits2.ia1.src0_address_mode = src->address_mode; + instr->bits2.ia1.src0_horiz_stride = src->horiz_stride; + instr->bits2.ia1.src0_width = src->width; + instr->bits2.ia1.src0_vert_stride = src->vert_stride; + if (src->swizzle_set) { + fprintf(stderr, "error: swizzle bits set in align1 " + "instruction\n"); + return 1; + } + } else { + instr->bits2.ia16.src0_swz_x = src->swizzle_x; + instr->bits2.ia16.src0_swz_y = src->swizzle_y; + instr->bits2.ia16.src0_indirect_offset = (src->indirect_offset >> 4); /* half register aligned */ + instr->bits2.ia16.src0_subreg_nr = get_indirect_subreg_address(src->address_subreg_nr); + instr->bits2.ia16.src0_abs = src->abs; + instr->bits2.ia16.src0_negate = src->negate; + instr->bits2.ia16.src0_address_mode = src->address_mode; + instr->bits2.ia16.src0_swz_z = src->swizzle_z; + instr->bits2.ia16.src0_swz_w = src->swizzle_w; + instr->bits2.ia16.src0_vert_stride = src->vert_stride; + } + } + + return 0; +} + +/* Sets the second source operand for the instruction. Returns 0 on success. + */ +int set_instruction_src1(struct brw_instruction *instr, + struct src_operand *src) +{ + if (advanced_flag) { + reset_instruction_src_region(instr, src); + } + instr->bits1.da1.src1_reg_file = src->reg_file; + instr->bits1.da1.src1_reg_type = src->reg_type; + if (src->reg_file == BRW_IMMEDIATE_VALUE) { + instr->bits3.ud = src->imm32; + } else if (src->address_mode == BRW_ADDRESS_DIRECT) { + if (instr->header.access_mode == BRW_ALIGN_1) { + instr->bits3.da1.src1_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode); + instr->bits3.da1.src1_reg_nr = src->reg_nr; + instr->bits3.da1.src1_vert_stride = src->vert_stride; + instr->bits3.da1.src1_width = src->width; + instr->bits3.da1.src1_horiz_stride = src->horiz_stride; + instr->bits3.da1.src1_negate = src->negate; + instr->bits3.da1.src1_abs = src->abs; + instr->bits3.da1.src1_address_mode = src->address_mode; + /* XXX why? + if (src->address_mode != BRW_ADDRESS_DIRECT) { + fprintf(stderr, "error: swizzle bits set in align1 " + "instruction\n"); + return 1; + } + */ + if (src->swizzle_set) { + fprintf(stderr, "error: swizzle bits set in align1 " + "instruction\n"); + return 1; + } + } else { + instr->bits3.da16.src1_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode); + instr->bits3.da16.src1_reg_nr = src->reg_nr; + instr->bits3.da16.src1_vert_stride = src->vert_stride; + instr->bits3.da16.src1_negate = src->negate; + instr->bits3.da16.src1_abs = src->abs; + instr->bits3.da16.src1_swz_x = src->swizzle_x; + instr->bits3.da16.src1_swz_y = src->swizzle_y; + instr->bits3.da16.src1_swz_z = src->swizzle_z; + instr->bits3.da16.src1_swz_w = src->swizzle_w; + instr->bits3.da16.src1_address_mode = src->address_mode; + if (src->address_mode != BRW_ADDRESS_DIRECT) { + fprintf(stderr, "error: swizzle bits set in align1 " + "instruction\n"); + return 1; + } + } + } else { + if (instr->header.access_mode == BRW_ALIGN_1) { + instr->bits3.ia1.src1_indirect_offset = src->indirect_offset; + instr->bits3.ia1.src1_subreg_nr = get_indirect_subreg_address(src->address_subreg_nr); + instr->bits3.ia1.src1_abs = src->abs; + instr->bits3.ia1.src1_negate = src->negate; + instr->bits3.ia1.src1_address_mode = src->address_mode; + instr->bits3.ia1.src1_horiz_stride = src->horiz_stride; + instr->bits3.ia1.src1_width = src->width; + instr->bits3.ia1.src1_vert_stride = src->vert_stride; + if (src->swizzle_set) { + fprintf(stderr, "error: swizzle bits set in align1 " + "instruction\n"); + return 1; + } + } else { + instr->bits3.ia16.src1_swz_x = src->swizzle_x; + instr->bits3.ia16.src1_swz_y = src->swizzle_y; + instr->bits3.ia16.src1_indirect_offset = (src->indirect_offset >> 4); /* half register aligned */ + instr->bits3.ia16.src1_subreg_nr = get_indirect_subreg_address(src->address_subreg_nr); + instr->bits3.ia16.src1_abs = src->abs; + instr->bits3.ia16.src1_negate = src->negate; + instr->bits3.ia16.src1_address_mode = src->address_mode; + instr->bits3.ia16.src1_swz_z = src->swizzle_z; + instr->bits3.ia16.src1_swz_w = src->swizzle_w; + instr->bits3.ia16.src1_vert_stride = src->vert_stride; + } + } + + return 0; +} + +/* convert 2-src reg type to 3-src reg type + * + * 2-src reg type: + * 000=UD 001=D 010=UW 011=W 100=UB 101=B 110=DF 111=F + * + * 3-src reg type: + * 00=F 01=D 10=UD 11=DF + */ +static int reg_type_2_to_3(int reg_type) +{ + int r = 0; + switch(reg_type) { + case 7: r = 0; break; + case 1: r = 1; break; + case 0: r = 2; break; + // TODO: supporting DF + } + return r; +} + +int set_instruction_dest_three_src(struct brw_instruction *instr, + struct dst_operand *dest) +{ + instr->bits1.three_src_gen6.dest_reg_file = dest->reg_file; + instr->bits1.three_src_gen6.dest_reg_nr = dest->reg_nr; + instr->bits1.three_src_gen6.dest_subreg_nr = get_subreg_address(dest->reg_file, dest->reg_type, dest->subreg_nr, dest->address_mode) / 4; // in DWORD + instr->bits1.three_src_gen6.dest_writemask = dest->writemask; + instr->bits1.three_src_gen6.dest_reg_type = reg_type_2_to_3(dest->reg_type); + return 0; +} + +int set_instruction_src0_three_src(struct brw_instruction *instr, + struct src_operand *src) +{ + if (advanced_flag) { + reset_instruction_src_region(instr, src); + } + // TODO: supporting src0 swizzle, src0 modifier, src0 rep_ctrl + instr->bits1.three_src_gen6.src_reg_type = reg_type_2_to_3(src->reg_type); + instr->bits2.three_src_gen6.src0_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD + instr->bits2.three_src_gen6.src0_reg_nr = src->reg_nr; + return 0; +} + +int set_instruction_src1_three_src(struct brw_instruction *instr, + struct src_operand *src) +{ + if (advanced_flag) { + reset_instruction_src_region(instr, src); + } + // TODO: supporting src1 swizzle, src1 modifier, src1 rep_ctrl + int v = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD + instr->bits2.three_src_gen6.src1_subreg_nr_low = v % 4; // lower 2 bits + instr->bits3.three_src_gen6.src1_subreg_nr_high = v / 4; // highest bit + instr->bits3.three_src_gen6.src1_reg_nr = src->reg_nr; + return 0; +} + +int set_instruction_src2_three_src(struct brw_instruction *instr, + struct src_operand *src) +{ + if (advanced_flag) { + reset_instruction_src_region(instr, src); + } + // TODO: supporting src2 swizzle, src2 modifier, src2 rep_ctrl + instr->bits3.three_src_gen6.src2_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD + instr->bits3.three_src_gen6.src2_reg_nr = src->reg_nr; + return 0; +} + +void set_instruction_options(struct brw_instruction *instr, + struct brw_instruction *options) +{ + /* XXX: more instr options */ + instr->header.access_mode = options->header.access_mode; + instr->header.mask_control = options->header.mask_control; + instr->header.dependency_control = options->header.dependency_control; + instr->header.compression_control = + options->header.compression_control; +} + +void set_instruction_predicate(struct brw_instruction *instr, + struct brw_instruction *predicate) +{ + instr->header.predicate_control = predicate->header.predicate_control; + instr->header.predicate_inverse = predicate->header.predicate_inverse; + instr->bits2.da1.flag_reg_nr = predicate->bits2.da1.flag_reg_nr; + instr->bits2.da1.flag_subreg_nr = predicate->bits2.da1.flag_subreg_nr; +} + +void set_direct_dst_operand(struct dst_operand *dst, struct direct_reg *reg, + int type) +{ + memset(dst, 0, sizeof(*dst)); + dst->address_mode = BRW_ADDRESS_DIRECT; + dst->reg_file = reg->reg_file; + dst->reg_nr = reg->reg_nr; + dst->subreg_nr = reg->subreg_nr; + dst->reg_type = type; + dst->horiz_stride = 1; + dst->writemask_set = 0; + dst->writemask = 0xf; +} + +void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg, + int type) +{ + memset(src, 0, sizeof(*src)); + src->address_mode = BRW_ADDRESS_DIRECT; + src->reg_file = reg->reg_file; + src->reg_type = type; + src->subreg_nr = reg->subreg_nr; + src->reg_nr = reg->reg_nr; + src->vert_stride = 0; + src->width = 0; + src->horiz_stride = 0; + src->negate = 0; + src->abs = 0; + src->swizzle_set = 0; + src->swizzle_x = BRW_CHANNEL_X; + src->swizzle_y = BRW_CHANNEL_Y; + src->swizzle_z = BRW_CHANNEL_Z; + src->swizzle_w = BRW_CHANNEL_W; +} diff --git a/assembler/lex.l b/assembler/lex.l new file mode 100644 index 00000000..626042f6 --- /dev/null +++ b/assembler/lex.l @@ -0,0 +1,428 @@ +%option yylineno +%{ +#include +#include "gen4asm.h" +#include "gram.h" +#include "brw_defines.h" + +#include "string.h" +int saved_state = 0; +extern char *input_filename; + +%} +%x BLOCK_COMMENT +%x CHANNEL +%x LINENUMBER +%x FILENAME + +%% +\/\/.*[\r\n] { } /* eat up single-line comments */ +"\.kernel".*[\r\n] { } +"\.end_kernel".*[\r\n] { } +"\.code".*[\r\n] { } +"\.end_code".*[\r\n] { } + + /* eat up multi-line comments, non-nesting. */ +\/\* { + saved_state = YYSTATE; + BEGIN(BLOCK_COMMENT); +} +\*\/ { + BEGIN(saved_state); +} +. { } +[\r\n] { } +"#line"" "* { + saved_state = YYSTATE; + BEGIN(LINENUMBER); +} +[0-9]+" "* { + yylineno = atoi (yytext) - 1; + BEGIN(FILENAME); +} +\"[^\"]+\" { + char *name = malloc (yyleng - 1); + memmove (name, yytext + 1, yyleng - 2); + name[yyleng-1] = '\0'; + input_filename = name; + BEGIN(saved_state); +} + +"x" { + yylval.integer = BRW_CHANNEL_X; + return X; +} +"y" { + yylval.integer = BRW_CHANNEL_Y; + return Y; +} +"z" { + yylval.integer = BRW_CHANNEL_Z; + return Z; +} +"w" { +yylval.integer = BRW_CHANNEL_W; + return W; +} +. { + yyless(0); + BEGIN(INITIAL); +} + + /* used for both null send and null register. */ +"null" { return NULL_TOKEN; } + + /* opcodes */ +"mov" { yylval.integer = BRW_OPCODE_MOV; return MOV; } +"frc" { yylval.integer = BRW_OPCODE_FRC; return FRC; } +"rndu" { yylval.integer = BRW_OPCODE_RNDU; return RNDU; } +"rndd" { yylval.integer = BRW_OPCODE_RNDD; return RNDD; } +"rnde" { yylval.integer = BRW_OPCODE_RNDE; return RNDE; } +"rndz" { yylval.integer = BRW_OPCODE_RNDZ; return RNDZ; } +"not" { yylval.integer = BRW_OPCODE_NOT; return NOT; } +"lzd" { yylval.integer = BRW_OPCODE_LZD; return LZD; } +"f16to32" { yylval.integer = BRW_OPCODE_F16TO32; return F16TO32; } +"f32to16" { yylval.integer = BRW_OPCODE_F32TO16; return F32TO16; } +"fbh" { yylval.integer = BRW_OPCODE_FBH; return FBH; } +"fbl" { yylval.integer = BRW_OPCODE_FBL; return FBL; } + +"mad" { yylval.integer = BRW_OPCODE_MAD; return MAD; } +"lrp" { yylval.integer = BRW_OPCODE_LRP; return LRP; } +"bfe" { yylval.integer = BRW_OPCODE_BFE; return BFE; } +"bfi1" { yylval.integer = BRW_OPCODE_BFI1; return BFI1; } +"bfi2" { yylval.integer = BRW_OPCODE_BFI2; return BFI2; } +"bfrev" { yylval.integer = BRW_OPCODE_BFREV; return BFREV; } +"mul" { yylval.integer = BRW_OPCODE_MUL; return MUL; } +"mac" { yylval.integer = BRW_OPCODE_MAC; return MAC; } +"mach" { yylval.integer = BRW_OPCODE_MACH; return MACH; } +"line" { yylval.integer = BRW_OPCODE_LINE; return LINE; } +"sad2" { yylval.integer = BRW_OPCODE_SAD2; return SAD2; } +"sada2" { yylval.integer = BRW_OPCODE_SADA2; return SADA2; } +"dp4" { yylval.integer = BRW_OPCODE_DP4; return DP4; } +"dph" { yylval.integer = BRW_OPCODE_DPH; return DPH; } +"dp3" { yylval.integer = BRW_OPCODE_DP3; return DP3; } +"dp2" { yylval.integer = BRW_OPCODE_DP2; return DP2; } + +"cbit" { yylval.integer = BRW_OPCODE_CBIT; return CBIT; } +"avg" { yylval.integer = BRW_OPCODE_AVG; return AVG; } +"add" { yylval.integer = BRW_OPCODE_ADD; return ADD; } +"addc" { yylval.integer = BRW_OPCODE_ADDC; return ADDC; } +"sel" { yylval.integer = BRW_OPCODE_SEL; return SEL; } +"and" { yylval.integer = BRW_OPCODE_AND; return AND; } +"or" { yylval.integer = BRW_OPCODE_OR; return OR; } +"xor" { yylval.integer = BRW_OPCODE_XOR; return XOR; } +"shr" { yylval.integer = BRW_OPCODE_SHR; return SHR; } +"shl" { yylval.integer = BRW_OPCODE_SHL; return SHL; } +"asr" { yylval.integer = BRW_OPCODE_ASR; return ASR; } +"cmp" { yylval.integer = BRW_OPCODE_CMP; return CMP; } +"cmpn" { yylval.integer = BRW_OPCODE_CMPN; return CMPN; } +"subb" { yylval.integer = BRW_OPCODE_SUBB; return SUBB; } + +"send" { yylval.integer = BRW_OPCODE_SEND; return SEND; } +"nop" { yylval.integer = BRW_OPCODE_NOP; return NOP; } +"jmpi" { yylval.integer = BRW_OPCODE_JMPI; return JMPI; } +"if" { yylval.integer = BRW_OPCODE_IF; return IF; } +"iff" { yylval.integer = BRW_OPCODE_IFF; return IFF; } +"while" { yylval.integer = BRW_OPCODE_WHILE; return WHILE; } +"else" { yylval.integer = BRW_OPCODE_ELSE; return ELSE; } +"break" { yylval.integer = BRW_OPCODE_BREAK; return BREAK; } +"cont" { yylval.integer = BRW_OPCODE_CONTINUE; return CONT; } +"halt" { yylval.integer = BRW_OPCODE_HALT; return HALT; } +"msave" { yylval.integer = BRW_OPCODE_MSAVE; return MSAVE; } +"push" { yylval.integer = BRW_OPCODE_PUSH; return PUSH; } +"mrest" { yylval.integer = BRW_OPCODE_MRESTORE; return MREST; } +"pop" { yylval.integer = BRW_OPCODE_POP; return POP; } +"wait" { yylval.integer = BRW_OPCODE_WAIT; return WAIT; } +"do" { yylval.integer = BRW_OPCODE_DO; return DO; } +"endif" { yylval.integer = BRW_OPCODE_ENDIF; return ENDIF; } +"call" { yylval.integer = BRW_OPCODE_CALL; return CALL; } +"ret" { yylval.integer = BRW_OPCODE_RET; return RET; } +"brd" { yylval.integer = BRW_OPCODE_BRD; return BRD; } +"brc" { yylval.integer = BRW_OPCODE_BRC; return BRC; } + +"pln" { yylval.integer = BRW_OPCODE_PLN; return PLN; } + + /* send argument tokens */ +"mlen" { return MSGLEN; } +"rlen" { return RETURNLEN; } +"math" { if (IS_GENp(6)) { yylval.integer = BRW_OPCODE_MATH; return MATH_INST; } else return MATH; } +"sampler" { return SAMPLER; } +"gateway" { return GATEWAY; } +"read" { return READ; } +"write" { return WRITE; } +"urb" { return URB; } +"thread_spawner" { return THREAD_SPAWNER; } +"vme" { return VME; } +"cre" { return CRE; } +"data_port" { return DATA_PORT; } + +"allocate" { return ALLOCATE; } +"used" { return USED; } +"complete" { return COMPLETE; } +"transpose" { return TRANSPOSE; } +"interleave" { return INTERLEAVE; } + +";" { return SEMICOLON; } +"(" { return LPAREN; } +")" { return RPAREN; } +"<" { return LANGLE; } +">" { return RANGLE; } +"{" { return LCURLY; } +"}" { return RCURLY; } +"[" { return LSQUARE; } +"]" { return RSQUARE; } +"," { return COMMA; } +"." { BEGIN(CHANNEL); return DOT; } +"+" { return PLUS; } +"-" { return MINUS; } +"*" { return MULTIPLY;} +"/" { return DIVIDE; } +":" { return COLON; } +"=" { return EQ; } +"(abs)" { return ABS; } + + /* Most register accesses are lexed as REGFILE[0-9]+, to prevent the register + * with subreg from being lexed as REGFILE NUMBER instead of + * REGISTER INTEGER DOT INTEGER like we want. The alternative was to use a + * start condition, which wasn't very clean-looking. + * + * However, this means we need to lex the general and message register file + * characters as well, for register-indirect access which is formatted + * like g[a#.#] or m[a#.#]. + */ +"acc"[0-9]+ { + yylval.integer = atoi(yytext + 3); + return ACCREG; +} +"a"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return ADDRESSREG; +} +"m"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return MSGREG; +} +"m" { + return MSGREGFILE; +} +"mask"[0-9]+ { + yylval.integer = atoi(yytext + 4); + return MASKREG; +} +"ms"[0-9]+ { + yylval.integer = atoi(yytext + 2); + return MASKSTACKREG; +} +"msd"[0-9]+ { + yylval.integer = atoi(yytext + 3); + return MASKSTACKDEPTHREG; +} + +"n0."[0-9]+ { + yylval.integer = atoi(yytext + 3); + return NOTIFYREG; +} + +"n"[0-9]+ { + yylval.integer = atoi(yytext + 1); + return NOTIFYREG; +} + +"f"[0-9] { + yylval.integer = atoi(yytext + 1); + return FLAGREG; +} + +[gr][0-9]+ { + yylval.integer = atoi(yytext + 1); + return GENREG; +} +[gr] { + return GENREGFILE; +} +"cr"[0-9]+ { + yylval.integer = atoi(yytext + 2); + return CONTROLREG; +} +"sr"[0-9]+ { + yylval.integer = atoi(yytext + 2); + return STATEREG; +} +"ip" { + return IPREG; +} +"amask" { + yylval.integer = BRW_AMASK; + return AMASK; +} +"imask" { + yylval.integer = BRW_IMASK; + return IMASK; +} +"lmask" { + yylval.integer = BRW_LMASK; + return LMASK; +} +"cmask" { + yylval.integer = BRW_CMASK; + return CMASK; +} +"imsd" { + yylval.integer = 0; + return IMSD; +} +"lmsd" { + yylval.integer = 1; + return LMSD; +} +"ims" { + yylval.integer = 0; + return IMS; +} +"lms" { + yylval.integer = 16; + return LMS; +} + + /* + * Lexing of register types should probably require the ":" symbol specified + * in the BNF of the assembly, but our existing source didn't use that syntax. + */ +"UD" { return TYPE_UD; } +":UD" { return TYPE_UD; } +"D" { return TYPE_D; } +":D" { return TYPE_D; } +"UW" { return TYPE_UW; } +":UW" { return TYPE_UW; } +"W" { return TYPE_W; } +":W" { return TYPE_W; } +"UB" { return TYPE_UB; } +":UB" { return TYPE_UB; } +"B" { return TYPE_B; } +":B" { return TYPE_B; } +"F" { return TYPE_F; } +":F" { return TYPE_F; } +"VF" {return TYPE_VF; } +":VF" {return TYPE_VF; } +"V" { return TYPE_V; } +":V" { return TYPE_V; } + +#".kernel" { return KERNEL_PRAGMA;} +#".end_kernel" { return END_KERNEL_PRAGMA;} +#".code" { return CODE_PRAGMA;} +#".end_code" { return END_CODE_PRAGMA;} +".reg_count_payload" { return REG_COUNT_PAYLOAD_PRAGMA; } +".reg_count_total" { return REG_COUNT_TOTAL_PRAGMA; } +".default_execution_size" { return DEFAULT_EXEC_SIZE_PRAGMA; } +".default_register_type" { return DEFAULT_REG_TYPE_PRAGMA; } +".declare" { return DECLARE_PRAGMA; } +"Base" { return BASE; } +"ElementSize" { return ELEMENTSIZE; } +"SrcRegion" { return SRCREGION; } +"DstRegion" { return DSTREGION; } +"Type" { return TYPE; } + + +".sat" { return SATURATE; } +"align1" { return ALIGN1; } +"align16" { return ALIGN16; } +"sechalf" { return SECHALF; } +"compr" { return COMPR; } +"switch" { return SWITCH; } +"atomic" { return ATOMIC; } +"noddchk" { return NODDCHK; } +"noddclr" { return NODDCLR; } +"mask_disable" { return MASK_DISABLE; } +"nomask" { return MASK_DISABLE; } +"breakpoint" { return BREAKPOINT; } +"accwrctrl" { return ACCWRCTRL; } +"EOT" { return EOT; } + + /* extended math functions */ +"inv" { yylval.integer = BRW_MATH_FUNCTION_INV; return SIN; } +"log" { yylval.integer = BRW_MATH_FUNCTION_LOG; return LOG; } +"exp" { yylval.integer = BRW_MATH_FUNCTION_EXP; return EXP; } +"sqrt" { yylval.integer = BRW_MATH_FUNCTION_SQRT; return SQRT; } +"rsq" { yylval.integer = BRW_MATH_FUNCTION_RSQ; return RSQ; } +"pow" { yylval.integer = BRW_MATH_FUNCTION_POW; return POW; } +"sin" { yylval.integer = BRW_MATH_FUNCTION_SIN; return SIN; } +"cos" { yylval.integer = BRW_MATH_FUNCTION_COS; return COS; } +"sincos" { yylval.integer = BRW_MATH_FUNCTION_SINCOS; return SINCOS; } +"intdiv" { + yylval.integer = BRW_MATH_FUNCTION_INT_DIV_QUOTIENT; + return INTDIV; +} +"intmod" { + yylval.integer = BRW_MATH_FUNCTION_INT_DIV_REMAINDER; + return INTMOD; +} +"intdivmod" { + yylval.integer = BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER; + return INTDIVMOD; +} + +"signed" { return SIGNED; } +"scalar" { return SCALAR; } + + /* predicate control */ +".anyv" { return ANYV; } +".allv" { return ALLV; } +".any2h" { return ANY2H; } +".all2h" { return ALL2H; } +".any4h" { return ANY4H; } +".all4h" { return ALL4H; } +".any8h" { return ANY8H; } +".all8h" { return ALL8H; } +".any16h" { return ANY16H; } +".all16h" { return ALL16H; } + +".z" { yylval.integer = BRW_CONDITIONAL_Z; return ZERO; } +".e" { yylval.integer = BRW_CONDITIONAL_Z; return EQUAL; } +".nz" { yylval.integer = BRW_CONDITIONAL_NZ; return NOT_ZERO; } +".ne" { yylval.integer = BRW_CONDITIONAL_NZ; return NOT_EQUAL; } +".g" { yylval.integer = BRW_CONDITIONAL_G; return GREATER; } +".ge" { yylval.integer = BRW_CONDITIONAL_GE; return GREATER_EQUAL; } +".l" { yylval.integer = BRW_CONDITIONAL_L; return LESS; } +".le" { yylval.integer = BRW_CONDITIONAL_LE; return LESS_EQUAL; } +".r" { yylval.integer = BRW_CONDITIONAL_R; return ROUND_INCREMENT; } +".o" { yylval.integer = BRW_CONDITIONAL_O; return OVERFLOW; } +".u" { yylval.integer = BRW_CONDITIONAL_U; return UNORDERED; } + +[a-zA-Z_][0-9a-zA-Z_]* { + yylval.string = strdup(yytext); + return STRING; +} + +0x[0-9a-fA-F][0-9a-fA-F]* { + yylval.integer = strtoul(yytext + 2, NULL, 16); + return INTEGER; +} +[0-9][0-9]* { + yylval.integer = strtoul(yytext, NULL, 10); + return INTEGER; +} + +[-]?[0-9]+"."[0-9]+ { + yylval.number = strtod(yytext, NULL); + return NUMBER; +} + +[ \t\n]+ { } /* eat up whitespace */ + +. { + fprintf(stderr, "%s: %d: %s at \"%s\"\n", + input_filename, yylineno, "unexpected token", lex_text()); + } +%% + +char * +lex_text(void) +{ + return yytext; + (void) yyunput; +} + +#ifndef yywrap +int yywrap() { return 1; } +#endif + diff --git a/assembler/main.c b/assembler/main.c new file mode 100644 index 00000000..15ed5179 --- /dev/null +++ b/assembler/main.c @@ -0,0 +1,493 @@ +/* -*- c-basic-offset: 8 -*- */ +/* + * Copyright © 2006 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include +#include +#include +#include + +#include "gen4asm.h" + +extern FILE *yyin; + +extern int errors; + +long int gen_level = 40; +int advanced_flag = 0; /* 0: in unit of byte, 1: in unit of data element size */ +int binary_like_output = 0; /* 0: default output style, 1: nice C-style output */ +int need_export = 0; +char *input_filename = ""; +char *export_filename = NULL; + +const char const *binary_prepend = "static const char gen_eu_bytes[] = {\n"; + +struct brw_program compiled_program; +struct program_defaults program_defaults = {.register_type = BRW_REGISTER_TYPE_F}; + +#define HASH_SIZE 37 + +struct hash_item { + char *key; + void *value; + struct hash_item *next; +}; + +typedef struct hash_item *hash_table[HASH_SIZE]; + +static hash_table declared_register_table; + +struct label_item { + char *name; + int addr; + struct label_item *next; +}; +static struct label_item *label_table; + +static const struct option longopts[] = { + {"advanced", no_argument, 0, 'a'}, + {"binary", no_argument, 0, 'b'}, + {"export", required_argument, 0, 'e'}, + {"input_list", required_argument, 0, 'l'}, + {"output", required_argument, 0, 'o'}, + {"gen", required_argument, 0, 'g'}, + { NULL, 0, NULL, 0 } +}; + +// jump distance used in branch instructions as JIP or UIP +static int jump_distance(int offset) +{ + // Gen4- bspec: the jump distance is in number of sixteen-byte units + // Gen5+ bspec: the jump distance is in number of eight-byte units + if(IS_GENp(5)) + offset *= 2; + return offset; +} + +static void usage(void) +{ + fprintf(stderr, "usage: intel-gen4asm [options] inputfile\n"); + fprintf(stderr, "OPTIONS:\n"); + fprintf(stderr, "\t-a, --advanced Set advanced flag\n"); + fprintf(stderr, "\t-b, --binary C style binary output\n"); + fprintf(stderr, "\t-e, --export {exportfile} Export label file\n"); + fprintf(stderr, "\t-l, --input_list {entrytablefile} Input entry_table_list file\n"); + fprintf(stderr, "\t-o, --output {outputfile} Specify output file\n"); + fprintf(stderr, "\t-g, --gen <4|5|6|7> Specify GPU generation\n"); +} + +static int hash(char *key) +{ + unsigned ret = 0; + while(*key) + ret = (ret << 1) + (*key++); + return ret % HASH_SIZE; +} + +static void *find_hash_item(hash_table t, char *key) +{ + struct hash_item *p; + for(p = t[hash(key)]; p; p = p->next) + if(strcasecmp(p->key, key) == 0) + return p->value; + return NULL; +} + +static void insert_hash_item(hash_table t, char *key, void *v) +{ + int index = hash(key); + struct hash_item *p = malloc(sizeof(*p)); + p->key = key; + p->value = v; + p->next = t[index]; + t[index] = p; +} + +static void free_hash_table(hash_table t) +{ + struct hash_item *p, *next; + int i; + for (i = 0; i < HASH_SIZE; i++) { + p = t[i]; + while(p) { + next = p->next; + free(p->key); + free(p->value); + free(p); + p = next; + } + } +} + +struct declared_register *find_register(char *name) +{ + return find_hash_item(declared_register_table, name); +} + +void insert_register(struct declared_register *reg) +{ + insert_hash_item(declared_register_table, reg->name, reg); +} + +void add_label(char *name, int addr) +{ + struct label_item **p = &label_table; + while(*p) + p = &((*p)->next); + *p = calloc(1, sizeof(**p)); + (*p)->name = name; + (*p)->addr = addr; +} + +/* Some assembly code have duplicated labels. + Start from start_addr. Search as a loop. Return the first label found. */ +int label_to_addr(char *name, int start_addr) +{ + /* return the first label just after start_addr, or the first label from the head */ + struct label_item *p; + int r = -1; + for(p = label_table; p; p = p->next) { + if(strcmp(p->name, name) == 0) { + if(p->addr >= start_addr) // the first label just after start_addr + return p->addr; + else if(r == -1) // the first label from the head + r = p->addr; + } + } + if(r == -1) { + fprintf(stderr, "Can't find label %s\n", name); + exit(1); + } + return r; +} + +static void free_label_table(struct label_item *p) +{ + if(p) { + free_label_table(p->next); + free(p); + } +} + +struct entry_point_item { + char *str; + struct entry_point_item *next; +} *entry_point_table; + +static int read_entry_file(char *fn) +{ + FILE *entry_table_file; + char buf[2048]; + struct entry_point_item **p = &entry_point_table; + if (!fn) + return 0; + if ((entry_table_file = fopen(fn, "r")) == NULL) + return -1; + while (fgets(buf, sizeof(buf)-1, entry_table_file) != NULL) { + // drop the final char '\n' + if(buf[strlen(buf)-1] == '\n') + buf[strlen(buf)-1] = 0; + *p = calloc(1, sizeof(struct entry_point_item)); + (*p)->str = strdup(buf); + p = &((*p)->next); + } + fclose(entry_table_file); + return 0; +} + +static int is_entry_point(char *s) +{ + struct entry_point_item *p; + for (p = entry_point_table; p; p = p->next) { + if (strcmp(p->str, s) == 0) + return 1; + } + return 0; +} + +static void free_entry_point_table(struct entry_point_item *p) { + if (p) { + free_entry_point_table(p->next); + free(p->str); + free(p); + } +} + +static void +print_instruction(FILE *output, struct brw_program_instruction *entry) +{ + if (binary_like_output) { + fprintf(output, "\t0x%02x, 0x%02x, 0x%02x, 0x%02x, " + "0x%02x, 0x%02x, 0x%02x, 0x%02x,\n" + "\t0x%02x, 0x%02x, 0x%02x, 0x%02x, " + "0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", + ((unsigned char *)(&entry->instruction))[0], + ((unsigned char *)(&entry->instruction))[1], + ((unsigned char *)(&entry->instruction))[2], + ((unsigned char *)(&entry->instruction))[3], + ((unsigned char *)(&entry->instruction))[4], + ((unsigned char *)(&entry->instruction))[5], + ((unsigned char *)(&entry->instruction))[6], + ((unsigned char *)(&entry->instruction))[7], + ((unsigned char *)(&entry->instruction))[8], + ((unsigned char *)(&entry->instruction))[9], + ((unsigned char *)(&entry->instruction))[10], + ((unsigned char *)(&entry->instruction))[11], + ((unsigned char *)(&entry->instruction))[12], + ((unsigned char *)(&entry->instruction))[13], + ((unsigned char *)(&entry->instruction))[14], + ((unsigned char *)(&entry->instruction))[15]); + } else { + fprintf(output, " { 0x%08x, 0x%08x, 0x%08x, 0x%08x },\n", + ((int *)(&entry->instruction))[0], + ((int *)(&entry->instruction))[1], + ((int *)(&entry->instruction))[2], + ((int *)(&entry->instruction))[3]); + } +} +int main(int argc, char **argv) +{ + char *output_file = NULL; + char *entry_table_file = NULL; + FILE *output = stdout; + FILE *export_file; + struct brw_program_instruction *entry, *entry1, *tmp_entry; + int err, inst_offset; + char o; + while ((o = getopt_long(argc, argv, "e:l:o:g:ab", longopts, NULL)) != -1) { + switch (o) { + case 'o': + if (strcmp(optarg, "-") != 0) + output_file = optarg; + + break; + + case 'g': { + char *dec_ptr, *end_ptr; + unsigned long decimal; + + gen_level = strtol(optarg, &dec_ptr, 10) * 10; + + if (*dec_ptr == '.') { + decimal = strtoul(++dec_ptr, &end_ptr, 10); + if (end_ptr != dec_ptr && *end_ptr == '\0') { + if (decimal > 10) { + fprintf(stderr, "Invalid Gen X decimal version\n"); + exit(1); + } + gen_level += decimal; + } + } + + if (gen_level < 40 || gen_level > 75) { + usage(); + exit(1); + } + + break; + } + + case 'a': + advanced_flag = 1; + break; + case 'b': + binary_like_output = 1; + break; + + case 'e': + need_export = 1; + if (strcmp(optarg, "-") != 0) + export_filename = optarg; + break; + + case 'l': + if (strcmp(optarg, "-") != 0) + entry_table_file = optarg; + break; + + default: + usage(); + exit(1); + } + } + argc -= optind; + argv += optind; + if (argc != 1) { + usage(); + exit(1); + } + + if (strcmp(argv[0], "-") != 0) { + input_filename = argv[0]; + yyin = fopen(input_filename, "r"); + if (yyin == NULL) { + perror("Couldn't open input file"); + exit(1); + } + } + + err = yyparse(); + + if (strcmp(argv[0], "-")) + fclose(yyin); + + yylex_destroy(); + + if (err || errors) + exit (1); + + if (output_file) { + output = fopen(output_file, "w"); + if (output == NULL) { + perror("Couldn't open output file"); + exit(1); + } + + } + + if (read_entry_file(entry_table_file)) { + fprintf(stderr, "Read entry file error\n"); + exit(1); + } + inst_offset = 0 ; + for (entry = compiled_program.first; + entry != NULL; entry = entry->next) { + entry->inst_offset = inst_offset; + entry1 = entry->next; + if (entry1 && entry1->islabel && is_entry_point(entry1->string)) { + // insert NOP instructions until (inst_offset+1) % 4 == 0 + while (((inst_offset+1) % 4) != 0) { + tmp_entry = calloc(sizeof(*tmp_entry), 1); + tmp_entry->instruction.header.opcode = BRW_OPCODE_NOP; + entry->next = tmp_entry; + tmp_entry->next = entry1; + entry = tmp_entry; + tmp_entry->inst_offset = ++inst_offset; + } + } + if (!entry->islabel) + inst_offset++; + } + + for (entry = compiled_program.first; entry; entry = entry->next) + if (entry->islabel) + add_label(entry->string, entry->inst_offset); + + if (need_export) { + if (export_filename) { + export_file = fopen(export_filename, "w"); + } else { + export_file = fopen("export.inc", "w"); + } + for (entry = compiled_program.first; + entry != NULL; entry = entry->next) { + if (entry->islabel) + fprintf(export_file, "#define %s_IP %d\n", + entry->string, (IS_GENx(5) ? 2 : 1)*(entry->inst_offset)); + } + fclose(export_file); + } + + for (entry = compiled_program.first; entry; entry = entry->next) { + struct brw_instruction *inst = & entry->instruction; + + if (inst->first_reloc_target) + inst->first_reloc_offset = label_to_addr(inst->first_reloc_target, entry->inst_offset) - entry->inst_offset; + + if (inst->second_reloc_target) + inst->second_reloc_offset = label_to_addr(inst->second_reloc_target, entry->inst_offset) - entry->inst_offset; + + if (inst->second_reloc_offset) { + // this is a branch instruction with two offset arguments + entry->instruction.bits3.branch_2_offset.JIP = jump_distance(inst->first_reloc_offset); + entry->instruction.bits3.branch_2_offset.UIP = jump_distance(inst->second_reloc_offset); + } else if (inst->first_reloc_offset) { + // this is a branch instruction with one offset argument + int offset = inst->first_reloc_offset; + /* bspec: Unlike other flow control instructions, the offset used by JMPI is relative to the incremented instruction pointer rather than the IP value for the instruction itself. */ + + int is_jmpi = entry->instruction.header.opcode == BRW_OPCODE_JMPI; // target relative to the post-incremented IP, so delta == 1 if JMPI + if(is_jmpi) + offset --; + offset = jump_distance(offset); + if (is_jmpi && (gen_level == 75)) + offset = offset * 8; + + if(!IS_GENp(6)) { + entry->instruction.bits3.JIP = offset; + if(entry->instruction.header.opcode == BRW_OPCODE_ELSE) + entry->instruction.bits3.branch_2_offset.UIP = 1; /* Set the istack pop count, which must always be 1. */ + } else if(IS_GENx(6)) { + /* TODO: endif JIP pos is not in Gen6 spec. may be bits1 */ + int opcode = entry->instruction.header.opcode; + if(opcode == BRW_OPCODE_CALL || opcode == BRW_OPCODE_JMPI) + entry->instruction.bits3.JIP = offset; // for CALL, JMPI + else + entry->instruction.bits1.branch.JIP = offset; // for CASE,ELSE,FORK,IF,WHILE + } else if(IS_GENp(7)) { + int opcode = entry->instruction.header.opcode; + /* Gen7 JMPI Restrictions in bspec: + * The JIP data type must be Signed DWord + */ + if(opcode == BRW_OPCODE_JMPI) + entry->instruction.bits3.JIP = offset; + else + entry->instruction.bits3.branch_2_offset.JIP = offset; + } + } + } + + if (binary_like_output) + fprintf(output, "%s", binary_prepend); + + for (entry = compiled_program.first; + entry != NULL; + entry = entry1) { + entry1 = entry->next; + if (!entry->islabel) + print_instruction(output, entry); + else + free(entry->string); + free(entry); + } + if (binary_like_output) + fprintf(output, "};"); + + free_entry_point_table(entry_point_table); + free_hash_table(declared_register_table); + free_label_table(label_table); + + fflush (output); + if (ferror (output)) { + perror ("Could not flush output file"); + if (output_file) + unlink (output_file); + err = 1; + } + return err; +} diff --git a/assembler/src/Makefile.am b/assembler/src/Makefile.am deleted file mode 100644 index 09ad400c..00000000 --- a/assembler/src/Makefile.am +++ /dev/null @@ -1,23 +0,0 @@ -AM_YFLAGS = -d --warnings=all - -AM_CFLAGS= $(WARN_CFLAGS) -bin_PROGRAMS = intel-gen4asm intel-gen4disasm - -intel_gen4asm_SOURCES = \ - brw_defines.h \ - brw_structs.h \ - gen4asm.h \ - gram.y \ - lex.l \ - main.c - -intel_gen4disasm_SOURCES = \ - disasm.c disasm-main.c - -gram.h: gram.c - -BUILT_SOURCES = gram.h gram.c lex.c -MAINTAINERCLEANFILES = $(BUILT_SOURCES) -LEX = flex -i - -# man_MANS = intel-gen4asm.1 diff --git a/assembler/src/brw_defines.h b/assembler/src/brw_defines.h deleted file mode 100644 index 2ec8050c..00000000 --- a/assembler/src/brw_defines.h +++ /dev/null @@ -1,878 +0,0 @@ - /************************************************************************** - * - * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#ifndef BRW_DEFINES_H -#define BRW_DEFINES_H - -/* - */ -#define MI_NOOP 0x00 -#define MI_USER_INTERRUPT 0x02 -#define MI_WAIT_FOR_EVENT 0x03 -#define MI_FLUSH 0x04 -#define MI_REPORT_HEAD 0x07 -#define MI_ARB_ON_OFF 0x08 -#define MI_BATCH_BUFFER_END 0x0A -#define MI_OVERLAY_FLIP 0x11 -#define MI_LOAD_SCAN_LINES_INCL 0x12 -#define MI_LOAD_SCAN_LINES_EXCL 0x13 -#define MI_DISPLAY_BUFFER_INFO 0x14 -#define MI_SET_CONTEXT 0x18 -#define MI_STORE_DATA_IMM 0x20 -#define MI_STORE_DATA_INDEX 0x21 -#define MI_LOAD_REGISTER_IMM 0x22 -#define MI_STORE_REGISTER_MEM 0x24 -#define MI_BATCH_BUFFER_START 0x31 - -#define MI_SYNCHRONOUS_FLIP 0x0 -#define MI_ASYNCHRONOUS_FLIP 0x1 - -#define MI_BUFFER_SECURE 0x0 -#define MI_BUFFER_NONSECURE 0x1 - -#define MI_ARBITRATE_AT_CHAIN_POINTS 0x0 -#define MI_ARBITRATE_BETWEEN_INSTS 0x1 -#define MI_NO_ARBITRATION 0x3 - -#define MI_CONDITION_CODE_WAIT_DISABLED 0x0 -#define MI_CONDITION_CODE_WAIT_0 0x1 -#define MI_CONDITION_CODE_WAIT_1 0x2 -#define MI_CONDITION_CODE_WAIT_2 0x3 -#define MI_CONDITION_CODE_WAIT_3 0x4 -#define MI_CONDITION_CODE_WAIT_4 0x5 - -#define MI_DISPLAY_PIPE_A 0x0 -#define MI_DISPLAY_PIPE_B 0x1 - -#define MI_DISPLAY_PLANE_A 0x0 -#define MI_DISPLAY_PLANE_B 0x1 -#define MI_DISPLAY_PLANE_C 0x2 - -#define MI_STANDARD_FLIP 0x0 -#define MI_ENQUEUE_FLIP_PERFORM_BASE_FRAME_NUMBER_LOAD 0x1 -#define MI_ENQUEUE_FLIP_TARGET_FRAME_NUMBER_RELATIVE 0x2 -#define MI_ENQUEUE_FLIP_ABSOLUTE_TARGET_FRAME_NUMBER 0x3 - -#define MI_PHYSICAL_ADDRESS 0x0 -#define MI_VIRTUAL_ADDRESS 0x1 - -#define MI_BUFFER_MEMORY_MAIN 0x0 -#define MI_BUFFER_MEMORY_GTT 0x2 -#define MI_BUFFER_MEMORY_PER_PROCESS_GTT 0x3 - -#define MI_FLIP_CONTINUE 0x0 -#define MI_FLIP_ON 0x1 -#define MI_FLIP_OFF 0x2 - -#define MI_UNTRUSTED_REGISTER_SPACE 0x0 -#define MI_TRUSTED_REGISTER_SPACE 0x1 - -/* 3D state: - */ -#define _3DOP_3DSTATE_PIPELINED 0x0 -#define _3DOP_3DSTATE_NONPIPELINED 0x1 -#define _3DOP_3DCONTROL 0x2 -#define _3DOP_3DPRIMITIVE 0x3 - -#define _3DSTATE_PIPELINED_POINTERS 0x00 -#define _3DSTATE_BINDING_TABLE_POINTERS 0x01 -#define _3DSTATE_VERTEX_BUFFERS 0x08 -#define _3DSTATE_VERTEX_ELEMENTS 0x09 -#define _3DSTATE_INDEX_BUFFER 0x0A -#define _3DSTATE_VF_STATISTICS 0x0B -#define _3DSTATE_DRAWING_RECTANGLE 0x00 -#define _3DSTATE_CONSTANT_COLOR 0x01 -#define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02 -#define _3DSTATE_CHROMA_KEY 0x04 -#define _3DSTATE_DEPTH_BUFFER 0x05 -#define _3DSTATE_POLY_STIPPLE_OFFSET 0x06 -#define _3DSTATE_POLY_STIPPLE_PATTERN 0x07 -#define _3DSTATE_LINE_STIPPLE 0x08 -#define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09 -#define _3DCONTROL 0x00 -#define _3DPRIMITIVE 0x00 - -#define PIPE_CONTROL_NOWRITE 0x00 -#define PIPE_CONTROL_WRITEIMMEDIATE 0x01 -#define PIPE_CONTROL_WRITEDEPTH 0x02 -#define PIPE_CONTROL_WRITETIMESTAMP 0x03 - -#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00 -#define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01 - -#define _3DPRIM_POINTLIST 0x01 -#define _3DPRIM_LINELIST 0x02 -#define _3DPRIM_LINESTRIP 0x03 -#define _3DPRIM_TRILIST 0x04 -#define _3DPRIM_TRISTRIP 0x05 -#define _3DPRIM_TRIFAN 0x06 -#define _3DPRIM_QUADLIST 0x07 -#define _3DPRIM_QUADSTRIP 0x08 -#define _3DPRIM_LINELIST_ADJ 0x09 -#define _3DPRIM_LINESTRIP_ADJ 0x0A -#define _3DPRIM_TRILIST_ADJ 0x0B -#define _3DPRIM_TRISTRIP_ADJ 0x0C -#define _3DPRIM_TRISTRIP_REVERSE 0x0D -#define _3DPRIM_POLYGON 0x0E -#define _3DPRIM_RECTLIST 0x0F -#define _3DPRIM_LINELOOP 0x10 -#define _3DPRIM_POINTLIST_BF 0x11 -#define _3DPRIM_LINESTRIP_CONT 0x12 -#define _3DPRIM_LINESTRIP_BF 0x13 -#define _3DPRIM_LINESTRIP_CONT_BF 0x14 -#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 - -#define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0 -#define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1 - -#define BRW_ANISORATIO_2 0 -#define BRW_ANISORATIO_4 1 -#define BRW_ANISORATIO_6 2 -#define BRW_ANISORATIO_8 3 -#define BRW_ANISORATIO_10 4 -#define BRW_ANISORATIO_12 5 -#define BRW_ANISORATIO_14 6 -#define BRW_ANISORATIO_16 7 - -#define BRW_BLENDFACTOR_ONE 0x1 -#define BRW_BLENDFACTOR_SRC_COLOR 0x2 -#define BRW_BLENDFACTOR_SRC_ALPHA 0x3 -#define BRW_BLENDFACTOR_DST_ALPHA 0x4 -#define BRW_BLENDFACTOR_DST_COLOR 0x5 -#define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 -#define BRW_BLENDFACTOR_CONST_COLOR 0x7 -#define BRW_BLENDFACTOR_CONST_ALPHA 0x8 -#define BRW_BLENDFACTOR_SRC1_COLOR 0x9 -#define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A -#define BRW_BLENDFACTOR_ZERO 0x11 -#define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12 -#define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13 -#define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14 -#define BRW_BLENDFACTOR_INV_DST_COLOR 0x15 -#define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17 -#define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18 -#define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19 -#define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A - -#define BRW_BLENDFUNCTION_ADD 0 -#define BRW_BLENDFUNCTION_SUBTRACT 1 -#define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2 -#define BRW_BLENDFUNCTION_MIN 3 -#define BRW_BLENDFUNCTION_MAX 4 - -#define BRW_ALPHATEST_FORMAT_UNORM8 0 -#define BRW_ALPHATEST_FORMAT_FLOAT32 1 - -#define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0 -#define BRW_CHROMAKEY_REPLACE_BLACK 1 - -#define BRW_CLIP_API_OGL 0 -#define BRW_CLIP_API_DX 1 - -#define BRW_CLIPMODE_NORMAL 0 -#define BRW_CLIPMODE_CLIP_ALL 1 -#define BRW_CLIPMODE_CLIP_NON_REJECTED 2 -#define BRW_CLIPMODE_REJECT_ALL 3 -#define BRW_CLIPMODE_ACCEPT_ALL 4 - -#define BRW_CLIP_NDCSPACE 0 -#define BRW_CLIP_SCREENSPACE 1 - -#define BRW_COMPAREFUNCTION_ALWAYS 0 -#define BRW_COMPAREFUNCTION_NEVER 1 -#define BRW_COMPAREFUNCTION_LESS 2 -#define BRW_COMPAREFUNCTION_EQUAL 3 -#define BRW_COMPAREFUNCTION_LEQUAL 4 -#define BRW_COMPAREFUNCTION_GREATER 5 -#define BRW_COMPAREFUNCTION_NOTEQUAL 6 -#define BRW_COMPAREFUNCTION_GEQUAL 7 - -#define BRW_COVERAGE_PIXELS_HALF 0 -#define BRW_COVERAGE_PIXELS_1 1 -#define BRW_COVERAGE_PIXELS_2 2 -#define BRW_COVERAGE_PIXELS_4 3 - -#define BRW_CULLMODE_BOTH 0 -#define BRW_CULLMODE_NONE 1 -#define BRW_CULLMODE_FRONT 2 -#define BRW_CULLMODE_BACK 3 - -#define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0 -#define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 - -#define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 -#define BRW_DEPTHFORMAT_D32_FLOAT 1 -#define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2 -#define BRW_DEPTHFORMAT_D16_UNORM 5 - -#define BRW_FLOATING_POINT_IEEE_754 0 -#define BRW_FLOATING_POINT_NON_IEEE_754 1 - -#define BRW_FRONTWINDING_CW 0 -#define BRW_FRONTWINDING_CCW 1 - -#define BRW_INDEX_BYTE 0 -#define BRW_INDEX_WORD 1 -#define BRW_INDEX_DWORD 2 - -#define BRW_LOGICOPFUNCTION_CLEAR 0 -#define BRW_LOGICOPFUNCTION_NOR 1 -#define BRW_LOGICOPFUNCTION_AND_INVERTED 2 -#define BRW_LOGICOPFUNCTION_COPY_INVERTED 3 -#define BRW_LOGICOPFUNCTION_AND_REVERSE 4 -#define BRW_LOGICOPFUNCTION_INVERT 5 -#define BRW_LOGICOPFUNCTION_XOR 6 -#define BRW_LOGICOPFUNCTION_NAND 7 -#define BRW_LOGICOPFUNCTION_AND 8 -#define BRW_LOGICOPFUNCTION_EQUIV 9 -#define BRW_LOGICOPFUNCTION_NOOP 10 -#define BRW_LOGICOPFUNCTION_OR_INVERTED 11 -#define BRW_LOGICOPFUNCTION_COPY 12 -#define BRW_LOGICOPFUNCTION_OR_REVERSE 13 -#define BRW_LOGICOPFUNCTION_OR 14 -#define BRW_LOGICOPFUNCTION_SET 15 - -#define BRW_MAPFILTER_NEAREST 0x0 -#define BRW_MAPFILTER_LINEAR 0x1 -#define BRW_MAPFILTER_ANISOTROPIC 0x2 - -#define BRW_MIPFILTER_NONE 0 -#define BRW_MIPFILTER_NEAREST 1 -#define BRW_MIPFILTER_LINEAR 3 - -#define BRW_POLYGON_FRONT_FACING 0 -#define BRW_POLYGON_BACK_FACING 1 - -#define BRW_PREFILTER_ALWAYS 0x0 -#define BRW_PREFILTER_NEVER 0x1 -#define BRW_PREFILTER_LESS 0x2 -#define BRW_PREFILTER_EQUAL 0x3 -#define BRW_PREFILTER_LEQUAL 0x4 -#define BRW_PREFILTER_GREATER 0x5 -#define BRW_PREFILTER_NOTEQUAL 0x6 -#define BRW_PREFILTER_GEQUAL 0x7 - -#define BRW_PROVOKING_VERTEX_0 0 -#define BRW_PROVOKING_VERTEX_1 1 -#define BRW_PROVOKING_VERTEX_2 2 - -#define BRW_RASTRULE_UPPER_LEFT 0 -#define BRW_RASTRULE_UPPER_RIGHT 1 - -#define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0 -#define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1 -#define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2 - -#define BRW_STENCILOP_KEEP 0 -#define BRW_STENCILOP_ZERO 1 -#define BRW_STENCILOP_REPLACE 2 -#define BRW_STENCILOP_INCRSAT 3 -#define BRW_STENCILOP_DECRSAT 4 -#define BRW_STENCILOP_INCR 5 -#define BRW_STENCILOP_DECR 6 -#define BRW_STENCILOP_INVERT 7 - -#define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0 -#define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1 - -#define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 -#define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001 -#define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002 -#define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 -#define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 -#define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005 -#define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 -#define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 -#define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 -#define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040 -#define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041 -#define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042 -#define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043 -#define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044 -#define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045 -#define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046 -#define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 -#define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 -#define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082 -#define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083 -#define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 -#define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 -#define BRW_SURFACEFORMAT_R32G32_SINT 0x086 -#define BRW_SURFACEFORMAT_R32G32_UINT 0x087 -#define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 -#define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 -#define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A -#define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B -#define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C -#define BRW_SURFACEFORMAT_R64_FLOAT 0x08D -#define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E -#define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F -#define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090 -#define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091 -#define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092 -#define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 -#define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 -#define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095 -#define BRW_SURFACEFORMAT_R32G32_USCALED 0x096 -#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 -#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 -#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 -#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 -#define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 -#define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 -#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 -#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 -#define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 -#define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA -#define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB -#define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC -#define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD -#define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE -#define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF -#define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0 -#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 -#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 -#define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 -#define BRW_SURFACEFORMAT_R32_SINT 0x0D6 -#define BRW_SURFACEFORMAT_R32_UINT 0x0D7 -#define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8 -#define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 -#define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA -#define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF -#define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0 -#define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1 -#define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2 -#define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3 -#define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4 -#define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5 -#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 -#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA -#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB -#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC -#define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED -#define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE -#define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0 -#define BRW_SURFACEFORMAT_R32_UNORM 0x0F1 -#define BRW_SURFACEFORMAT_R32_SNORM 0x0F2 -#define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 -#define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 -#define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 -#define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6 -#define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7 -#define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8 -#define BRW_SURFACEFORMAT_R32_USCALED 0x0F9 -#define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100 -#define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 -#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 -#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 -#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 -#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 -#define BRW_SURFACEFORMAT_R8G8_UNORM 0x106 -#define BRW_SURFACEFORMAT_R8G8_SNORM 0x107 -#define BRW_SURFACEFORMAT_R8G8_SINT 0x108 -#define BRW_SURFACEFORMAT_R8G8_UINT 0x109 -#define BRW_SURFACEFORMAT_R16_UNORM 0x10A -#define BRW_SURFACEFORMAT_R16_SNORM 0x10B -#define BRW_SURFACEFORMAT_R16_SINT 0x10C -#define BRW_SURFACEFORMAT_R16_UINT 0x10D -#define BRW_SURFACEFORMAT_R16_FLOAT 0x10E -#define BRW_SURFACEFORMAT_I16_UNORM 0x111 -#define BRW_SURFACEFORMAT_L16_UNORM 0x112 -#define BRW_SURFACEFORMAT_A16_UNORM 0x113 -#define BRW_SURFACEFORMAT_L8A8_UNORM 0x114 -#define BRW_SURFACEFORMAT_I16_FLOAT 0x115 -#define BRW_SURFACEFORMAT_L16_FLOAT 0x116 -#define BRW_SURFACEFORMAT_A16_FLOAT 0x117 -#define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 -#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A -#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B -#define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C -#define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D -#define BRW_SURFACEFORMAT_R16_SSCALED 0x11E -#define BRW_SURFACEFORMAT_R16_USCALED 0x11F -#define BRW_SURFACEFORMAT_R8_UNORM 0x140 -#define BRW_SURFACEFORMAT_R8_SNORM 0x141 -#define BRW_SURFACEFORMAT_R8_SINT 0x142 -#define BRW_SURFACEFORMAT_R8_UINT 0x143 -#define BRW_SURFACEFORMAT_A8_UNORM 0x144 -#define BRW_SURFACEFORMAT_I8_UNORM 0x145 -#define BRW_SURFACEFORMAT_L8_UNORM 0x146 -#define BRW_SURFACEFORMAT_P4A4_UNORM 0x147 -#define BRW_SURFACEFORMAT_A4P4_UNORM 0x148 -#define BRW_SURFACEFORMAT_R8_SSCALED 0x149 -#define BRW_SURFACEFORMAT_R8_USCALED 0x14A -#define BRW_SURFACEFORMAT_R1_UINT 0x181 -#define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182 -#define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 -#define BRW_SURFACEFORMAT_BC1_UNORM 0x186 -#define BRW_SURFACEFORMAT_BC2_UNORM 0x187 -#define BRW_SURFACEFORMAT_BC3_UNORM 0x188 -#define BRW_SURFACEFORMAT_BC4_UNORM 0x189 -#define BRW_SURFACEFORMAT_BC5_UNORM 0x18A -#define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B -#define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C -#define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D -#define BRW_SURFACEFORMAT_MONO8 0x18E -#define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F -#define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190 -#define BRW_SURFACEFORMAT_DXT1_RGB 0x191 -#define BRW_SURFACEFORMAT_FXT1 0x192 -#define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193 -#define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194 -#define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195 -#define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196 -#define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 -#define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198 -#define BRW_SURFACEFORMAT_BC4_SNORM 0x199 -#define BRW_SURFACEFORMAT_BC5_SNORM 0x19A -#define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C -#define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D -#define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E -#define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F - -#define BRW_SURFACERETURNFORMAT_FLOAT32 0 -#define BRW_SURFACERETURNFORMAT_S1 1 - -#define BRW_SURFACE_1D 0 -#define BRW_SURFACE_2D 1 -#define BRW_SURFACE_3D 2 -#define BRW_SURFACE_CUBE 3 -#define BRW_SURFACE_BUFFER 4 -#define BRW_SURFACE_NULL 7 - -#define BRW_TEXCOORDMODE_WRAP 0 -#define BRW_TEXCOORDMODE_MIRROR 1 -#define BRW_TEXCOORDMODE_CLAMP 2 -#define BRW_TEXCOORDMODE_CUBE 3 -#define BRW_TEXCOORDMODE_CLAMP_BORDER 4 -#define BRW_TEXCOORDMODE_MIRROR_ONCE 5 - -#define BRW_THREAD_PRIORITY_NORMAL 0 -#define BRW_THREAD_PRIORITY_HIGH 1 - -#define BRW_TILEWALK_XMAJOR 0 -#define BRW_TILEWALK_YMAJOR 1 - -#define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0 -#define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1 - -#define BRW_VERTEXBUFFER_ACCESS_VERTEXDATA 0 -#define BRW_VERTEXBUFFER_ACCESS_INSTANCEDATA 1 - -#define BRW_VFCOMPONENT_NOSTORE 0 -#define BRW_VFCOMPONENT_STORE_SRC 1 -#define BRW_VFCOMPONENT_STORE_0 2 -#define BRW_VFCOMPONENT_STORE_1_FLT 3 -#define BRW_VFCOMPONENT_STORE_1_INT 4 -#define BRW_VFCOMPONENT_STORE_VID 5 -#define BRW_VFCOMPONENT_STORE_IID 6 -#define BRW_VFCOMPONENT_STORE_PID 7 - - - -/* Execution Unit (EU) defines - */ - -#define BRW_ALIGN_1 0 -#define BRW_ALIGN_16 1 - -#define BRW_ADDRESS_DIRECT 0 -#define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1 - -#define BRW_CHANNEL_X 0 -#define BRW_CHANNEL_Y 1 -#define BRW_CHANNEL_Z 2 -#define BRW_CHANNEL_W 3 - -#define BRW_COMPRESSION_NONE 0 -#define BRW_COMPRESSION_2NDHALF 1 -#define BRW_COMPRESSION_COMPRESSED 2 - -#define BRW_CONDITIONAL_NONE 0 -#define BRW_CONDITIONAL_Z 1 -#define BRW_CONDITIONAL_NZ 2 -#define BRW_CONDITIONAL_EQ 1 /* Z */ -#define BRW_CONDITIONAL_NEQ 2 /* NZ */ -#define BRW_CONDITIONAL_G 3 -#define BRW_CONDITIONAL_GE 4 -#define BRW_CONDITIONAL_L 5 -#define BRW_CONDITIONAL_LE 6 -#define BRW_CONDITIONAL_C 7 -#define BRW_CONDITIONAL_R 7 /* round increment */ -#define BRW_CONDITIONAL_O 8 /* overflow */ -#define BRW_CONDITIONAL_U 9 /* unordered */ - -#define BRW_DEBUG_NONE 0 -#define BRW_DEBUG_BREAKPOINT 1 - -#define BRW_DEPENDENCY_NORMAL 0 -#define BRW_DEPENDENCY_NOTCLEARED 1 -#define BRW_DEPENDENCY_NOTCHECKED 2 -#define BRW_DEPENDENCY_DISABLE 3 - -#define BRW_EXECUTE_1 0 -#define BRW_EXECUTE_2 1 -#define BRW_EXECUTE_4 2 -#define BRW_EXECUTE_8 3 -#define BRW_EXECUTE_16 4 -#define BRW_EXECUTE_32 5 - -#define BRW_HORIZONTAL_STRIDE_0 0 -#define BRW_HORIZONTAL_STRIDE_1 1 -#define BRW_HORIZONTAL_STRIDE_2 2 -#define BRW_HORIZONTAL_STRIDE_4 3 - -#define BRW_INSTRUCTION_NORMAL 0 -#define BRW_INSTRUCTION_SATURATE 1 - -#define BRW_MASK_ENABLE 0 -#define BRW_MASK_DISABLE 1 - -#define BRW_ACCWRCTRL_NONE 0 -#define BRW_ACCWRCTRL_ACCWRCTRL 1 - -#define BRW_OPCODE_MOV 1 -#define BRW_OPCODE_SEL 2 -#define BRW_OPCODE_NOT 4 -#define BRW_OPCODE_AND 5 -#define BRW_OPCODE_OR 6 -#define BRW_OPCODE_XOR 7 -#define BRW_OPCODE_SHR 8 -#define BRW_OPCODE_SHL 9 -#define BRW_OPCODE_RSR 10 -#define BRW_OPCODE_RSL 11 -#define BRW_OPCODE_ASR 12 -#define BRW_OPCODE_CMP 16 -#define BRW_OPCODE_CMPN 17 -#define BRW_OPCODE_F32TO16 19 -#define BRW_OPCODE_F16TO32 20 -#define BRW_OPCODE_BFREV 23 -#define BRW_OPCODE_BFE 24 -#define BRW_OPCODE_BFI1 25 -#define BRW_OPCODE_BFI2 26 -#define BRW_OPCODE_JMPI 32 -#define BRW_OPCODE_BRD 33 -#define BRW_OPCODE_IF 34 -#define BRW_OPCODE_BRC 35 -#define BRW_OPCODE_IFF 35 -#define BRW_OPCODE_ELSE 36 -#define BRW_OPCODE_ENDIF 37 -#define BRW_OPCODE_DO 38 -#define BRW_OPCODE_WHILE 39 -#define BRW_OPCODE_BREAK 40 -#define BRW_OPCODE_CONTINUE 41 -#define BRW_OPCODE_HALT 42 -#define BRW_OPCODE_MSAVE 44 -#define BRW_OPCODE_CALL 44 -#define BRW_OPCODE_MRESTORE 45 -#define BRW_OPCODE_RET 45 -#define BRW_OPCODE_PUSH 46 -#define BRW_OPCODE_POP 47 -#define BRW_OPCODE_WAIT 48 -#define BRW_OPCODE_SEND 49 -#define BRW_OPCODE_SENDC 50 -#define BRW_OPCODE_MATH 56 -#define BRW_OPCODE_ADD 64 -#define BRW_OPCODE_MUL 65 -#define BRW_OPCODE_AVG 66 -#define BRW_OPCODE_FRC 67 -#define BRW_OPCODE_RNDU 68 -#define BRW_OPCODE_RNDD 69 -#define BRW_OPCODE_RNDE 70 -#define BRW_OPCODE_RNDZ 71 -#define BRW_OPCODE_MAC 72 -#define BRW_OPCODE_MACH 73 -#define BRW_OPCODE_LZD 74 -#define BRW_OPCODE_FBH 75 -#define BRW_OPCODE_FBL 76 -#define BRW_OPCODE_CBIT 77 -#define BRW_OPCODE_ADDC 78 -#define BRW_OPCODE_SUBB 79 -#define BRW_OPCODE_SAD2 80 -#define BRW_OPCODE_SADA2 81 -#define BRW_OPCODE_DP4 84 -#define BRW_OPCODE_DPH 85 -#define BRW_OPCODE_DP3 86 -#define BRW_OPCODE_DP2 87 -#define BRW_OPCODE_DPA2 88 -#define BRW_OPCODE_LINE 89 -#define BRW_OPCODE_PLN 90 -#define BRW_OPCODE_MAD 91 -#define BRW_OPCODE_LRP 92 -#define BRW_OPCODE_NOP 126 - -#define BRW_PREDICATE_NONE 0 -#define BRW_PREDICATE_NORMAL 1 -#define BRW_PREDICATE_ALIGN1_ANYV 2 -#define BRW_PREDICATE_ALIGN1_ALLV 3 -#define BRW_PREDICATE_ALIGN1_ANY2H 4 -#define BRW_PREDICATE_ALIGN1_ALL2H 5 -#define BRW_PREDICATE_ALIGN1_ANY4H 6 -#define BRW_PREDICATE_ALIGN1_ALL4H 7 -#define BRW_PREDICATE_ALIGN1_ANY8H 8 -#define BRW_PREDICATE_ALIGN1_ALL8H 9 -#define BRW_PREDICATE_ALIGN1_ANY16H 10 -#define BRW_PREDICATE_ALIGN1_ALL16H 11 -#define BRW_PREDICATE_ALIGN16_REPLICATE_X 2 -#define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3 -#define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4 -#define BRW_PREDICATE_ALIGN16_REPLICATE_W 5 -#define BRW_PREDICATE_ALIGN16_ANY4H 6 -#define BRW_PREDICATE_ALIGN16_ALL4H 7 - -#define BRW_ARCHITECTURE_REGISTER_FILE 0 -#define BRW_GENERAL_REGISTER_FILE 1 -#define BRW_MESSAGE_REGISTER_FILE 2 -#define BRW_IMMEDIATE_VALUE 3 - -#define BRW_REGISTER_TYPE_UD 0 -#define BRW_REGISTER_TYPE_D 1 -#define BRW_REGISTER_TYPE_UW 2 -#define BRW_REGISTER_TYPE_W 3 -#define BRW_REGISTER_TYPE_UB 4 -#define BRW_REGISTER_TYPE_B 5 -#define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ -#define BRW_REGISTER_TYPE_HF 6 -#define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ -#define BRW_REGISTER_TYPE_F 7 - -#define BRW_ARF_NULL 0x00 -#define BRW_ARF_ADDRESS 0x10 -#define BRW_ARF_ACCUMULATOR 0x20 -#define BRW_ARF_FLAG 0x30 -#define BRW_ARF_MASK 0x40 -#define BRW_ARF_MASK_STACK 0x50 -#define BRW_ARF_MASK_STACK_DEPTH 0x60 -#define BRW_ARF_STATE 0x70 -#define BRW_ARF_CONTROL 0x80 -#define BRW_ARF_NOTIFICATION_COUNT 0x90 -#define BRW_ARF_IP 0xA0 - -#define BRW_AMASK 0 -#define BRW_IMASK 1 -#define BRW_LMASK 2 -#define BRW_CMASK 3 - - - -#define BRW_THREAD_NORMAL 0 -#define BRW_THREAD_ATOMIC 1 -#define BRW_THREAD_SWITCH 2 - -#define BRW_VERTICAL_STRIDE_0 0 -#define BRW_VERTICAL_STRIDE_1 1 -#define BRW_VERTICAL_STRIDE_2 2 -#define BRW_VERTICAL_STRIDE_4 3 -#define BRW_VERTICAL_STRIDE_8 4 -#define BRW_VERTICAL_STRIDE_16 5 -#define BRW_VERTICAL_STRIDE_32 6 -#define BRW_VERTICAL_STRIDE_64 7 -#define BRW_VERTICAL_STRIDE_128 8 -#define BRW_VERTICAL_STRIDE_256 9 -#define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF - -#define BRW_WIDTH_1 0 -#define BRW_WIDTH_2 1 -#define BRW_WIDTH_4 2 -#define BRW_WIDTH_8 3 -#define BRW_WIDTH_16 4 - -#define BRW_STATELESS_BUFFER_BOUNDARY_1K 0 -#define BRW_STATELESS_BUFFER_BOUNDARY_2K 1 -#define BRW_STATELESS_BUFFER_BOUNDARY_4K 2 -#define BRW_STATELESS_BUFFER_BOUNDARY_8K 3 -#define BRW_STATELESS_BUFFER_BOUNDARY_16K 4 -#define BRW_STATELESS_BUFFER_BOUNDARY_32K 5 -#define BRW_STATELESS_BUFFER_BOUNDARY_64K 6 -#define BRW_STATELESS_BUFFER_BOUNDARY_128K 7 -#define BRW_STATELESS_BUFFER_BOUNDARY_256K 8 -#define BRW_STATELESS_BUFFER_BOUNDARY_512K 9 -#define BRW_STATELESS_BUFFER_BOUNDARY_1M 10 -#define BRW_STATELESS_BUFFER_BOUNDARY_2M 11 - -#define BRW_POLYGON_FACING_FRONT 0 -#define BRW_POLYGON_FACING_BACK 1 - -#define BRW_MESSAGE_TARGET_NULL 0 -#define BRW_MESSAGE_TARGET_MATH 1 -#define BRW_MESSAGE_TARGET_SAMPLER 2 -#define BRW_MESSAGE_TARGET_GATEWAY 3 -#define BRW_MESSAGE_TARGET_DATAPORT_READ 4 -#define BRW_MESSAGE_TARGET_DP_SC 4 /* data port sampler cache */ -#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5 -#define BRW_MESSAGE_TARGET_DP_RC 5 /* data port render cache */ -#define BRW_MESSAGE_TARGET_URB 6 -#define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7 -#define BRW_MESSAGE_TARGET_VME 8 -#define BRW_MESSAGE_TARGET_DP_CC 9 /* data port constant cache */ -#define BRW_MESSAGE_TARGET_DP_DC 10 /* data port data cache */ -#define BRW_MESSAGE_TARGET_CRE 0x0d /* check & refinement enginee */ - -#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 -#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 -#define BRW_SAMPLER_RETURN_FORMAT_SINT32 3 - -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 -#define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 -#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 -#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 -#define BRW_SAMPLER_MESSAGE_SIMD8_RESINFO 2 -#define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2 -#define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3 -#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 -#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 - -#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 -#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 -#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2 -#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3 -#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4 - -#define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 -#define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 - -#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 -#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 - -#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 -#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 -#define BRW_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2 -#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 - -#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0 -#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1 -#define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 - -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 -#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 - -#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 -#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 -#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2 -#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 -#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 -#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 -#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 - -#define BRW_MATH_FUNCTION_INV 1 -#define BRW_MATH_FUNCTION_LOG 2 -#define BRW_MATH_FUNCTION_EXP 3 -#define BRW_MATH_FUNCTION_SQRT 4 -#define BRW_MATH_FUNCTION_RSQ 5 -#define BRW_MATH_FUNCTION_SIN 6 /* was 7 */ -#define BRW_MATH_FUNCTION_COS 7 /* was 8 */ -#define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */ -#define BRW_MATH_FUNCTION_TAN 9 -#define BRW_MATH_FUNCTION_POW 10 -#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 -#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 -#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13 - -#define BRW_MATH_INTEGER_UNSIGNED 0 -#define BRW_MATH_INTEGER_SIGNED 1 - -#define BRW_MATH_PRECISION_FULL 0 -#define BRW_MATH_PRECISION_PARTIAL 1 - -#define BRW_MATH_SATURATE_NONE 0 -#define BRW_MATH_SATURATE_SATURATE 1 - -#define BRW_MATH_DATA_VECTOR 0 -#define BRW_MATH_DATA_SCALAR 1 - -#define BRW_URB_OPCODE_WRITE 0 - -#define BRW_URB_SWIZZLE_NONE 0 -#define BRW_URB_SWIZZLE_INTERLEAVE 1 -#define BRW_URB_SWIZZLE_TRANSPOSE 2 - -#define BRW_SCRATCH_SPACE_SIZE_1K 0 -#define BRW_SCRATCH_SPACE_SIZE_2K 1 -#define BRW_SCRATCH_SPACE_SIZE_4K 2 -#define BRW_SCRATCH_SPACE_SIZE_8K 3 -#define BRW_SCRATCH_SPACE_SIZE_16K 4 -#define BRW_SCRATCH_SPACE_SIZE_32K 5 -#define BRW_SCRATCH_SPACE_SIZE_64K 6 -#define BRW_SCRATCH_SPACE_SIZE_128K 7 -#define BRW_SCRATCH_SPACE_SIZE_256K 8 -#define BRW_SCRATCH_SPACE_SIZE_512K 9 -#define BRW_SCRATCH_SPACE_SIZE_1M 10 -#define BRW_SCRATCH_SPACE_SIZE_2M 11 - - - - -#define CMD_URB_FENCE 0x6000 -#define CMD_CONST_BUFFER_STATE 0x6001 -#define CMD_CONST_BUFFER 0x6002 - -#define CMD_STATE_BASE_ADDRESS 0x6101 -#define CMD_STATE_INSN_POINTER 0x6102 -#define CMD_PIPELINE_SELECT 0x6104 - -#define CMD_PIPELINED_STATE_POINTERS 0x7800 -#define CMD_BINDING_TABLE_PTRS 0x7801 -#define CMD_VERTEX_BUFFER 0x7808 -#define CMD_VERTEX_ELEMENT 0x7809 -#define CMD_INDEX_BUFFER 0x780a -#define CMD_VF_STATISTICS 0x780b - -#define CMD_DRAW_RECT 0x7900 -#define CMD_BLEND_CONSTANT_COLOR 0x7901 -#define CMD_CHROMA_KEY 0x7904 -#define CMD_DEPTH_BUFFER 0x7905 -#define CMD_POLY_STIPPLE_OFFSET 0x7906 -#define CMD_POLY_STIPPLE_PATTERN 0x7907 -#define CMD_LINE_STIPPLE_PATTERN 0x7908 -#define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7908 - -#define CMD_PIPE_CONTROL 0x7a00 - -#define CMD_3D_PRIM 0x7b00 - -#define CMD_MI_FLUSH 0x0200 - - -/* Various values from the R0 vertex header: - */ -#define R02_PRIM_END 0x1 -#define R02_PRIM_START 0x2 - -#define EX_DESC_SFID_MASK 0xF -#define EX_DESC_EOT_MASK 0x20 - -#endif diff --git a/assembler/src/brw_structs.h b/assembler/src/brw_structs.h deleted file mode 100644 index 3a3b1601..00000000 --- a/assembler/src/brw_structs.h +++ /dev/null @@ -1,1579 +0,0 @@ - /************************************************************************** - * - * Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - -#ifndef BRW_STRUCTS_H -#define BRW_STRUCTS_H - -/* Command packets: - */ -struct header -{ - GLuint length:16; - GLuint opcode:16; -} bits; - - -union header_union -{ - struct header bits; - GLuint dword; -}; - -struct brw_3d_control -{ - struct - { - GLuint length:8; - GLuint notify_enable:1; - GLuint pad:3; - GLuint wc_flush_enable:1; - GLuint depth_stall_enable:1; - GLuint operation:2; - GLuint opcode:16; - } header; - - struct - { - GLuint pad:2; - GLuint dest_addr_type:1; - GLuint dest_addr:29; - } dest; - - GLuint dword2; - GLuint dword3; -}; - - -struct brw_3d_primitive -{ - struct - { - GLuint length:8; - GLuint pad:2; - GLuint topology:5; - GLuint indexed:1; - GLuint opcode:16; - } header; - - GLuint verts_per_instance; - GLuint start_vert_location; - GLuint instance_count; - GLuint start_instance_location; - GLuint base_vert_location; -}; - -/* These seem to be passed around as function args, so it works out - * better to keep them as #defines: - */ -#define BRW_FLUSH_READ_CACHE 0x1 -#define BRW_FLUSH_STATE_CACHE 0x2 -#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 -#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 - -struct brw_mi_flush -{ - GLuint flags:4; - GLuint pad:12; - GLuint opcode:16; -}; - -struct brw_vf_statistics -{ - GLuint statistics_enable:1; - GLuint pad:15; - GLuint opcode:16; -}; - - - -struct brw_binding_table_pointers -{ - struct header header; - GLuint vs; - GLuint gs; - GLuint clp; - GLuint sf; - GLuint wm; -}; - - -struct brw_blend_constant_color -{ - struct header header; - GLfloat blend_constant_color[4]; -}; - - -struct brw_depthbuffer -{ - union header_union header; - - union { - struct { - GLuint pitch:18; - GLuint format:3; - GLuint pad:4; - GLuint depth_offset_disable:1; - GLuint tile_walk:1; - GLuint tiled_surface:1; - GLuint pad2:1; - GLuint surface_type:3; - } bits; - GLuint dword; - } dword1; - - GLuint dword2_base_addr; - - union { - struct { - GLuint pad:1; - GLuint mipmap_layout:1; - GLuint lod:4; - GLuint width:13; - GLuint height:13; - } bits; - GLuint dword; - } dword3; - - union { - struct { - GLuint pad:12; - GLuint min_array_element:9; - GLuint depth:11; - } bits; - GLuint dword; - } dword4; -}; - -struct brw_drawrect -{ - struct header header; - GLuint xmin:16; - GLuint ymin:16; - GLuint xmax:16; - GLuint ymax:16; - GLuint xorg:16; - GLuint yorg:16; -}; - - - - -struct brw_global_depth_offset_clamp -{ - struct header header; - GLfloat depth_offset_clamp; -}; - -struct brw_indexbuffer -{ - union { - struct - { - GLuint length:8; - GLuint index_format:2; - GLuint cut_index_enable:1; - GLuint pad:5; - GLuint opcode:16; - } bits; - GLuint dword; - - } header; - - GLuint buffer_start; - GLuint buffer_end; -}; - - -struct brw_line_stipple -{ - struct header header; - - struct - { - GLuint pattern:16; - GLuint pad:16; - } bits0; - - struct - { - GLuint repeat_count:9; - GLuint pad:7; - GLuint inverse_repeat_count:16; - } bits1; -}; - - -struct brw_pipelined_state_pointers -{ - struct header header; - - struct { - GLuint pad:5; - GLuint offset:27; - } vs; - - struct - { - GLuint enable:1; - GLuint pad:4; - GLuint offset:27; - } gs; - - struct - { - GLuint enable:1; - GLuint pad:4; - GLuint offset:27; - } clp; - - struct - { - GLuint pad:5; - GLuint offset:27; - } sf; - - struct - { - GLuint pad:5; - GLuint offset:27; - } wm; - - struct - { - GLuint pad:5; - GLuint offset:27; /* KW: check me! */ - } cc; -}; - - -struct brw_polygon_stipple_offset -{ - struct header header; - - struct { - GLuint y_offset:5; - GLuint pad:3; - GLuint x_offset:5; - GLuint pad0:19; - } bits0; -}; - - - -struct brw_polygon_stipple -{ - struct header header; - GLuint stipple[32]; -}; - - - -struct brw_pipeline_select -{ - struct - { - GLuint pipeline_select:1; - GLuint pad:15; - GLuint opcode:16; - } header; -}; - - -struct brw_pipe_control -{ - struct - { - GLuint length:8; - GLuint notify_enable:1; - GLuint pad:2; - GLuint instruction_state_cache_flush_enable:1; - GLuint write_cache_flush_enable:1; - GLuint depth_stall_enable:1; - GLuint post_sync_operation:2; - - GLuint opcode:16; - } header; - - struct - { - GLuint pad:2; - GLuint dest_addr_type:1; - GLuint dest_addr:29; - } bits1; - - GLuint data0; - GLuint data1; -}; - - -struct brw_urb_fence -{ - struct - { - GLuint length:8; - GLuint vs_realloc:1; - GLuint gs_realloc:1; - GLuint clp_realloc:1; - GLuint sf_realloc:1; - GLuint vfe_realloc:1; - GLuint cs_realloc:1; - GLuint pad:2; - GLuint opcode:16; - } header; - - struct - { - GLuint vs_fence:10; - GLuint gs_fence:10; - GLuint clp_fence:10; - GLuint pad:2; - } bits0; - - struct - { - GLuint sf_fence:10; - GLuint vf_fence:10; - GLuint cs_fence:10; - GLuint pad:2; - } bits1; -}; - -struct brw_constant_buffer_state /* previously brw_command_streamer */ -{ - struct header header; - - struct - { - GLuint nr_urb_entries:3; - GLuint pad:1; - GLuint urb_entry_size:5; - GLuint pad0:23; - } bits0; -}; - -struct brw_constant_buffer -{ - struct - { - GLuint length:8; - GLuint valid:1; - GLuint pad:7; - GLuint opcode:16; - } header; - - struct - { - GLuint buffer_length:6; - GLuint buffer_address:26; - } bits0; -}; - -struct brw_state_base_address -{ - struct header header; - - struct - { - GLuint modify_enable:1; - GLuint pad:4; - GLuint general_state_address:27; - } bits0; - - struct - { - GLuint modify_enable:1; - GLuint pad:4; - GLuint surface_state_address:27; - } bits1; - - struct - { - GLuint modify_enable:1; - GLuint pad:4; - GLuint indirect_object_state_address:27; - } bits2; - - struct - { - GLuint modify_enable:1; - GLuint pad:11; - GLuint general_state_upper_bound:20; - } bits3; - - struct - { - GLuint modify_enable:1; - GLuint pad:11; - GLuint indirect_object_state_upper_bound:20; - } bits4; -}; - -struct brw_state_prefetch -{ - struct header header; - - struct - { - GLuint prefetch_count:3; - GLuint pad:3; - GLuint prefetch_pointer:26; - } bits0; -}; - -struct brw_system_instruction_pointer -{ - struct header header; - - struct - { - GLuint pad:4; - GLuint system_instruction_pointer:28; - } bits0; -}; - - - - -/* State structs for the various fixed function units: - */ - - -struct thread0 -{ - GLuint pad0:1; - GLuint grf_reg_count:3; - GLuint pad1:2; - GLuint kernel_start_pointer:26; -}; - -struct thread1 -{ - GLuint ext_halt_exception_enable:1; - GLuint sw_exception_enable:1; - GLuint mask_stack_exception_enable:1; - GLuint timeout_exception_enable:1; - GLuint illegal_op_exception_enable:1; - GLuint pad0:3; - GLuint depth_coef_urb_read_offset:6; /* WM only */ - GLuint pad1:2; - GLuint floating_point_mode:1; - GLuint thread_priority:1; - GLuint binding_table_entry_count:8; - GLuint pad3:5; - GLuint single_program_flow:1; -}; - -struct thread2 -{ - GLuint per_thread_scratch_space:4; - GLuint pad0:6; - GLuint scratch_space_base_pointer:22; -}; - - -struct thread3 -{ - GLuint dispatch_grf_start_reg:4; - GLuint urb_entry_read_offset:6; - GLuint pad0:1; - GLuint urb_entry_read_length:6; - GLuint pad1:1; - GLuint const_urb_entry_read_offset:6; - GLuint pad2:1; - GLuint const_urb_entry_read_length:6; - GLuint pad3:1; -}; - - - -struct brw_clip_unit_state -{ - struct thread0 thread0; - struct thread1 thread1; - struct thread2 thread2; - struct thread3 thread3; - - struct - { - GLuint pad0:9; - GLuint gs_output_stats:1; /* not always */ - GLuint stats_enable:1; - GLuint nr_urb_entries:7; - GLuint pad1:1; - GLuint urb_entry_allocation_size:5; - GLuint pad2:1; - GLuint max_threads:6; /* may be less */ - GLuint pad3:1; - } thread4; - - struct - { - GLuint pad0:13; - GLuint clip_mode:3; - GLuint userclip_enable_flags:8; - GLuint userclip_must_clip:1; - GLuint pad1:1; - GLuint guard_band_enable:1; - GLuint viewport_z_clip_enable:1; - GLuint viewport_xy_clip_enable:1; - GLuint vertex_position_space:1; - GLuint api_mode:1; - GLuint pad2:1; - } clip5; - - struct - { - GLuint pad0:5; - GLuint clipper_viewport_state_ptr:27; - } clip6; - - - GLfloat viewport_xmin; - GLfloat viewport_xmax; - GLfloat viewport_ymin; - GLfloat viewport_ymax; -}; - - - -struct brw_cc_unit_state -{ - struct - { - GLuint pad0:3; - GLuint bf_stencil_pass_depth_pass_op:3; - GLuint bf_stencil_pass_depth_fail_op:3; - GLuint bf_stencil_fail_op:3; - GLuint bf_stencil_func:3; - GLuint bf_stencil_enable:1; - GLuint pad1:2; - GLuint stencil_write_enable:1; - GLuint stencil_pass_depth_pass_op:3; - GLuint stencil_pass_depth_fail_op:3; - GLuint stencil_fail_op:3; - GLuint stencil_func:3; - GLuint stencil_enable:1; - } cc0; - - - struct - { - GLuint bf_stencil_ref:8; - GLuint stencil_write_mask:8; - GLuint stencil_test_mask:8; - GLuint stencil_ref:8; - } cc1; - - - struct - { - GLuint logicop_enable:1; - GLuint pad0:10; - GLuint depth_write_enable:1; - GLuint depth_test_function:3; - GLuint depth_test:1; - GLuint bf_stencil_write_mask:8; - GLuint bf_stencil_test_mask:8; - } cc2; - - - struct - { - GLuint pad0:8; - GLuint alpha_test_func:3; - GLuint alpha_test:1; - GLuint blend_enable:1; - GLuint ia_blend_enable:1; - GLuint pad1:1; - GLuint alpha_test_format:1; - GLuint pad2:16; - } cc3; - - struct - { - GLuint pad0:5; - GLuint cc_viewport_state_offset:27; - } cc4; - - struct - { - GLuint pad0:2; - GLuint ia_dest_blend_factor:5; - GLuint ia_src_blend_factor:5; - GLuint ia_blend_function:3; - GLuint statistics_enable:1; - GLuint logicop_func:4; - GLuint pad1:11; - GLuint dither_enable:1; - } cc5; - - struct - { - GLuint clamp_post_alpha_blend:1; - GLuint clamp_pre_alpha_blend:1; - GLuint clamp_range:2; - GLuint pad0:11; - GLuint y_dither_offset:2; - GLuint x_dither_offset:2; - GLuint dest_blend_factor:5; - GLuint src_blend_factor:5; - GLuint blend_function:3; - } cc6; - - struct { - union { - GLfloat f; - GLubyte ub[4]; - } alpha_ref; - } cc7; -}; - - - -struct brw_sf_unit_state -{ - struct thread0 thread0; - struct thread1 thread1; - struct thread2 thread2; - struct thread3 thread3; - - struct - { - GLuint pad0:10; - GLuint stats_enable:1; - GLuint nr_urb_entries:7; - GLuint pad1:1; - GLuint urb_entry_allocation_size:5; - GLuint pad2:1; - GLuint max_threads:6; - GLuint pad3:1; - } thread4; - - struct - { - GLuint front_winding:1; - GLuint viewport_transform:1; - GLuint pad0:3; - GLuint sf_viewport_state_offset:27; - } sf5; - - struct - { - GLuint pad0:9; - GLuint dest_org_vbias:4; - GLuint dest_org_hbias:4; - GLuint scissor:1; - GLuint disable_2x2_trifilter:1; - GLuint disable_zero_pix_trifilter:1; - GLuint point_rast_rule:2; - GLuint line_endcap_aa_region_width:2; - GLuint line_width:4; - GLuint fast_scissor_disable:1; - GLuint cull_mode:2; - GLuint aa_enable:1; - } sf6; - - struct - { - GLuint point_size:11; - GLuint use_point_size_state:1; - GLuint subpixel_precision:1; - GLuint sprite_point:1; - GLuint pad0:11; - GLuint trifan_pv:2; - GLuint linestrip_pv:2; - GLuint tristrip_pv:2; - GLuint line_last_pixel_enable:1; - } sf7; - -}; - - -struct brw_gs_unit_state -{ - struct thread0 thread0; - struct thread1 thread1; - struct thread2 thread2; - struct thread3 thread3; - - struct - { - GLuint pad0:10; - GLuint stats_enable:1; - GLuint nr_urb_entries:7; - GLuint pad1:1; - GLuint urb_entry_allocation_size:5; - GLuint pad2:1; - GLuint max_threads:1; - GLuint pad3:6; - } thread4; - - struct - { - GLuint sampler_count:3; - GLuint pad0:2; - GLuint sampler_state_pointer:27; - } gs5; - - - struct - { - GLuint max_vp_index:4; - GLuint pad0:26; - GLuint reorder_enable:1; - GLuint pad1:1; - } gs6; -}; - - -struct brw_vs_unit_state -{ - struct thread0 thread0; - struct thread1 thread1; - struct thread2 thread2; - struct thread3 thread3; - - struct - { - GLuint pad0:10; - GLuint stats_enable:1; - GLuint nr_urb_entries:7; - GLuint pad1:1; - GLuint urb_entry_allocation_size:5; - GLuint pad2:1; - GLuint max_threads:4; - GLuint pad3:3; - } thread4; - - struct - { - GLuint sampler_count:3; - GLuint pad0:2; - GLuint sampler_state_pointer:27; - } vs5; - - struct - { - GLuint vs_enable:1; - GLuint vert_cache_disable:1; - GLuint pad0:30; - } vs6; -}; - - -struct brw_wm_unit_state -{ - struct thread0 thread0; - struct thread1 thread1; - struct thread2 thread2; - struct thread3 thread3; - - struct { - GLuint stats_enable:1; - GLuint pad0:1; - GLuint sampler_count:3; - GLuint sampler_state_pointer:27; - } wm4; - - struct - { - GLuint enable_8_pix:1; - GLuint enable_16_pix:1; - GLuint enable_32_pix:1; - GLuint pad0:7; - GLuint legacy_global_depth_bias:1; - GLuint line_stipple:1; - GLuint depth_offset:1; - GLuint polygon_stipple:1; - GLuint line_aa_region_width:2; - GLuint line_endcap_aa_region_width:2; - GLuint early_depth_test:1; - GLuint thread_dispatch_enable:1; - GLuint program_uses_depth:1; - GLuint program_computes_depth:1; - GLuint program_uses_killpixel:1; - GLuint legacy_line_rast: 1; - GLuint pad1:1; - GLuint max_threads:6; - GLuint pad2:1; - } wm5; - - GLfloat global_depth_offset_constant; - GLfloat global_depth_offset_scale; -}; - -struct brw_sampler_default_color { - GLfloat color[4]; -}; - -struct brw_sampler_state -{ - - struct - { - GLuint shadow_function:3; - GLuint lod_bias:11; - GLuint min_filter:3; - GLuint mag_filter:3; - GLuint mip_filter:2; - GLuint base_level:5; - GLuint pad:1; - GLuint lod_preclamp:1; - GLuint default_color_mode:1; - GLuint pad0:1; - GLuint disable:1; - } ss0; - - struct - { - GLuint r_wrap_mode:3; - GLuint t_wrap_mode:3; - GLuint s_wrap_mode:3; - GLuint pad:3; - GLuint max_lod:10; - GLuint min_lod:10; - } ss1; - - - struct - { - GLuint pad:5; - GLuint default_color_pointer:27; - } ss2; - - struct - { - GLuint pad:19; - GLuint max_aniso:3; - GLuint chroma_key_mode:1; - GLuint chroma_key_index:2; - GLuint chroma_key_enable:1; - GLuint monochrome_filter_width:3; - GLuint monochrome_filter_height:3; - } ss3; -}; - - -struct brw_clipper_viewport -{ - GLfloat xmin; - GLfloat xmax; - GLfloat ymin; - GLfloat ymax; -}; - -struct brw_cc_viewport -{ - GLfloat min_depth; - GLfloat max_depth; -}; - -struct brw_sf_viewport -{ - struct { - GLfloat m00; - GLfloat m11; - GLfloat m22; - GLfloat m30; - GLfloat m31; - GLfloat m32; - } viewport; - - struct { - GLshort xmin; - GLshort ymin; - GLshort xmax; - GLshort ymax; - } scissor; -}; - -/* Documented in the subsystem/shared-functions/sampler chapter... - */ -struct brw_surface_state -{ - struct { - GLuint cube_pos_z:1; - GLuint cube_neg_z:1; - GLuint cube_pos_y:1; - GLuint cube_neg_y:1; - GLuint cube_pos_x:1; - GLuint cube_neg_x:1; - GLuint pad:4; - GLuint mipmap_layout_mode:1; - GLuint vert_line_stride_ofs:1; - GLuint vert_line_stride:1; - GLuint color_blend:1; - GLuint writedisable_blue:1; - GLuint writedisable_green:1; - GLuint writedisable_red:1; - GLuint writedisable_alpha:1; - GLuint surface_format:9; - GLuint data_return_format:1; - GLuint pad0:1; - GLuint surface_type:3; - } ss0; - - struct { - GLuint base_addr; - } ss1; - - struct { - GLuint pad:2; - GLuint mip_count:4; - GLuint width:13; - GLuint height:13; - } ss2; - - struct { - GLuint tile_walk:1; - GLuint tiled_surface:1; - GLuint pad:1; - GLuint pitch:18; - GLuint depth:11; - } ss3; - - struct { - GLuint pad:19; - GLuint min_array_elt:9; - GLuint min_lod:4; - } ss4; -}; - - - -struct brw_vertex_buffer_state -{ - struct { - GLuint pitch:11; - GLuint pad:15; - GLuint access_type:1; - GLuint vb_index:5; - } vb0; - - GLuint start_addr; - GLuint max_index; -#if 1 - GLuint instance_data_step_rate; /* not included for sequential/random vertices? */ -#endif -}; - -#define BRW_VBP_MAX 17 - -struct brw_vb_array_state { - struct header header; - struct brw_vertex_buffer_state vb[BRW_VBP_MAX]; -}; - - -struct brw_vertex_element_state -{ - struct - { - GLuint src_offset:11; - GLuint pad:5; - GLuint src_format:9; - GLuint pad0:1; - GLuint valid:1; - GLuint vertex_buffer_index:5; - } ve0; - - struct - { - GLuint dst_offset:8; - GLuint pad:8; - GLuint vfcomponent3:4; - GLuint vfcomponent2:4; - GLuint vfcomponent1:4; - GLuint vfcomponent0:4; - } ve1; -}; - -#define BRW_VEP_MAX 18 - -struct brw_vertex_element_packet { - struct header header; - struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */ -}; - - -struct brw_urb_immediate { - GLuint opcode:4; - GLuint offset:6; - GLuint swizzle_control:2; - GLuint pad:1; - GLuint allocate:1; - GLuint used:1; - GLuint complete:1; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; -}; - -/* Instruction format for the execution units: - */ - -struct brw_instruction -{ - struct - { - GLuint opcode:7; /* 0x0000007f */ - GLuint pad:1; /* 0x00000080 */ /* reserved for Opcode */ - GLuint access_mode:1; /* 0x00000100 */ - GLuint mask_control:1; /* 0x00000200 */ - GLuint dependency_control:2; /* 0x00000c00 */ - GLuint compression_control:2; /* 0x00003000 */ - GLuint thread_control:2; /* 0x0000c000 */ - GLuint predicate_control:4; /* 0x000f0000 */ - GLuint predicate_inverse:1; /* 0x00100000 */ - GLuint execution_size:3; /* 0x00e00000 */ - GLuint sfid_destreg__conditionalmod:4; /* sfid - send on GEN6+, destreg - send on Prev GEN6, conditionalmod - others */ - GLuint acc_wr_control:1; /* 0x10000000 */ - GLuint pad0:1; /* 0x20000000 */ - GLuint debug_control:1; /* 0x40000000 */ - GLuint saturate:1; /* 0x80000000 */ - } header; - - union { - struct - { - GLuint dest_reg_file:2; /* 0x00000003 */ - GLuint dest_reg_type:3; /* 0x0000001c */ - GLuint src0_reg_file:2; /* 0x00000060 */ - GLuint src0_reg_type:3; /* 0x00000380 */ - GLuint src1_reg_file:2; /* 0x00000c00 */ - GLuint src1_reg_type:3; /* 0x00007000 */ - GLuint pad:1; /* 0x00008000 */ - GLuint dest_subreg_nr:5; /* 0x001f0000 */ - GLuint dest_reg_nr:8; /* 0x1f700000 */ - GLuint dest_horiz_stride:2; /* 0x60000000 */ - GLuint dest_address_mode:1; /* 0x80000000 */ - } da1; /* direct align1 */ - - struct - { - GLuint dest_reg_file:2; - GLuint dest_reg_type:3; - GLuint src0_reg_file:2; - GLuint src0_reg_type:3; - GLuint src1_reg_file:2; /* 0x00000c00 */ - GLuint src1_reg_type:3; /* 0x00007000 */ - GLuint pad:1; - GLint dest_indirect_offset:10; /* offset against the deref'd address reg */ - GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */ - GLuint dest_horiz_stride:2; - GLuint dest_address_mode:1; - } ia1; /* indirect align1 */ - - struct - { - GLuint dest_reg_file:2; - GLuint dest_reg_type:3; - GLuint src0_reg_file:2; - GLuint src0_reg_type:3; - GLuint src1_reg_file:2; - GLuint src1_reg_type:3; - GLuint pad0:1; - GLuint dest_writemask:4; - GLuint dest_subreg_nr:1; - GLuint dest_reg_nr:8; - GLuint dest_horiz_stride:2; - GLuint dest_address_mode:1; - } da16; /* direct align16 */ - - struct - { - GLuint dest_reg_file:2; - GLuint dest_reg_type:3; - GLuint src0_reg_file:2; - GLuint src0_reg_type:3; - GLuint pad0:6; - GLuint dest_writemask:4; - GLint dest_indirect_offset:6; - GLuint dest_subreg_nr:3; - GLuint dest_horiz_stride:2; - GLuint dest_address_mode:1; - } ia16; /* indirect align16 */ - - struct - { - GLuint dest_reg_file:1; /* used in Gen6, deleted in Gen7 */ - GLuint flag_subreg_nr:1; - GLuint flag_reg_nr:1; /* not in Gen6. Add in Gen7 */ - GLuint pad1:1; /* reserved */ - GLuint src0_modifier:2; - GLuint src1_modifier:2; - GLuint src2_modifier:2; - GLuint src_reg_type:2; - GLuint dest_reg_type:2; - GLuint pad2:1; /* reserved */ - GLuint nib_ctrl:1; - GLuint pad3:1; /* reserved */ - GLuint dest_writemask:4; - GLuint dest_subreg_nr:3; - GLuint dest_reg_nr:8; - } three_src_gen6; /* Three-source-operator instructions for Gen6+ */ - - struct - { - GLuint pad:16; - GLint JIP:16; - } branch; /* conditional branch JIP for Gen6 only */ - } bits1; - - - union { - struct - { - GLuint src0_subreg_nr:5; /* 0x0000001f */ - GLuint src0_reg_nr:8; /* 0x00001fe0 */ - GLuint src0_abs:1; /* 0x00002000 */ - GLuint src0_negate:1; /* 0x00004000 */ - GLuint src0_address_mode:1; /* 0x00008000 */ - GLuint src0_horiz_stride:2; /* 0x00030000 */ - GLuint src0_width:3; /* 0x001c0000 */ - GLuint src0_vert_stride:4; /* 0x01e00000 */ - GLuint flag_subreg_nr:1; /* 0x02000000 */ - GLuint flag_reg_nr:1; /* 0x04000000 */ - GLuint pad:5; /* 0xf8000000 */ - } da1; /* direct align1 */ - - struct - { - GLint src0_indirect_offset:10; - GLuint src0_subreg_nr:3; - GLuint src0_abs:1; - GLuint src0_negate:1; - GLuint src0_address_mode:1; - GLuint src0_horiz_stride:2; - GLuint src0_width:3; - GLuint src0_vert_stride:4; - GLuint flag_subreg_nr:1; - GLuint flag_reg_nr:1; - GLuint pad:5; - } ia1; /* indirect align1 */ - - struct - { - GLuint src0_swz_x:2; - GLuint src0_swz_y:2; - GLuint src0_subreg_nr:1; - GLuint src0_reg_nr:8; - GLuint src0_abs:1; - GLuint src0_negate:1; - GLuint src0_address_mode:1; - GLuint src0_swz_z:2; - GLuint src0_swz_w:2; - GLuint pad0:1; - GLuint src0_vert_stride:4; - GLuint flag_subreg_nr:1; - GLuint flag_reg_nr:1; - GLuint pad1:5; - } da16; /* direct align16 */ - - struct - { - GLuint src0_swz_x:2; - GLuint src0_swz_y:2; - GLint src0_indirect_offset:6; - GLuint src0_subreg_nr:3; - GLuint src0_abs:1; - GLuint src0_negate:1; - GLuint src0_address_mode:1; - GLuint src0_swz_z:2; - GLuint src0_swz_w:2; - GLuint pad0:1; - GLuint src0_vert_stride:4; - GLuint flag_subreg_nr:1; - GLuint flag_reg_nr:1; - GLuint pad1:5; - } ia16; /* indirect align16 */ - - struct - { - GLuint src0_rep_ctrl:1; - GLuint src0_swizzle:8; - GLuint src0_subreg_nr:3; - GLuint src0_reg_nr:8; - GLuint pad0:1; /* reserved */ - GLuint src1_rep_ctrl:1; - GLuint src1_swizzle:8; - GLuint src1_subreg_nr_low:2; /* src1_subreg_nr spans on two DWORDs */ - } three_src_gen6; /* Three-source-operator instructions for Gen6+ */ - - struct - { - GLuint pad:26; - GLuint end_of_thread:1; - GLuint pad1:1; - GLuint sfid:4; - } send_gen5; /* for GEN5 only */ - struct - { - GLuint pad:26; - GLuint msg_ext:6; - } msg_ext; - } bits2; - - union - { - struct - { - GLuint src1_subreg_nr:5; - GLuint src1_reg_nr:8; - GLuint src1_abs:1; - GLuint src1_negate:1; - GLuint src1_address_mode:1; - GLuint src1_horiz_stride:2; - GLuint src1_width:3; - GLuint src1_vert_stride:4; - GLuint pad0:7; - } da1; /* direct align1 */ - - struct - { - GLuint src1_swz_x:2; - GLuint src1_swz_y:2; - GLuint src1_subreg_nr:1; - GLuint src1_reg_nr:8; - GLuint src1_abs:1; - GLuint src1_negate:1; - GLuint src1_address_mode:1; - GLuint src1_swz_z:2; - GLuint src1_swz_w:2; - GLuint pad1:1; - GLuint src1_vert_stride:4; - GLuint pad2:7; - } da16; /* direct align16 */ - - struct - { - GLint src1_indirect_offset:10; - GLuint src1_subreg_nr:3; - GLuint src1_abs:1; - GLuint src1_negate:1; - GLuint src1_address_mode:1; - GLuint src1_horiz_stride:2; - GLuint src1_width:3; - GLuint src1_vert_stride:4; - GLuint pad1:7; - } ia1; /* indirect align1 */ - - struct - { - GLuint src1_swz_x:2; - GLuint src1_swz_y:2; - GLint src1_indirect_offset:6; - GLuint src1_subreg_nr:3; - GLuint src1_abs:1; - GLuint src1_negate:1; - GLuint src1_address_mode:1; - GLuint src1_swz_z:2; - GLuint src1_swz_w:2; - GLuint pad1:1; - GLuint src1_vert_stride:4; - GLuint pad2:7; - } ia16; /* indirect align16 */ - - struct - { - GLuint src1_subreg_nr_high:1; /* src1_subreg_nr spans on two DWORDs */ - GLuint src1_reg_nr:8; - GLuint pad0:1; /* reserved */ - GLuint src2_rep_ctrl:1; - GLuint src2_swizzle:8; - GLuint src2_subreg_nr:3; - GLuint src2_reg_nr:8; - GLuint pad1:2; /* reserved */ - } three_src_gen6; /* Three-source-operator instructions for Gen6+ */ - - struct - { - GLint JIP:16; /* Gen7 bspec: both the JIP and UIP are signed 16-bit numbers */ - GLint UIP:16; - } branch_2_offset; /* for Gen6, Gen7 2-offsets branch; for Gen7 1-offset branch */ - - GLint JIP; /* used by Gen6 CALL instructions; Gen7 JMPI */ - - struct { - GLuint function:4; - GLuint int_type:1; - GLuint precision:1; - GLuint saturate:1; - GLuint data_type:1; - GLuint pad0:8; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } math; - - struct { - GLuint binding_table_index:8; - GLuint sampler:4; - GLuint return_format:2; - GLuint msg_type:2; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } sampler; - - struct brw_urb_immediate urb; - - struct { - GLuint binding_table_index:8; - GLuint msg_control:4; - GLuint msg_type:2; - GLuint target_cache:2; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } dp_read; - - struct { - GLuint binding_table_index:8; - GLuint msg_control:3; - GLuint pixel_scoreboard_clear:1; - GLuint msg_type:3; - GLuint send_commit_msg:1; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } dp_write; - - struct { - GLuint opcode:1; - GLuint requester_type:1; - GLuint pad:2; - GLuint resource_select:1; - GLuint pad1:11; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad2:3; - GLuint end_of_thread:1; - } thread_spawner; - - struct { - GLuint pad:16; - GLuint response_length:4; - GLuint msg_length:4; - GLuint msg_target:4; - GLuint pad1:3; - GLuint end_of_thread:1; - } generic; - - struct { - GLuint function:4; - GLuint int_type:1; - GLuint precision:1; - GLuint saturate:1; - GLuint data_type:1; - GLuint snapshot:1; - GLuint pad0:10; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } math_gen5; - - struct { - GLuint opcode:4; - GLuint offset:6; - GLuint swizzle_control:2; - GLuint pad:1; - GLuint allocate:1; - GLuint used:1; - GLuint complete:1; - GLuint pad0:3; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } urb_gen5; - - struct { - GLuint binding_table_index:8; - GLuint sampler:4; - GLuint msg_type:4; - GLuint simd_mode:2; - GLuint pad0:1; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } sampler_gen5; - - struct { - GLuint binding_table_index:8; - GLuint sampler:4; - GLuint msg_type:5; - GLuint simd_mode:2; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } sampler_gen7; - - struct { - GLuint binding_table_index:8; - GLuint msg_control:4; - GLuint msg_type:2; - GLuint target_cache:2; - GLuint pad0:3; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } dp_read_gen5; - - struct { - GLuint binding_table_index:8; - GLuint msg_control:5; - GLuint msg_type:3; - GLuint pad0:3; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } dp_read_gen6; - - struct { - GLuint binding_table_index:8; - GLuint msg_control:3; - GLuint pixel_scoreboard_clear:1; - GLuint msg_type:3; - GLuint send_commit_msg:1; - GLuint pad0:3; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } dp_write_gen5; - - struct { - GLuint binding_table_index:8; - GLuint msg_control:5; - GLuint msg_type:4; - GLuint send_commit_msg:1; - GLuint pad0:1; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } dp_write_gen6; - - struct { - GLuint binding_table_index:8; - GLuint msg_control:5; - GLuint msg_type:4; - GLuint send_commit_msg:1; /* ignore on read message */ - GLuint pad0:1; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } dp_gen6; - - struct { - GLuint binding_table_index:8; - GLuint msg_control:6; - GLuint msg_type:4; - GLuint category:1; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } dp_gen7; - - struct { - GLuint opcode:1; - GLuint requester_type:1; - GLuint pad0:2; - GLuint resource_select:1; - GLuint pad1:14; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad2:2; - GLuint end_of_thread:1; - } thread_spawner_gen5; - - struct { - GLuint binding_table_index:8; - GLuint search_path_index:3; - GLuint lut_subindex:2; - GLuint message_type:2; - GLuint pad0:4; - GLuint header_present:1; - } vme_gen6; - struct { - GLuint binding_table_index:8; - GLuint pad0:5; - GLuint message_type:2; - GLuint pad1:4; - GLuint header_present:1; - } cre_gen75; - struct { - GLuint pad:19; - GLuint header_present:1; - GLuint response_length:5; - GLuint msg_length:4; - GLuint pad1:2; - GLuint end_of_thread:1; - } generic_gen5; - - GLuint ud; - GLint id; - GLfloat fd; - } bits3; - - char *first_reloc_target, *second_reloc_target; // first for JIP, second for UIP - GLint first_reloc_offset, second_reloc_offset; // in number of instructions -}; - - -#endif diff --git a/assembler/src/disasm-main.c b/assembler/src/disasm-main.c deleted file mode 100644 index 5cc1e7d1..00000000 --- a/assembler/src/disasm-main.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright © 2008 Keith Packard - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#include -#include -#include -#include -#include - -#include "gen4asm.h" - -static const struct option longopts[] = { - { NULL, 0, NULL, 0 } -}; - -static struct brw_program * -read_program (FILE *input) -{ - uint32_t inst[4]; - struct brw_program *program; - struct brw_program_instruction *entry, **prev; - int c; - int n = 0; - - program = malloc (sizeof (struct brw_program)); - program->first = NULL; - prev = &program->first; - while ((c = getc (input)) != EOF) { - if (c == '0') { - if (fscanf (input, "x%x", &inst[n]) == 1) { - ++n; - if (n == 4) { - entry = malloc (sizeof (struct brw_program_instruction)); - memcpy (&entry->instruction, inst, 4 * sizeof (uint32_t)); - entry->next = NULL; - *prev = entry; - prev = &entry->next; - n = 0; - } - } - } - } - return program; -} - -static struct brw_program * -read_program_binary (FILE *input) -{ - uint32_t temp; - uint8_t inst[16]; - struct brw_program *program; - struct brw_program_instruction *entry, **prev; - int c; - int n = 0; - - program = malloc (sizeof (struct brw_program)); - program->first = NULL; - prev = &program->first; - while ((c = getc (input)) != EOF) { - if (c == '0') { - if (fscanf (input, "x%2x", &temp) == 1) { - inst[n++] = (uint8_t)temp; - if (n == 16) { - entry = malloc (sizeof (struct brw_program_instruction)); - memcpy (&entry->instruction, inst, 16 * sizeof (uint8_t)); - entry->next = NULL; - *prev = entry; - prev = &entry->next; - n = 0; - } - } - } - } - return program; -} - -static void usage(void) -{ - fprintf(stderr, "usage: intel-gen4disasm [-o outputfile] [-b] inputfile\n"); -} - -int main(int argc, char **argv) -{ - struct brw_program *program; - FILE *input = stdin; - FILE *output = stdout; - char *input_filename = NULL; - char *output_file = NULL; - int byte_array_input = 0; - int o; - struct brw_program_instruction *inst; - - while ((o = getopt_long(argc, argv, "o:b", longopts, NULL)) != -1) { - switch (o) { - case 'o': - if (strcmp(optarg, "-") != 0) - output_file = optarg; - break; - case 'b': - byte_array_input = 1; - break; - default: - usage(); - exit(1); - } - } - argc -= optind; - argv += optind; - if (argc != 1) { - usage(); - exit(1); - } - - if (strcmp(argv[0], "-") != 0) { - input_filename = argv[0]; - input = fopen(input_filename, "r"); - if (input == NULL) { - perror("Couldn't open input file"); - exit(1); - } - } - if (byte_array_input) - program = read_program_binary (input); - else - program = read_program (input); - if (!program) - exit (1); - if (output_file) { - output = fopen (output_file, "w"); - if (output == NULL) { - perror("Couldn't open output file"); - exit(1); - } - } - - for (inst = program->first; inst; inst = inst->next) - disasm (output, &inst->instruction); - exit (0); -} diff --git a/assembler/src/disasm.c b/assembler/src/disasm.c deleted file mode 100644 index 1ec6ae59..00000000 --- a/assembler/src/disasm.c +++ /dev/null @@ -1,906 +0,0 @@ -/* - * Copyright © 2008 Keith Packard - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#include -#include -#include -#include -#include -#include - -#include "gen4asm.h" -#include "brw_defines.h" - -struct { - char *name; - int nsrc; - int ndst; -} opcode[128] = { - [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 }, - - [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1}, - - [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 }, - [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 }, - - [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 1, .ndst = 0 }, - [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 }, - [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 1, .ndst = 01 }, - [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 1, .ndst = 0 }, - [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 }, - [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 1, .ndst = 0 }, - [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 }, - [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 }, - [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 }, - [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 }, - [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 }, - [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 }, - [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 }, -}; - -char *conditional_modifier[16] = { - [BRW_CONDITIONAL_NONE] = "", - [BRW_CONDITIONAL_Z] = ".e", - [BRW_CONDITIONAL_NZ] = ".ne", - [BRW_CONDITIONAL_G] = ".g", - [BRW_CONDITIONAL_GE] = ".ge", - [BRW_CONDITIONAL_L] = ".l", - [BRW_CONDITIONAL_LE] = ".le", - [BRW_CONDITIONAL_R] = ".r", - [BRW_CONDITIONAL_O] = ".o", - [BRW_CONDITIONAL_U] = ".u", -}; - -char *negate[2] = { - [0] = "", - [1] = "-", -}; - -char *_abs[2] = { - [0] = "", - [1] = "(abs)", -}; - -char *vert_stride[16] = { - [0] = "0", - [1] = "1", - [2] = "2", - [3] = "4", - [4] = "8", - [5] = "16", - [6] = "32", - [15] = "VxH", -}; - -char *width[8] = { - [0] = "1", - [1] = "2", - [2] = "4", - [3] = "8", - [4] = "16", -}; - -char *horiz_stride[4] = { - [0] = "0", - [1] = "1", - [2] = "2", - [3] = "4" -}; - -char *chan_sel[4] = { - [0] = "x", - [1] = "y", - [2] = "z", - [3] = "w", -}; - -char *dest_condmod[16] = { -}; - -char *debug_ctrl[2] = { - [0] = "", - [1] = ".breakpoint" -}; - -char *saturate[2] = { - [0] = "", - [1] = ".sat" -}; - -char *exec_size[8] = { - [0] = "1", - [1] = "2", - [2] = "4", - [3] = "8", - [4] = "16", - [5] = "32" -}; - -char *pred_inv[2] = { - [0] = "+", - [1] = "-" -}; - -char *pred_ctrl_align16[16] = { - [1] = "", - [2] = ".x", - [3] = ".y", - [4] = ".z", - [5] = ".w", - [6] = ".any4h", - [7] = ".all4h", -}; - -char *pred_ctrl_align1[16] = { - [1] = "", - [2] = ".anyv", - [3] = ".allv", - [4] = ".any2h", - [5] = ".all2h", - [6] = ".any4h", - [7] = ".all4h", - [8] = ".any8h", - [9] = ".all8h", - [10] = ".any16h", - [11] = ".all16h", -}; - -char *thread_ctrl[4] = { - [0] = "", - [2] = "switch" -}; - -char *compr_ctrl[4] = { - [0] = "", - [1] = "sechalf", - [2] = "compr", -}; - -char *dep_ctrl[4] = { - [0] = "", - [1] = "NoDDClr", - [2] = "NoDDChk", - [3] = "NoDDClr,NoDDChk", -}; - -char *mask_ctrl[4] = { - [0] = "", - [1] = "nomask", -}; - -char *access_mode[2] = { - [0] = "align1", - [1] = "align16", -}; - -char *reg_encoding[8] = { - [0] = "UD", - [1] = "D", - [2] = "UW", - [3] = "W", - [4] = "UB", - [5] = "B", - [7] = "F" -}; - -char *imm_encoding[8] = { - [0] = "UD", - [1] = "D", - [2] = "UW", - [3] = "W", - [5] = "VF", - [6] = "V", - [7] = "F" -}; - -char *reg_file[4] = { - [0] = "A", - [1] = "g", - [2] = "m", - [3] = "imm", -}; - -char *writemask[16] = { - [0x0] = ".", - [0x1] = ".x", - [0x2] = ".y", - [0x3] = ".xy", - [0x4] = ".z", - [0x5] = ".xz", - [0x6] = ".yz", - [0x7] = ".xyz", - [0x8] = ".w", - [0x9] = ".xw", - [0xa] = ".yw", - [0xb] = ".xyw", - [0xc] = ".zw", - [0xd] = ".xzw", - [0xe] = ".yzw", - [0xf] = "", -}; - -char *end_of_thread[2] = { - [0] = "", - [1] = "EOT" -}; - -char *target_function[16] = { - [BRW_MESSAGE_TARGET_NULL] = "null", - [BRW_MESSAGE_TARGET_MATH] = "math", - [BRW_MESSAGE_TARGET_SAMPLER] = "sampler", - [BRW_MESSAGE_TARGET_GATEWAY] = "gateway", - [BRW_MESSAGE_TARGET_DATAPORT_READ] = "read", - [BRW_MESSAGE_TARGET_DATAPORT_WRITE] = "write", - [BRW_MESSAGE_TARGET_URB] = "urb", - [BRW_MESSAGE_TARGET_THREAD_SPAWNER] = "thread_spawner" -}; - -char *math_function[16] = { - [BRW_MATH_FUNCTION_INV] = "inv", - [BRW_MATH_FUNCTION_LOG] = "log", - [BRW_MATH_FUNCTION_EXP] = "exp", - [BRW_MATH_FUNCTION_SQRT] = "sqrt", - [BRW_MATH_FUNCTION_RSQ] = "rsq", - [BRW_MATH_FUNCTION_SIN] = "sin", - [BRW_MATH_FUNCTION_COS] = "cos", - [BRW_MATH_FUNCTION_SINCOS] = "sincos", - [BRW_MATH_FUNCTION_TAN] = "tan", - [BRW_MATH_FUNCTION_POW] = "pow", - [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod", - [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intmod", - [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intdiv", -}; - -char *math_saturate[2] = { - [0] = "", - [1] = "sat" -}; - -char *math_signed[2] = { - [0] = "", - [1] = "signed" -}; - -char *math_scalar[2] = { - [0] = "", - [1] = "scalar" -}; - -char *math_precision[2] = { - [0] = "", - [1] = "partial_precision" -}; - -char *urb_swizzle[4] = { - [BRW_URB_SWIZZLE_NONE] = "", - [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave", - [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose", -}; - -char *urb_allocate[2] = { - [0] = "", - [1] = "allocate" -}; - -char *urb_used[2] = { - [0] = "", - [1] = "used" -}; - -char *urb_complete[2] = { - [0] = "", - [1] = "complete" -}; - -char *sampler_target_format[4] = { - [0] = "F", - [2] = "UD", - [3] = "D" -}; - - -static int column; - -static int string (FILE *file, char *string) -{ - fputs (string, file); - column += strlen (string); - return 0; -} - -static int format (FILE *f, char *format, ...) -{ - char buf[1024]; - va_list args; - va_start (args, format); - - vsnprintf (buf, sizeof (buf) - 1, format, args); - string (f, buf); - return 0; -} - -static int newline (FILE *f) -{ - putc ('\n', f); - column = 0; - return 0; -} - -static int pad (FILE *f, int c) -{ - do - string (f, " "); - while (column < c); - return 0; -} - -static int control (FILE *file, char *name, char *ctrl[], GLuint id, int *space) -{ - if (!ctrl[id]) { - fprintf (file, "*** invalid %s value %d ", - name, id); - return 1; - } - if (ctrl[id][0]) - { - if (space && *space) - string (file, " "); - string (file, ctrl[id]); - if (space) - *space = 1; - } - return 0; -} - -static int print_opcode (FILE *file, int id) -{ - if (!opcode[id].name) { - format (file, "*** invalid opcode value %d ", id); - return 1; - } - string (file, opcode[id].name); - return 0; -} - -static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr) -{ - int err = 0; - if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) { - switch (_reg_nr & 0xf0) { - case BRW_ARF_NULL: - string (file, "null"); - return -1; - case BRW_ARF_ADDRESS: - format (file, "a%d", _reg_nr & 0x0f); - break; - case BRW_ARF_ACCUMULATOR: - format (file, "acc%d", _reg_nr & 0x0f); - break; - case BRW_ARF_MASK: - format (file, "mask%d", _reg_nr & 0x0f); - break; - case BRW_ARF_MASK_STACK: - format (file, "msd%d", _reg_nr & 0x0f); - break; - case BRW_ARF_STATE: - format (file, "sr%d", _reg_nr & 0x0f); - break; - case BRW_ARF_CONTROL: - format (file, "cr%d", _reg_nr & 0x0f); - break; - case BRW_ARF_NOTIFICATION_COUNT: - format (file, "n%d", _reg_nr & 0x0f); - break; - case BRW_ARF_IP: - string (file, "ip"); - return -1; - break; - default: - format (file, "ARF%d", _reg_nr); - break; - } - } else { - err |= control (file, "src reg file", reg_file, _reg_file, NULL); - format (file, "%d", _reg_nr); - } - return err; -} - -static int dest (FILE *file, struct brw_instruction *inst) -{ - int err = 0; - - if (inst->header.access_mode == BRW_ALIGN_1) - { - if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT) - { - err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr); - if (err == -1) - return 0; - if (inst->bits1.da1.dest_subreg_nr) - format (file, ".%d", inst->bits1.da1.dest_subreg_nr); - format (file, "<%d>", inst->bits1.da1.dest_horiz_stride); - err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL); - } - else - { - string (file, "g[a0"); - if (inst->bits1.ia1.dest_subreg_nr) - format (file, ".%d", inst->bits1.ia1.dest_subreg_nr); - if (inst->bits1.ia1.dest_indirect_offset) - format (file, " %d", inst->bits1.ia1.dest_indirect_offset); - string (file, "]"); - format (file, "<%d>", inst->bits1.ia1.dest_horiz_stride); - err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.ia1.dest_reg_type, NULL); - } - } - else - { - if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT) - { - err |= reg (file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr); - if (err == -1) - return 0; - if (inst->bits1.da16.dest_subreg_nr) - format (file, ".%d", inst->bits1.da16.dest_subreg_nr); - string (file, "<1>"); - err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL); - err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL); - } - else - { - err = 1; - string (file, "Indirect align16 address mode not supported"); - } - } - - return 0; -} - -static int src_align1_region (FILE *file, - GLuint _vert_stride, GLuint _width, GLuint _horiz_stride) -{ - int err = 0; - string (file, "<"); - err |= control (file, "vert stride", vert_stride, _vert_stride, NULL); - string (file, ","); - err |= control (file, "width", width, _width, NULL); - string (file, ","); - err |= control (file, "horiz_stride", horiz_stride, _horiz_stride, NULL); - string (file, ">"); - return err; -} - -static int src_da1 (FILE *file, GLuint type, GLuint _reg_file, - GLuint _vert_stride, GLuint _width, GLuint _horiz_stride, - GLuint reg_num, GLuint sub_reg_num, GLuint __abs, GLuint _negate) -{ - int err = 0; - err |= control (file, "negate", negate, _negate, NULL); - err |= control (file, "abs", _abs, __abs, NULL); - - err |= reg (file, _reg_file, reg_num); - if (err == -1) - return 0; - if (sub_reg_num) - format (file, ".%d", sub_reg_num); - src_align1_region (file, _vert_stride, _width, _horiz_stride); - err |= control (file, "src reg encoding", reg_encoding, type, NULL); - return err; -} - -static int src_ia1 (FILE *file, - GLuint type, - GLuint _reg_file, - GLint _addr_imm, - GLuint _addr_subreg_nr, - GLuint _negate, - GLuint __abs, - GLuint _addr_mode, - GLuint _horiz_stride, - GLuint _width, - GLuint _vert_stride) -{ - int err = 0; - err |= control (file, "negate", negate, _negate, NULL); - err |= control (file, "abs", _abs, __abs, NULL); - - string (file, "g[a0"); - if (_addr_subreg_nr) - format (file, ".%d", _addr_subreg_nr); - if (_addr_imm) - format (file, " %d", _addr_imm); - string (file, "]"); - src_align1_region (file, _vert_stride, _width, _horiz_stride); - err |= control (file, "src reg encoding", reg_encoding, type, NULL); - return err; -} - -static int src_da16 (FILE *file, - GLuint _reg_type, - GLuint _reg_file, - GLuint _vert_stride, - GLuint _reg_nr, - GLuint _subreg_nr, - GLuint __abs, - GLuint _negate, - GLuint swz_x, - GLuint swz_y, - GLuint swz_z, - GLuint swz_w) -{ - int err = 0; - err |= control (file, "negate", negate, _negate, NULL); - err |= control (file, "abs", _abs, __abs, NULL); - - err |= reg (file, _reg_file, _reg_nr); - if (err == -1) - return 0; - if (_subreg_nr) - format (file, ".%d", _subreg_nr); - string (file, "<"); - err |= control (file, "vert stride", vert_stride, _vert_stride, NULL); - string (file, ",1,1>"); - err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL); - /* - * Three kinds of swizzle display: - * identity - nothing printed - * 1->all - print the single channel - * 1->1 - print the mapping - */ - if (swz_x == BRW_CHANNEL_X && - swz_y == BRW_CHANNEL_Y && - swz_z == BRW_CHANNEL_Z && - swz_w == BRW_CHANNEL_W) - { - ; - } - else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w) - { - string (file, "."); - err |= control (file, "channel select", chan_sel, swz_x, NULL); - } - else - { - string (file, "."); - err |= control (file, "channel select", chan_sel, swz_x, NULL); - err |= control (file, "channel select", chan_sel, swz_y, NULL); - err |= control (file, "channel select", chan_sel, swz_z, NULL); - err |= control (file, "channel select", chan_sel, swz_w, NULL); - } - return err; -} - - -static int imm (FILE *file, GLuint type, struct brw_instruction *inst) { - switch (type) { - case BRW_REGISTER_TYPE_UD: - format (file, "0x%08xUD", inst->bits3.ud); - break; - case BRW_REGISTER_TYPE_D: - format (file, "%dD", inst->bits3.id); - break; - case BRW_REGISTER_TYPE_UW: - format (file, "0x%04xUW", (uint16_t) inst->bits3.ud); - break; - case BRW_REGISTER_TYPE_W: - format (file, "%dW", (int16_t) inst->bits3.id); - break; - case BRW_REGISTER_TYPE_UB: - format (file, "0x%02xUB", (int8_t) inst->bits3.ud); - break; - case BRW_REGISTER_TYPE_VF: - format (file, "Vector Float"); - break; - case BRW_REGISTER_TYPE_V: - format (file, "0x%08xV", inst->bits3.ud); - break; - case BRW_REGISTER_TYPE_F: - format (file, "%-gF", inst->bits3.fd); - } - return 0; -} - -static int src0 (FILE *file, struct brw_instruction *inst) -{ - if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE) - return imm (file, inst->bits1.da1.src0_reg_type, - inst); - else if (inst->header.access_mode == BRW_ALIGN_1) - { - if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT) - { - return src_da1 (file, - inst->bits1.da1.src0_reg_type, - inst->bits1.da1.src0_reg_file, - inst->bits2.da1.src0_vert_stride, - inst->bits2.da1.src0_width, - inst->bits2.da1.src0_horiz_stride, - inst->bits2.da1.src0_reg_nr, - inst->bits2.da1.src0_subreg_nr, - inst->bits2.da1.src0_abs, - inst->bits2.da1.src0_negate); - } - else - { - return src_ia1 (file, - inst->bits1.ia1.src0_reg_type, - inst->bits1.ia1.src0_reg_file, - inst->bits2.ia1.src0_indirect_offset, - inst->bits2.ia1.src0_subreg_nr, - inst->bits2.ia1.src0_negate, - inst->bits2.ia1.src0_abs, - inst->bits2.ia1.src0_address_mode, - inst->bits2.ia1.src0_horiz_stride, - inst->bits2.ia1.src0_width, - inst->bits2.ia1.src0_vert_stride); - } - } - else - { - if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT) - { - return src_da16 (file, - inst->bits1.da16.src0_reg_type, - inst->bits1.da16.src0_reg_file, - inst->bits2.da16.src0_vert_stride, - inst->bits2.da16.src0_reg_nr, - inst->bits2.da16.src0_subreg_nr, - inst->bits2.da16.src0_abs, - inst->bits2.da16.src0_negate, - inst->bits2.da16.src0_swz_x, - inst->bits2.da16.src0_swz_y, - inst->bits2.da16.src0_swz_z, - inst->bits2.da16.src0_swz_w); - } - else - { - string (file, "Indirect align16 address mode not supported"); - return 1; - } - } -} - -static int src1 (FILE *file, struct brw_instruction *inst) -{ - if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE) - return imm (file, inst->bits1.da1.src1_reg_type, - inst); - else if (inst->header.access_mode == BRW_ALIGN_1) - { - if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT) - { - return src_da1 (file, - inst->bits1.da1.src1_reg_type, - inst->bits1.da1.src1_reg_file, - inst->bits3.da1.src1_vert_stride, - inst->bits3.da1.src1_width, - inst->bits3.da1.src1_horiz_stride, - inst->bits3.da1.src1_reg_nr, - inst->bits3.da1.src1_subreg_nr, - inst->bits3.da1.src1_abs, - inst->bits3.da1.src1_negate); - } - else - { - return src_ia1 (file, - inst->bits1.ia1.src1_reg_type, - inst->bits1.ia1.src1_reg_file, - inst->bits3.ia1.src1_indirect_offset, - inst->bits3.ia1.src1_subreg_nr, - inst->bits3.ia1.src1_negate, - inst->bits3.ia1.src1_abs, - inst->bits3.ia1.src1_address_mode, - inst->bits3.ia1.src1_horiz_stride, - inst->bits3.ia1.src1_width, - inst->bits3.ia1.src1_vert_stride); - } - } - else - { - if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT) - { - return src_da16 (file, - inst->bits1.da16.src1_reg_type, - inst->bits1.da16.src1_reg_file, - inst->bits3.da16.src1_vert_stride, - inst->bits3.da16.src1_reg_nr, - inst->bits3.da16.src1_subreg_nr, - inst->bits3.da16.src1_abs, - inst->bits3.da16.src1_negate, - inst->bits3.da16.src1_swz_x, - inst->bits3.da16.src1_swz_y, - inst->bits3.da16.src1_swz_z, - inst->bits3.da16.src1_swz_w); - } - else - { - string (file, "Indirect align16 address mode not supported"); - return 1; - } - } -} - -int disasm (FILE *file, struct brw_instruction *inst) -{ - int err = 0; - int space = 0; - - if (inst->header.predicate_control) { - string (file, "("); - err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL); - format (file, "f%d", inst->bits2.da1.flag_reg_nr); - if (inst->bits2.da1.flag_subreg_nr) - format (file, ".%d", inst->bits2.da1.flag_subreg_nr); - if (inst->header.access_mode == BRW_ALIGN_1) - err |= control (file, "predicate control align1", pred_ctrl_align1, - inst->header.predicate_control, NULL); - else - err |= control (file, "predicate control align16", pred_ctrl_align16, - inst->header.predicate_control, NULL); - string (file, ") "); - } - - err |= print_opcode (file, inst->header.opcode); - err |= control (file, "saturate", saturate, inst->header.saturate, NULL); - err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL); - - if (inst->header.opcode != BRW_OPCODE_SEND && - inst->header.opcode != BRW_OPCODE_SENDC) - err |= control (file, "conditional modifier", conditional_modifier, - inst->header.sfid_destreg__conditionalmod, NULL); - - if (inst->header.opcode != BRW_OPCODE_NOP) { - string (file, "("); - err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL); - string (file, ")"); - } - - if (inst->header.opcode == BRW_OPCODE_SEND || - inst->header.opcode == BRW_OPCODE_SENDC) - format (file, " %d", inst->header.sfid_destreg__conditionalmod); - - if (opcode[inst->header.opcode].ndst > 0) { - pad (file, 16); - err |= dest (file, inst); - } - if (opcode[inst->header.opcode].nsrc > 0) { - pad (file, 32); - err |= src0 (file, inst); - } - if (opcode[inst->header.opcode].nsrc > 1) { - pad (file, 48); - err |= src1 (file, inst); - } - - if (inst->header.opcode == BRW_OPCODE_SEND || - inst->header.opcode == BRW_OPCODE_SENDC) { - newline (file); - pad (file, 16); - space = 0; - err |= control (file, "target function", target_function, - inst->header.sfid_destreg__conditionalmod, &space); - switch (inst->header.sfid_destreg__conditionalmod) { - case BRW_MESSAGE_TARGET_MATH: - err |= control (file, "math function", math_function, - inst->bits3.math.function, &space); - err |= control (file, "math saturate", math_saturate, - inst->bits3.math.saturate, &space); - err |= control (file, "math signed", math_signed, - inst->bits3.math.int_type, &space); - err |= control (file, "math scalar", math_scalar, - inst->bits3.math.data_type, &space); - err |= control (file, "math precision", math_precision, - inst->bits3.math.precision, &space); - break; - case BRW_MESSAGE_TARGET_SAMPLER: - format (file, " (%d, %d, ", - inst->bits3.sampler.binding_table_index, - inst->bits3.sampler.sampler); - err |= control (file, "sampler target format", sampler_target_format, - inst->bits3.sampler.return_format, NULL); - string (file, ")"); - break; - case BRW_MESSAGE_TARGET_DATAPORT_WRITE: - format (file, " (%d, %d, %d, %d)", - inst->bits3.dp_write.binding_table_index, - (inst->bits3.dp_write.pixel_scoreboard_clear << 3) | - inst->bits3.dp_write.msg_control, - inst->bits3.dp_write.msg_type, - inst->bits3.dp_write.send_commit_msg); - break; - case BRW_MESSAGE_TARGET_URB: - format (file, " %d", inst->bits3.urb.offset); - space = 1; - err |= control (file, "urb swizzle", urb_swizzle, - inst->bits3.urb.swizzle_control, &space); - err |= control (file, "urb allocate", urb_allocate, - inst->bits3.urb.allocate, &space); - err |= control (file, "urb used", urb_used, - inst->bits3.urb.used, &space); - err |= control (file, "urb complete", urb_complete, - inst->bits3.urb.complete, &space); - break; - case BRW_MESSAGE_TARGET_THREAD_SPAWNER: - break; - default: - format (file, "unsupported target %d", inst->bits3.generic.msg_target); - break; - } - if (space) - string (file, " "); - format (file, "mlen %d", - inst->bits3.generic.msg_length); - format (file, " rlen %d", - inst->bits3.generic.response_length); - } - pad (file, 64); - if (inst->header.opcode != BRW_OPCODE_NOP) { - string (file, "{"); - space = 1; - err |= control(file, "access mode", access_mode, inst->header.access_mode, &space); - err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space); - err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space); - err |= control (file, "compression control", compr_ctrl, inst->header.compression_control, &space); - err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space); - if (inst->header.opcode == BRW_OPCODE_SEND) - err |= control (file, "end of thread", end_of_thread, - inst->bits3.generic.end_of_thread, &space); - if (space) - string (file, " "); - string (file, "}"); - } - string (file, ";"); - newline (file); - return err; -} diff --git a/assembler/src/gen4asm.h b/assembler/src/gen4asm.h deleted file mode 100644 index f9ed161d..00000000 --- a/assembler/src/gen4asm.h +++ /dev/null @@ -1,202 +0,0 @@ -/* -*- c-basic-offset: 8 -*- */ -/* - * Copyright © 2006 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: - * Eric Anholt - * - */ - -#include - -typedef unsigned char GLubyte; -typedef short GLshort; -typedef unsigned int GLuint; -typedef int GLint; -typedef float GLfloat; - -extern long int gen_level; - -/* Predicate for Gen X and above */ -#define IS_GENp(x) (gen_level >= (x)*10) - -/* Predicate for Gen X exactly */ -#define IS_GENx(x) (gen_level >= (x)*10 && gen_level < ((x)+1)*10) - -/* Predicate to match Haswell processors */ -#define IS_HASWELL(x) (gen_level == 75) - -#include "brw_defines.h" -#include "brw_structs.h" - -void yyerror (char *msg); - -/** - * This structure is the internal representation of directly-addressed - * registers in the parser. - */ -struct direct_reg { - int reg_file, reg_nr, subreg_nr; -}; - -struct condition { - int cond; - int flag_reg_nr; - int flag_subreg_nr; -}; - -struct region { - int vert_stride, width, horiz_stride; - int is_default; -}; -struct regtype { - int type; - int is_default; -}; -/** - * This structure is the internal representation of register-indirect addressed - * registers in the parser. - */ - -struct indirect_reg { - int reg_file, address_subreg_nr, indirect_offset; -}; - -/** - * This structure is the internal representation of destination operands in the - * parser. - */ -struct dst_operand { - int reg_file, reg_nr, subreg_nr, reg_type; - - int writemask_set; - int writemask; - - int horiz_stride; - int address_mode; /* 0 if direct, 1 if register-indirect */ - - /* Indirect addressing */ - int address_subreg_nr; - int indirect_offset; -}; - -/** - * This structure is the internal representation of source operands in the - * parser. - */ -struct src_operand { - int reg_file, reg_nr, subreg_nr, reg_type; - - int abs, negate; - - int horiz_stride, width, vert_stride; - int default_region; - - int address_mode; /* 0 if direct, 1 if register-indirect */ - int address_subreg_nr; - int indirect_offset; /* XXX */ - - int swizzle_set; - int swizzle_x, swizzle_y, swizzle_z, swizzle_w; - - uint32_t imm32; /* set if reg_file == BRW_IMMEDIATE_VALUE or it is expressing a branch offset */ - char *reloc_target; /* bspec: branching instructions JIP and UIP are source operands */ -} src_operand; - -typedef struct { - enum { - imm32_d, imm32_f - } r; - union { - uint32_t d; - float f; - int32_t signed_d; - } u; -} imm32_t; - -/** - * This structure is just the list container for instructions accumulated by - * the parser and labels. - */ -struct brw_program_instruction { - struct brw_instruction instruction; - struct brw_program_instruction *next; - GLuint islabel; - GLuint inst_offset; - char *string; -}; - -/** - * This structure is a list of instructions. It is the final output of the - * parser. - */ -struct brw_program { - struct brw_program_instruction *first; - struct brw_program_instruction *last; -}; - -extern struct brw_program compiled_program; - -#define TYPE_B_INDEX 0 -#define TYPE_UB_INDEX 1 -#define TYPE_W_INDEX 2 -#define TYPE_UW_INDEX 3 -#define TYPE_D_INDEX 4 -#define TYPE_UD_INDEX 5 -#define TYPE_F_INDEX 6 - -#define TOTAL_TYPES 7 - -struct program_defaults { - int execute_size; - int execute_type[TOTAL_TYPES]; - int register_type; - int register_type_regfile; - struct region source_region; - struct region source_region_type[TOTAL_TYPES]; - struct region dest_region; - struct region dest_region_type[TOTAL_TYPES]; -}; -extern struct program_defaults program_defaults; - -struct declared_register { - char *name; - struct direct_reg base; - int element_size; - struct region src_region; - int dst_region; - int type; -}; -struct declared_register *find_register(char *name); -void insert_register(struct declared_register *reg); -void add_label(char *name, int addr); -int label_to_addr(char *name, int start_addr); - -int yyparse(void); -int yylex(void); -int yylex_destroy(void); - -char * -lex_text(void); - -int -disasm (FILE *output, struct brw_instruction *inst); diff --git a/assembler/src/gram.y b/assembler/src/gram.y deleted file mode 100644 index 2ed79c13..00000000 --- a/assembler/src/gram.y +++ /dev/null @@ -1,3167 +0,0 @@ -%{ -/* - * Copyright © 2006 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: - * Eric Anholt - * - */ - -#include -#include -#include -#include -#include "gen4asm.h" -#include "brw_defines.h" - -#define DEFAULT_EXECSIZE (ffs(program_defaults.execute_size) - 1) -#define DEFAULT_DSTREGION -1 - -extern long int gen_level; -extern int advanced_flag; -extern int yylineno; -extern int need_export; -static struct src_operand src_null_reg = -{ - .reg_file = BRW_ARCHITECTURE_REGISTER_FILE, - .reg_nr = BRW_ARF_NULL, - .reg_type = BRW_REGISTER_TYPE_UD, -}; -static struct dst_operand dst_null_reg = -{ - .reg_file = BRW_ARCHITECTURE_REGISTER_FILE, - .reg_nr = BRW_ARF_NULL, -}; -static struct dst_operand ip_dst = -{ - .reg_file = BRW_ARCHITECTURE_REGISTER_FILE, - .reg_nr = BRW_ARF_IP, - .reg_type = BRW_REGISTER_TYPE_UD, - .address_mode = BRW_ADDRESS_DIRECT, - .horiz_stride = 1, - .writemask = 0xF, -}; -static struct src_operand ip_src = -{ - .reg_file = BRW_ARCHITECTURE_REGISTER_FILE, - .reg_nr = BRW_ARF_IP, - .reg_type = BRW_REGISTER_TYPE_UD, - .address_mode = BRW_ADDRESS_DIRECT, - .swizzle_x = BRW_CHANNEL_X, - .swizzle_y = BRW_CHANNEL_Y, - .swizzle_z = BRW_CHANNEL_Z, - .swizzle_w = BRW_CHANNEL_W, -}; - -static int get_type_size(GLuint type); -int set_instruction_dest(struct brw_instruction *instr, - struct dst_operand *dest); -int set_instruction_src0(struct brw_instruction *instr, - struct src_operand *src); -int set_instruction_src1(struct brw_instruction *instr, - struct src_operand *src); -int set_instruction_dest_three_src(struct brw_instruction *instr, - struct dst_operand *dest); -int set_instruction_src0_three_src(struct brw_instruction *instr, - struct src_operand *src); -int set_instruction_src1_three_src(struct brw_instruction *instr, - struct src_operand *src); -int set_instruction_src2_three_src(struct brw_instruction *instr, - struct src_operand *src); -void set_instruction_options(struct brw_instruction *instr, - struct brw_instruction *options); -void set_instruction_predicate(struct brw_instruction *instr, - struct brw_instruction *predicate); -void set_direct_dst_operand(struct dst_operand *dst, struct direct_reg *reg, - int type); -void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg, - int type); - -%} - -%start ROOT - -%union { - char *string; - int integer; - double number; - struct brw_instruction instruction; - struct brw_program program; - struct region region; - struct regtype regtype; - struct direct_reg direct_reg; - struct indirect_reg indirect_reg; - struct condition condition; - struct declared_register symbol_reg; - imm32_t imm32; - - struct dst_operand dst_operand; - struct src_operand src_operand; -} - -%token COLON -%token SEMICOLON -%token LPAREN RPAREN -%token LANGLE RANGLE -%token LCURLY RCURLY -%token LSQUARE RSQUARE -%token COMMA EQ -%token ABS DOT -%token PLUS MINUS MULTIPLY DIVIDE - -%token TYPE_UD TYPE_D TYPE_UW TYPE_W TYPE_UB TYPE_B -%token TYPE_VF TYPE_HF TYPE_V TYPE_F - -%token ALIGN1 ALIGN16 SECHALF COMPR SWITCH ATOMIC NODDCHK NODDCLR -%token MASK_DISABLE BREAKPOINT ACCWRCTRL EOT - -%token SEQ ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H ANYV ALLV -%token ZERO EQUAL NOT_ZERO NOT_EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL -%token ROUND_INCREMENT OVERFLOW UNORDERED -%token GENREG MSGREG ADDRESSREG ACCREG FLAGREG -%token MASKREG AMASK IMASK LMASK CMASK -%token MASKSTACKREG LMS IMS MASKSTACKDEPTHREG IMSD LMSD -%token NOTIFYREG STATEREG CONTROLREG IPREG -%token GENREGFILE MSGREGFILE - -%token MOV FRC RNDU RNDD RNDE RNDZ NOT LZD -%token MUL MAC MACH LINE SAD2 SADA2 DP4 DPH DP3 DP2 -%token AVG ADD SEL AND OR XOR SHR SHL ASR CMP CMPN PLN -%token ADDC BFI1 BFREV CBIT F16TO32 F32TO16 FBH FBL -%token SEND NOP JMPI IF IFF WHILE ELSE BREAK CONT HALT MSAVE -%token PUSH MREST POP WAIT DO ENDIF ILLEGAL -%token MATH_INST -%token MAD LRP BFE BFI2 SUBB -%token CALL RET -%token BRD BRC - -%token NULL_TOKEN MATH SAMPLER GATEWAY READ WRITE URB THREAD_SPAWNER VME DATA_PORT CRE - -%token MSGLEN RETURNLEN -%token ALLOCATE USED COMPLETE TRANSPOSE INTERLEAVE -%token SATURATE - -%token INTEGER -%token STRING -%token NUMBER - -%token INV LOG EXP SQRT RSQ POW SIN COS SINCOS INTDIV INTMOD -%token INTDIVMOD -%token SIGNED SCALAR - -%token X Y Z W - -%token KERNEL_PRAGMA END_KERNEL_PRAGMA CODE_PRAGMA END_CODE_PRAGMA -%token REG_COUNT_PAYLOAD_PRAGMA REG_COUNT_TOTAL_PRAGMA DECLARE_PRAGMA -%token BASE ELEMENTSIZE SRCREGION DSTREGION TYPE - -%token DEFAULT_EXEC_SIZE_PRAGMA DEFAULT_REG_TYPE_PRAGMA -%nonassoc SUBREGNUM -%nonassoc SNDOPR -%left PLUS MINUS -%left MULTIPLY DIVIDE -%right UMINUS -%nonassoc DOT -%nonassoc STR_SYMBOL_REG -%nonassoc EMPTEXECSIZE -%nonassoc LPAREN - -%type exp sndopr -%type simple_int -%type instruction unaryinstruction binaryinstruction -%type binaryaccinstruction trinaryinstruction sendinstruction -%type jumpinstruction -%type breakinstruction syncinstruction -%type msgtarget -%type instoptions instoption_list predicate -%type mathinstruction -%type subroutineinstruction -%type multibranchinstruction -%type nopinstruction loopinstruction ifelseinstruction haltinstruction -%type label -%type instrseq -%type instoption -%type unaryop binaryop binaryaccop breakop -%type trinaryop -%type conditionalmodifier -%type condition saturate negate abs chansel -%type writemask_x writemask_y writemask_z writemask_w -%type srcimmtype execsize dstregion immaddroffset -%type subregnum sampler_datatype -%type urb_swizzle urb_allocate urb_used urb_complete -%type math_function math_signed math_scalar -%type predctrl predstate -%type region region_wh indirectregion declare_srcregion; -%type regtype -%type directgenreg directmsgreg addrreg accreg flagreg maskreg -%type maskstackreg notifyreg -/* %type maskstackdepthreg */ -%type statereg controlreg ipreg nullreg -%type dstoperandex_typed srcarchoperandex_typed -%type sendleadreg -%type indirectgenreg indirectmsgreg addrparam -%type mask_subreg maskstack_subreg -%type declare_elementsize declare_dstregion declare_type -/* %type maskstackdepth_subreg */ -%type symbol_reg symbol_reg_p; -%type imm32 -%type dst dstoperand dstoperandex dstreg post_dst writemask -%type declare_base -%type directsrcoperand srcarchoperandex directsrcaccoperand -%type indirectsrcoperand -%type src srcimm imm32reg payload srcacc srcaccimm swizzle -%type relativelocation relativelocation2 -%% -simple_int: INTEGER { $$ = $1; } - | MINUS INTEGER { $$ = -$2;} -; - -exp: INTEGER { $$ = $1; } - | exp PLUS exp { $$ = $1 + $3; } - | exp MINUS exp { $$ = $1 - $3; } - | exp MULTIPLY exp { $$ = $1 * $3; } - | exp DIVIDE exp { if ($3) $$ = $1 / $3; else YYERROR;} - | MINUS exp %prec UMINUS { $$ = -$2;} - | LPAREN exp RPAREN { $$ = $2; } - ; - -ROOT: instrseq - { - compiled_program = $1; - } -; - - -label: STRING COLON -; - -declare_base: BASE EQ dstreg - { - $$ = $3; - } -; -declare_elementsize: ELEMENTSIZE EQ exp - { - $$ = $3; - } -; -declare_srcregion: /* empty */ - { - /* XXX is this default correct?*/ - memset (&$$, '\0', sizeof ($$)); - $$.vert_stride = ffs(0); - $$.width = ffs(1) - 1; - $$.horiz_stride = ffs(0); - } - | SRCREGION EQ region - { - $$ = $3; - } -; -declare_dstregion: /* empty */ - { - $$ = 1; - } - | DSTREGION EQ dstregion - { - $$ = $3; - } -; -declare_type: TYPE EQ regtype - { - $$ = $3.type; - } -; -declare_pragma: DECLARE_PRAGMA STRING declare_base declare_elementsize declare_srcregion declare_dstregion declare_type - { - struct declared_register *reg; - int defined; - defined = (reg = find_register($2)) != NULL; - if (defined) { - fprintf(stderr, "WARNING: %s already defined\n", $2); - free($2); // $2 has been malloc'ed by strdup - } else { - reg = calloc(sizeof(struct declared_register), 1); - reg->name = $2; - } - reg->base.reg_file = $3.reg_file; - reg->base.reg_nr = $3.reg_nr; - reg->base.subreg_nr = $3.subreg_nr; - reg->element_size = $4; - reg->src_region = $5; - reg->dst_region = $6; - reg->type = $7; - if (!defined) { - insert_register(reg); - } - } -; - -reg_count_total_pragma: REG_COUNT_TOTAL_PRAGMA exp -; -reg_count_payload_pragma: REG_COUNT_PAYLOAD_PRAGMA exp -; - -default_exec_size_pragma: DEFAULT_EXEC_SIZE_PRAGMA exp - { - program_defaults.execute_size = $2; - } -; -default_reg_type_pragma: DEFAULT_REG_TYPE_PRAGMA regtype - { - program_defaults.register_type = $2.type; - } -; -pragma: reg_count_total_pragma - |reg_count_payload_pragma - |default_exec_size_pragma - |default_reg_type_pragma - |declare_pragma -; - -instrseq: instrseq pragma - { - $$ = $1; - } - | instrseq instruction SEMICOLON - { - struct brw_program_instruction *list_entry = - calloc(sizeof(struct brw_program_instruction), 1); - list_entry->instruction = $2; - list_entry->next = NULL; - if ($1.last) { - $1.last->next = list_entry; - } else { - $1.first = list_entry; - } - $1.last = list_entry; - $$ = $1; - } - | instruction SEMICOLON - { - struct brw_program_instruction *list_entry = - calloc(sizeof(struct brw_program_instruction), 1); - list_entry->instruction = $1; - - list_entry->next = NULL; - - $$.first = list_entry; - $$.last = list_entry; - } - | instrseq SEMICOLON - { - $$ = $1; - } - | instrseq label - { - struct brw_program_instruction *list_entry = - calloc(sizeof(struct brw_program_instruction), 1); - list_entry->string = strdup($2); - list_entry->islabel = 1; - list_entry->next = NULL; - if ($1.last) { - $1.last->next = list_entry; - } else { - $1.first = list_entry; - } - $1.last = list_entry; - $$ = $1; - } - | label - { - struct brw_program_instruction *list_entry = - calloc(sizeof(struct brw_program_instruction), 1); - list_entry->string = strdup($1); - list_entry->islabel = 1; - - list_entry->next = NULL; - - $$.first = list_entry; - $$.last = list_entry; - } - | pragma - { - $$.first = NULL; - $$.last = NULL; - } - | instrseq error SEMICOLON { - $$ = $1; - } -; - -/* 1.4.1: Instruction groups */ -// binaryinstruction: Source operands cannot be accumulators -// binaryaccinstruction: Source operands can be accumulators -instruction: unaryinstruction - | binaryinstruction - | binaryaccinstruction - | trinaryinstruction - | sendinstruction - | jumpinstruction - | ifelseinstruction - | breakinstruction - | syncinstruction - | mathinstruction - | subroutineinstruction - | multibranchinstruction - | nopinstruction - | haltinstruction - | loopinstruction -; - -ifelseinstruction: ENDIF - { - // for Gen4 - if(IS_GENp(6)) { // For gen6+. - fprintf(stderr, "ENDIF Syntax error: should be 'ENDIF execsize relativelocation'\n"); - YYERROR; - } - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $1; - $$.header.thread_control |= BRW_THREAD_SWITCH; - $$.bits1.da1.dest_horiz_stride = 1; - $$.bits1.da1.src1_reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.bits1.da1.src1_reg_type = BRW_REGISTER_TYPE_UD; - } - | ENDIF execsize relativelocation instoptions - { - // for Gen6+ - /* Gen6, Gen7 bspec: predication is prohibited */ - if(!IS_GENp(6)) { // for gen6- - fprintf(stderr, "ENDIF Syntax error: should be 'ENDIF'\n"); - YYERROR; - } - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $1; - $$.header.execution_size = $2; - $$.first_reloc_target = $3.reloc_target; - $$.first_reloc_offset = $3.imm32; - } - | ELSE execsize relativelocation instoptions - { - if(!IS_GENp(6)) { - // for Gen4, Gen5. gen_level < 60 - /* Set the istack pop count, which must always be 1. */ - $3.imm32 |= (1 << 16); - - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $1; - $$.header.execution_size = $2; - $$.header.thread_control |= BRW_THREAD_SWITCH; - set_instruction_dest(&$$, &ip_dst); - set_instruction_src0(&$$, &ip_src); - set_instruction_src1(&$$, &$3); - $$.first_reloc_target = $3.reloc_target; - $$.first_reloc_offset = $3.imm32; - } else if(IS_GENp(6)) { - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $1; - $$.header.execution_size = $2; - $$.first_reloc_target = $3.reloc_target; - $$.first_reloc_offset = $3.imm32; - } else { - fprintf(stderr, "'ELSE' instruction is not implemented.\n"); - YYERROR; - } - } - | predicate IF execsize relativelocation - { - /* for Gen4, Gen5 */ - /* The branch instructions require that the IP register - * be the destination and first source operand, while the - * offset is the second source operand. The offset is added - * to the pre-incremented IP. - */ - /* for Gen6 */ - if(IS_GENp(7)) { - /* Error in Gen7+. */ - fprintf(stderr, "Syntax error: IF should be 'IF execsize JIP UIP'\n"); - YYERROR; - } - memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); - $$.header.opcode = $2; - $$.header.execution_size = $3; - if(!IS_GENp(6)) { - $$.header.thread_control |= BRW_THREAD_SWITCH; - set_instruction_dest(&$$, &ip_dst); - set_instruction_src0(&$$, &ip_src); - set_instruction_src1(&$$, &$4); - } - $$.first_reloc_target = $4.reloc_target; - $$.first_reloc_offset = $4.imm32; - } - | predicate IF execsize relativelocation relativelocation - { - /* for Gen7+ */ - if(!IS_GENp(7)) { - fprintf(stderr, "Syntax error: IF should be 'IF execsize relativelocation'\n"); - YYERROR; - } - memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.first_reloc_target = $4.reloc_target; - $$.first_reloc_offset = $4.imm32; - $$.second_reloc_target = $5.reloc_target; - $$.second_reloc_offset = $5.imm32; - } -; - -loopinstruction: predicate WHILE execsize relativelocation instoptions - { - if(!IS_GENp(6)) { - /* The branch instructions require that the IP register - * be the destination and first source operand, while the - * offset is the second source operand. The offset is added - * to the pre-incremented IP. - */ - set_instruction_dest(&$$, &ip_dst); - memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.header.thread_control |= BRW_THREAD_SWITCH; - set_instruction_src0(&$$, &ip_src); - set_instruction_src1(&$$, &$4); - $$.first_reloc_target = $4.reloc_target; - $$.first_reloc_offset = $4.imm32; - } else if (IS_GENp(6)) { - /* Gen6 spec: - dest must have the same element size as src0. - dest horizontal stride must be 1. */ - memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.first_reloc_target = $4.reloc_target; - $$.first_reloc_offset = $4.imm32; - } else { - fprintf(stderr, "'WHILE' instruction is not implemented!\n"); - YYERROR; - } - } - | DO - { - // deprecated - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $1; - }; - -haltinstruction: predicate HALT execsize relativelocation relativelocation instoptions - { - // for Gen6, Gen7 - /* Gen6, Gen7 bspec: dst and src0 must be the null reg. */ - memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.first_reloc_target = $4.reloc_target; - $$.first_reloc_offset = $4.imm32; - $$.second_reloc_target = $5.reloc_target; - $$.second_reloc_offset = $5.imm32; - set_instruction_dest(&$$, &dst_null_reg); - set_instruction_src0(&$$, &src_null_reg); - }; - -multibranchinstruction: - predicate BRD execsize relativelocation instoptions - { - /* Gen7 bspec: dest must be null. use Switch option */ - memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.header.thread_control |= BRW_THREAD_SWITCH; - $$.first_reloc_target = $4.reloc_target; - $$.first_reloc_offset = $4.imm32; - set_instruction_dest(&$$, &dst_null_reg); - } - | predicate BRC execsize relativelocation relativelocation instoptions - { - /* Gen7 bspec: dest must be null. src0 must be null. use Switch option */ - memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.header.thread_control |= BRW_THREAD_SWITCH; - $$.first_reloc_target = $4.reloc_target; - $$.first_reloc_offset = $4.imm32; - $$.second_reloc_target = $5.reloc_target; - $$.second_reloc_offset = $5.imm32; - set_instruction_dest(&$$, &dst_null_reg); - set_instruction_src0(&$$, &src_null_reg); - } -; - -subroutineinstruction: - predicate CALL execsize dst relativelocation instoptions - { - /* - Gen6 bspec: - source, dest type should be DWORD. - dest must be QWord aligned. - source0 region control must be <2,2,1>. - execution size must be 2. - QtrCtrl is prohibited. - JIP is an immediate operand, must be of type W. - Gen7 bspec: - source, dest type should be DWORD. - dest must be QWord aligned. - source0 region control must be <2,2,1>. - execution size must be 2. - */ - memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); - $$.header.opcode = $2; - $$.header.execution_size = 1; /* execution size must be 2. Here 1 is encoded 2. */ - - $4.reg_type = BRW_REGISTER_TYPE_D; /* dest type should be DWORD */ - set_instruction_dest(&$$, &$4); - - struct src_operand src0; - memset(&src0, 0, sizeof(src0)); - src0.reg_type = BRW_REGISTER_TYPE_D; /* source type should be DWORD */ - /* source0 region control must be <2,2,1>. */ - src0.horiz_stride = 1; /*encoded 1*/ - src0.width = 1; /*encoded 2*/ - src0.vert_stride = 2; /*encoded 2*/ - set_instruction_src0(&$$, &src0); - - $$.first_reloc_target = $5.reloc_target; - $$.first_reloc_offset = $5.imm32; - } - | predicate RET execsize dstoperandex src instoptions - { - /* - Gen6, 7: - source cannot be accumulator. - dest must be null. - src0 region control must be <2,2,1> (not specified clearly. should be same as CALL) - */ - memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); - $$.header.opcode = $2; - $$.header.execution_size = 1; /* execution size of RET should be 2 */ - set_instruction_dest(&$$, &dst_null_reg); - $5.reg_type = BRW_REGISTER_TYPE_D; - $5.horiz_stride = 1; /*encoded 1*/ - $5.width = 1; /*encoded 2*/ - $5.vert_stride = 2; /*encoded 2*/ - set_instruction_src0(&$$, &$5); - } -; - -unaryinstruction: - predicate unaryop conditionalmodifier saturate execsize - dst srcaccimm instoptions - { - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.sfid_destreg__conditionalmod = $3.cond; - $$.header.saturate = $4; - $$.header.execution_size = $5; - set_instruction_options(&$$, &$8); - set_instruction_predicate(&$$, &$1); - if (set_instruction_dest(&$$, &$6) != 0) - YYERROR; - if (set_instruction_src0(&$$, &$7) != 0) - YYERROR; - - if ($3.flag_subreg_nr != -1) { - if ($$.header.predicate_control != BRW_PREDICATE_NONE && - ($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr || - $1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) - fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n"); - - $$.bits2.da1.flag_reg_nr = $3.flag_reg_nr; - $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; - } - - if (!IS_GENp(6) && - get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) - $$.header.compression_control = BRW_COMPRESSION_COMPRESSED; - } -; - -unaryop: MOV | FRC | RNDU | RNDD | RNDE | RNDZ | NOT | LZD | BFREV | CBIT - | F16TO32 | F32TO16 | FBH | FBL -; - -// Source operands cannot be accumulators -binaryinstruction: - predicate binaryop conditionalmodifier saturate execsize - dst src srcimm instoptions - { - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.sfid_destreg__conditionalmod = $3.cond; - $$.header.saturate = $4; - $$.header.execution_size = $5; - set_instruction_options(&$$, &$9); - set_instruction_predicate(&$$, &$1); - if (set_instruction_dest(&$$, &$6) != 0) - YYERROR; - if (set_instruction_src0(&$$, &$7) != 0) - YYERROR; - if (set_instruction_src1(&$$, &$8) != 0) - YYERROR; - - if ($3.flag_subreg_nr != -1) { - if ($$.header.predicate_control != BRW_PREDICATE_NONE && - ($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr || - $1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) - fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n"); - - $$.bits2.da1.flag_reg_nr = $3.flag_reg_nr; - $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; - } - - if (!IS_GENp(6) && - get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) - $$.header.compression_control = BRW_COMPRESSION_COMPRESSED; - } -; - -/* bspec: BFI1 should not access accumulator. */ -binaryop: MUL | MAC | MACH | LINE | SAD2 | SADA2 | DP4 | DPH | DP3 | DP2 | PLN | BFI1 -; - -// Source operands can be accumulators -binaryaccinstruction: - predicate binaryaccop conditionalmodifier saturate execsize - dst srcacc srcimm instoptions - { - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.sfid_destreg__conditionalmod = $3.cond; - $$.header.saturate = $4; - $$.header.execution_size = $5; - set_instruction_options(&$$, &$9); - set_instruction_predicate(&$$, &$1); - if (set_instruction_dest(&$$, &$6) != 0) - YYERROR; - if (set_instruction_src0(&$$, &$7) != 0) - YYERROR; - if (set_instruction_src1(&$$, &$8) != 0) - YYERROR; - - if ($3.flag_subreg_nr != -1) { - if ($$.header.predicate_control != BRW_PREDICATE_NONE && - ($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr || - $1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) - fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n"); - - $$.bits2.da1.flag_reg_nr = $3.flag_reg_nr; - $$.bits2.da1.flag_subreg_nr = $3.flag_subreg_nr; - } - - if (!IS_GENp(6) && - get_type_size($$.bits1.da1.dest_reg_type) * (1 << $$.header.execution_size) == 64) - $$.header.compression_control = BRW_COMPRESSION_COMPRESSED; - } -; - -/* TODO: bspec says ADDC/SUBB/CMP/CMPN/SHL/BFI1 cannot use accumulator as dest. */ -binaryaccop: AVG | ADD | SEL | AND | OR | XOR | SHR | SHL | ASR | CMP | CMPN | ADDC | SUBB -; - -trinaryop: MAD | LRP | BFE | BFI2 -; - -trinaryinstruction: - predicate trinaryop conditionalmodifier saturate execsize - dst src src src instoptions -{ - memset(&$$, 0, sizeof($$)); - - $$.header.predicate_control = $1.header.predicate_control; - $$.header.predicate_inverse = $1.header.predicate_inverse; - $$.bits1.three_src_gen6.flag_reg_nr = $1.bits2.da1.flag_reg_nr; - $$.bits1.three_src_gen6.flag_subreg_nr = $1.bits2.da1.flag_subreg_nr; - - $$.header.opcode = $2; - $$.header.sfid_destreg__conditionalmod = $3.cond; - $$.header.saturate = $4; - $$.header.execution_size = $5; - - if (set_instruction_dest_three_src(&$$, &$6)) - YYERROR; - if (set_instruction_src0_three_src(&$$, &$7)) - YYERROR; - if (set_instruction_src1_three_src(&$$, &$8)) - YYERROR; - if (set_instruction_src2_three_src(&$$, &$9)) - YYERROR; - set_instruction_options(&$$, &$10); - - if ($3.flag_subreg_nr != -1) { - if ($$.header.predicate_control != BRW_PREDICATE_NONE && - ($1.bits2.da1.flag_reg_nr != $3.flag_reg_nr || - $1.bits2.da1.flag_subreg_nr != $3.flag_subreg_nr)) - fprintf(stderr, "WARNING: must use the same flag register if both prediction and conditional modifier are enabled\n"); - } -} -; - -sendinstruction: predicate SEND execsize exp post_dst payload msgtarget - MSGLEN exp RETURNLEN exp instoptions - { - /* Send instructions are messy. The first argument is the - * post destination -- the grf register that the response - * starts from. The second argument is the current - * destination, which is the start of the message arguments - * to the shared function, and where src0 payload is loaded - * to if not null. The payload is typically based on the - * grf 0 thread payload of your current thread, and is - * implicitly loaded if non-null. - */ - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */ - set_instruction_predicate(&$$, &$1); - if (set_instruction_dest(&$$, &$5) != 0) - YYERROR; - - if (IS_GENp(6)) { - struct src_operand src0; - - memset(&src0, 0, sizeof(src0)); - src0.address_mode = BRW_ADDRESS_DIRECT; - - if (IS_GENp(7)) - src0.reg_file = BRW_GENERAL_REGISTER_FILE; - else - src0.reg_file = BRW_MESSAGE_REGISTER_FILE; - - src0.reg_type = BRW_REGISTER_TYPE_D; - src0.reg_nr = $4; - src0.subreg_nr = 0; - set_instruction_src0(&$$, &src0); - } else { - if (set_instruction_src0(&$$, &$6) != 0) - YYERROR; - } - - $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; - $$.bits1.da1.src1_reg_type = BRW_REGISTER_TYPE_D; - - if (IS_GENp(5)) { - if (IS_GENp(6)) { - $$.header.sfid_destreg__conditionalmod = $7.bits2.send_gen5.sfid; - } else { - $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */ - $$.bits2.send_gen5.sfid = $7.bits2.send_gen5.sfid; - $$.bits2.send_gen5.end_of_thread = $12.bits3.generic_gen5.end_of_thread; - } - - $$.bits3.generic_gen5 = $7.bits3.generic_gen5; - $$.bits3.generic_gen5.msg_length = $9; - $$.bits3.generic_gen5.response_length = $11; - $$.bits3.generic_gen5.end_of_thread = - $12.bits3.generic_gen5.end_of_thread; - } else { - $$.header.sfid_destreg__conditionalmod = $4; /* msg reg index */ - $$.bits3.generic = $7.bits3.generic; - $$.bits3.generic.msg_length = $9; - $$.bits3.generic.response_length = $11; - $$.bits3.generic.end_of_thread = - $12.bits3.generic.end_of_thread; - } - } - | predicate SEND execsize dst sendleadreg payload directsrcoperand instoptions - { - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ - - set_instruction_predicate(&$$, &$1); - - if (set_instruction_dest(&$$, &$4) != 0) - YYERROR; - if (set_instruction_src0(&$$, &$6) != 0) - YYERROR; - /* XXX is this correct? */ - if (set_instruction_src1(&$$, &$7) != 0) - YYERROR; - } - | predicate SEND execsize dst sendleadreg payload imm32reg instoptions - { - if ($7.reg_type != BRW_REGISTER_TYPE_UD && - $7.reg_type != BRW_REGISTER_TYPE_D && - $7.reg_type != BRW_REGISTER_TYPE_V) { - fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $7.imm32, $7.reg_type); - YYERROR; - } - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ - - set_instruction_predicate(&$$, &$1); - if (set_instruction_dest(&$$, &$4) != 0) - YYERROR; - if (set_instruction_src0(&$$, &$6) != 0) - YYERROR; - $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; - $$.bits1.da1.src1_reg_type = $7.reg_type; - $$.bits3.ud = $7.imm32; - } - | predicate SEND execsize dst sendleadreg sndopr imm32reg instoptions - { - struct src_operand src0; - - if (!IS_GENp(6)) { - fprintf(stderr, "error: the syntax of send instruction\n"); - YYERROR; - } - - if ($7.reg_type != BRW_REGISTER_TYPE_UD && - $7.reg_type != BRW_REGISTER_TYPE_D && - $7.reg_type != BRW_REGISTER_TYPE_V) { - fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $7.imm32, $7.reg_type); - YYERROR; - } - - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ - set_instruction_predicate(&$$, &$1); - - if (set_instruction_dest(&$$, &$4) != 0) - YYERROR; - - memset(&src0, 0, sizeof(src0)); - src0.address_mode = BRW_ADDRESS_DIRECT; - - if (IS_GENp(7)) { - src0.reg_file = BRW_GENERAL_REGISTER_FILE; - src0.reg_type = BRW_REGISTER_TYPE_UB; - } else { - src0.reg_file = BRW_MESSAGE_REGISTER_FILE; - src0.reg_type = BRW_REGISTER_TYPE_D; - } - - src0.reg_nr = $5.reg_nr; - src0.subreg_nr = 0; - set_instruction_src0(&$$, &src0); - - $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; - $$.bits1.da1.src1_reg_type = $7.reg_type; - $$.bits3.ud = $7.imm32; - $$.bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); - } - | predicate SEND execsize dst sendleadreg sndopr directsrcoperand instoptions - { - struct src_operand src0; - - if (!IS_GENp(6)) { - fprintf(stderr, "error: the syntax of send instruction\n"); - YYERROR; - } - - if ($7.reg_file != BRW_ARCHITECTURE_REGISTER_FILE || - ($7.reg_nr & 0xF0) != BRW_ARF_ADDRESS || - ($7.reg_nr & 0x0F) != 0 || - $7.subreg_nr != 0) { - fprintf (stderr, "%d: scalar register must be a0.0<0;1,0>:ud\n", yylineno); - YYERROR; - } - - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = ($6 & EX_DESC_SFID_MASK); /* SFID */ - set_instruction_predicate(&$$, &$1); - - if (set_instruction_dest(&$$, &$4) != 0) - YYERROR; - - memset(&src0, 0, sizeof(src0)); - src0.address_mode = BRW_ADDRESS_DIRECT; - - if (IS_GENp(7)) { - src0.reg_file = BRW_GENERAL_REGISTER_FILE; - src0.reg_type = BRW_REGISTER_TYPE_UB; - } else { - src0.reg_file = BRW_MESSAGE_REGISTER_FILE; - src0.reg_type = BRW_REGISTER_TYPE_D; - } - - src0.reg_nr = $5.reg_nr; - src0.subreg_nr = 0; - set_instruction_src0(&$$, &src0); - - set_instruction_src1(&$$, &$7); - $$.bits3.generic_gen5.end_of_thread = !!($6 & EX_DESC_EOT_MASK); - } - | predicate SEND execsize dst sendleadreg payload sndopr imm32reg instoptions - { - if ($8.reg_type != BRW_REGISTER_TYPE_UD && - $8.reg_type != BRW_REGISTER_TYPE_D && - $8.reg_type != BRW_REGISTER_TYPE_V) { - fprintf (stderr, "%d: non-int D/UD/V representation: %d,type=%d\n", yylineno, $8.imm32, $8.reg_type); - YYERROR; - } - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ - - set_instruction_predicate(&$$, &$1); - if (set_instruction_dest(&$$, &$4) != 0) - YYERROR; - if (set_instruction_src0(&$$, &$6) != 0) - YYERROR; - $$.bits1.da1.src1_reg_file = BRW_IMMEDIATE_VALUE; - $$.bits1.da1.src1_reg_type = $8.reg_type; - if (IS_GENx(5)) { - $$.bits2.send_gen5.sfid = ($7 & EX_DESC_SFID_MASK); - $$.bits3.ud = $8.imm32; - $$.bits3.generic_gen5.end_of_thread = !!($7 & EX_DESC_EOT_MASK); - } - else - $$.bits3.ud = $8.imm32; - } - | predicate SEND execsize dst sendleadreg payload exp directsrcoperand instoptions - { - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.header.sfid_destreg__conditionalmod = $5.reg_nr; /* msg reg index */ - - set_instruction_predicate(&$$, &$1); - - if (set_instruction_dest(&$$, &$4) != 0) - YYERROR; - if (set_instruction_src0(&$$, &$6) != 0) - YYERROR; - /* XXX is this correct? */ - if (set_instruction_src1(&$$, &$8) != 0) - YYERROR; - if (IS_GENx(5)) { - $$.bits2.send_gen5.sfid = $7; - } - } - -; - -sndopr: exp %prec SNDOPR - { - $$ = $1; - } -; - -jumpinstruction: predicate JMPI execsize relativelocation2 - { - /* The jump instruction requires that the IP register - * be the destination and first source operand, while the - * offset is the second source operand. The next instruction - * is the post-incremented IP plus the offset. - */ - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.execution_size = ffs(1) - 1; - if(advanced_flag) - $$.header.mask_control = BRW_MASK_DISABLE; - set_instruction_predicate(&$$, &$1); - set_instruction_dest(&$$, &ip_dst); - set_instruction_src0(&$$, &ip_src); - set_instruction_src1(&$$, &$4); - $$.first_reloc_target = $4.reloc_target; - $$.first_reloc_offset = $4.imm32; - } -; - -mathinstruction: predicate MATH_INST execsize dst src srcimm math_function instoptions - { - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.sfid_destreg__conditionalmod = $7; - $$.header.execution_size = $3; - set_instruction_options(&$$, &$8); - set_instruction_predicate(&$$, &$1); - if (set_instruction_dest(&$$, &$4) != 0) - YYERROR; - if (set_instruction_src0(&$$, &$5) != 0) - YYERROR; - if (set_instruction_src1(&$$, &$6) != 0) - YYERROR; - } -; - -breakinstruction: predicate breakop execsize relativelocation relativelocation instoptions - { - // for Gen6, Gen7 - memset(&$$, 0, sizeof($$)); - set_instruction_predicate(&$$, &$1); - $$.header.opcode = $2; - $$.header.execution_size = $3; - $$.first_reloc_target = $4.reloc_target; - $$.first_reloc_offset = $4.imm32; - $$.second_reloc_target = $5.reloc_target; - $$.second_reloc_offset = $5.imm32; - } -; - -breakop: BREAK | CONT -; - -/* -maskpushop: MSAVE | PUSH -; - */ - -syncinstruction: predicate WAIT notifyreg - { - struct dst_operand notify_dst; - struct src_operand notify_src; - - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $2; - $$.header.execution_size = ffs(1) - 1; - set_direct_dst_operand(¬ify_dst, &$3, BRW_REGISTER_TYPE_D); - set_instruction_dest(&$$, ¬ify_dst); - set_direct_src_operand(¬ify_src, &$3, BRW_REGISTER_TYPE_D); - set_instruction_src0(&$$, ¬ify_src); - set_instruction_src1(&$$, &src_null_reg); - } - -; - -nopinstruction: NOP - { - memset(&$$, 0, sizeof($$)); - $$.header.opcode = $1; - }; - -/* XXX! */ -payload: directsrcoperand -; - -post_dst: dst -; - -msgtarget: NULL_TOKEN - { - if (IS_GENp(5)) { - $$.bits2.send_gen5.sfid= BRW_MESSAGE_TARGET_NULL; - $$.bits3.generic_gen5.header_present = 0; /* ??? */ - } else { - $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_NULL; - } - } - | SAMPLER LPAREN INTEGER COMMA INTEGER COMMA - sampler_datatype RPAREN - { - if (IS_GENp(7)) { - $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_SAMPLER; - $$.bits3.generic_gen5.header_present = 1; /* ??? */ - $$.bits3.sampler_gen7.binding_table_index = $3; - $$.bits3.sampler_gen7.sampler = $5; - $$.bits3.sampler_gen7.simd_mode = 2; /* SIMD16, maybe we should add a new parameter */ - } else if (IS_GENp(5)) { - $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_SAMPLER; - $$.bits3.generic_gen5.header_present = 1; /* ??? */ - $$.bits3.sampler_gen5.binding_table_index = $3; - $$.bits3.sampler_gen5.sampler = $5; - $$.bits3.sampler_gen5.simd_mode = 2; /* SIMD16, maybe we should add a new parameter */ - } else { - $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_SAMPLER; - $$.bits3.sampler.binding_table_index = $3; - $$.bits3.sampler.sampler = $5; - switch ($7) { - case TYPE_F: - $$.bits3.sampler.return_format = - BRW_SAMPLER_RETURN_FORMAT_FLOAT32; - break; - case TYPE_UD: - $$.bits3.sampler.return_format = - BRW_SAMPLER_RETURN_FORMAT_UINT32; - break; - case TYPE_D: - $$.bits3.sampler.return_format = - BRW_SAMPLER_RETURN_FORMAT_SINT32; - break; - } - } - } - | MATH math_function saturate math_signed math_scalar - { - if (IS_GENp(6)) { - fprintf (stderr, "Gen6+ doesn't have math function\n"); - YYERROR; - } else if (IS_GENx(5)) { - $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_MATH; - $$.bits3.generic_gen5.header_present = 0; - $$.bits3.math_gen5.function = $2; - if ($3 == BRW_INSTRUCTION_SATURATE) - $$.bits3.math_gen5.saturate = 1; - else - $$.bits3.math_gen5.saturate = 0; - $$.bits3.math_gen5.int_type = $4; - $$.bits3.math_gen5.precision = BRW_MATH_PRECISION_FULL; - $$.bits3.math_gen5.data_type = $5; - } else { - $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_MATH; - $$.bits3.math.function = $2; - if ($3 == BRW_INSTRUCTION_SATURATE) - $$.bits3.math.saturate = 1; - else - $$.bits3.math.saturate = 0; - $$.bits3.math.int_type = $4; - $$.bits3.math.precision = BRW_MATH_PRECISION_FULL; - $$.bits3.math.data_type = $5; - } - } - | GATEWAY - { - if (IS_GENp(5)) { - $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_GATEWAY; - $$.bits3.generic_gen5.header_present = 0; /* ??? */ - } else { - $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_GATEWAY; - } - } - | READ LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA - INTEGER RPAREN - { - if (IS_GENx(7)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_DP_SC; - $$.bits3.generic_gen5.header_present = 1; - $$.bits3.dp_gen7.binding_table_index = $3; - $$.bits3.dp_gen7.msg_control = $7; - $$.bits3.dp_gen7.msg_type = $9; - } else if (IS_GENx(6)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_DP_SC; - $$.bits3.generic_gen5.header_present = 1; - $$.bits3.dp_read_gen6.binding_table_index = $3; - $$.bits3.dp_read_gen6.msg_control = $7; - $$.bits3.dp_read_gen6.msg_type = $9; - } else if (IS_GENx(5)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_DATAPORT_READ; - $$.bits3.generic_gen5.header_present = 1; - $$.bits3.dp_read_gen5.binding_table_index = $3; - $$.bits3.dp_read_gen5.target_cache = $5; - $$.bits3.dp_read_gen5.msg_control = $7; - $$.bits3.dp_read_gen5.msg_type = $9; - } else { - $$.bits3.generic.msg_target = - BRW_MESSAGE_TARGET_DATAPORT_READ; - $$.bits3.dp_read.binding_table_index = $3; - $$.bits3.dp_read.target_cache = $5; - $$.bits3.dp_read.msg_control = $7; - $$.bits3.dp_read.msg_type = $9; - } - } - | WRITE LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA - INTEGER RPAREN - { - if (IS_GENx(7)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_DP_RC; - $$.bits3.generic_gen5.header_present = 1; - $$.bits3.dp_gen7.binding_table_index = $3; - $$.bits3.dp_gen7.msg_control = $5; - $$.bits3.dp_gen7.msg_type = $7; - } else if (IS_GENx(6)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_DP_RC; - /* Sandybridge supports headerlesss message for render target write. - * Currently the GFX assembler doesn't support it. so the program must provide - * message header - */ - $$.bits3.generic_gen5.header_present = 1; - $$.bits3.dp_write_gen6.binding_table_index = $3; - $$.bits3.dp_write_gen6.msg_control = $5; - $$.bits3.dp_write_gen6.msg_type = $7; - $$.bits3.dp_write_gen6.send_commit_msg = $9; - } else if (IS_GENx(5)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_DATAPORT_WRITE; - $$.bits3.generic_gen5.header_present = 1; - $$.bits3.dp_write_gen5.binding_table_index = $3; - $$.bits3.dp_write_gen5.pixel_scoreboard_clear = ($5 & 0x8) >> 3; - $$.bits3.dp_write_gen5.msg_control = $5 & 0x7; - $$.bits3.dp_write_gen5.msg_type = $7; - $$.bits3.dp_write_gen5.send_commit_msg = $9; - } else { - $$.bits3.generic.msg_target = - BRW_MESSAGE_TARGET_DATAPORT_WRITE; - $$.bits3.dp_write.binding_table_index = $3; - /* The msg control field of brw_struct.h is split into - * msg control and pixel_scoreboard_clear, even though - * pixel_scoreboard_clear isn't common to all write messages. - */ - $$.bits3.dp_write.pixel_scoreboard_clear = ($5 & 0x8) >> 3; - $$.bits3.dp_write.msg_control = $5 & 0x7; - $$.bits3.dp_write.msg_type = $7; - $$.bits3.dp_write.send_commit_msg = $9; - } - } - | WRITE LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA - INTEGER COMMA INTEGER RPAREN - { - if (IS_GENx(7)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_DP_RC; - $$.bits3.generic_gen5.header_present = ($11 != 0); - $$.bits3.dp_gen7.binding_table_index = $3; - $$.bits3.dp_gen7.msg_control = $5; - $$.bits3.dp_gen7.msg_type = $7; - } else if (IS_GENx(6)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_DP_RC; - $$.bits3.generic_gen5.header_present = ($11 != 0); - $$.bits3.dp_write_gen6.binding_table_index = $3; - $$.bits3.dp_write_gen6.msg_control = $5; - $$.bits3.dp_write_gen6.msg_type = $7; - $$.bits3.dp_write_gen6.send_commit_msg = $9; - } else if (IS_GENx(5)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_DATAPORT_WRITE; - $$.bits3.generic_gen5.header_present = ($11 != 0); - $$.bits3.dp_write_gen5.binding_table_index = $3; - $$.bits3.dp_write_gen5.pixel_scoreboard_clear = ($5 & 0x8) >> 3; - $$.bits3.dp_write_gen5.msg_control = $5 & 0x7; - $$.bits3.dp_write_gen5.msg_type = $7; - $$.bits3.dp_write_gen5.send_commit_msg = $9; - } else { - $$.bits3.generic.msg_target = - BRW_MESSAGE_TARGET_DATAPORT_WRITE; - $$.bits3.dp_write.binding_table_index = $3; - /* The msg control field of brw_struct.h is split into - * msg control and pixel_scoreboard_clear, even though - * pixel_scoreboard_clear isn't common to all write messages. - */ - $$.bits3.dp_write.pixel_scoreboard_clear = ($5 & 0x8) >> 3; - $$.bits3.dp_write.msg_control = $5 & 0x7; - $$.bits3.dp_write.msg_type = $7; - $$.bits3.dp_write.send_commit_msg = $9; - } - } - | URB INTEGER urb_swizzle urb_allocate urb_used urb_complete - { - $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_URB; - if (IS_GENp(5)) { - $$.bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB; - $$.bits3.generic_gen5.header_present = 1; - $$.bits3.urb_gen5.opcode = BRW_URB_OPCODE_WRITE; - $$.bits3.urb_gen5.offset = $2; - $$.bits3.urb_gen5.swizzle_control = $3; - $$.bits3.urb_gen5.pad = 0; - $$.bits3.urb_gen5.allocate = $4; - $$.bits3.urb_gen5.used = $5; - $$.bits3.urb_gen5.complete = $6; - } else { - $$.bits3.generic.msg_target = BRW_MESSAGE_TARGET_URB; - $$.bits3.urb.opcode = BRW_URB_OPCODE_WRITE; - $$.bits3.urb.offset = $2; - $$.bits3.urb.swizzle_control = $3; - $$.bits3.urb.pad = 0; - $$.bits3.urb.allocate = $4; - $$.bits3.urb.used = $5; - $$.bits3.urb.complete = $6; - } - } - | THREAD_SPAWNER LPAREN INTEGER COMMA INTEGER COMMA - INTEGER RPAREN - { - $$.bits3.generic.msg_target = - BRW_MESSAGE_TARGET_THREAD_SPAWNER; - if (IS_GENp(5)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_THREAD_SPAWNER; - $$.bits3.generic_gen5.header_present = 0; - $$.bits3.thread_spawner_gen5.opcode = $3; - $$.bits3.thread_spawner_gen5.requester_type = $5; - $$.bits3.thread_spawner_gen5.resource_select = $7; - } else { - $$.bits3.generic.msg_target = - BRW_MESSAGE_TARGET_THREAD_SPAWNER; - $$.bits3.thread_spawner.opcode = $3; - $$.bits3.thread_spawner.requester_type = $5; - $$.bits3.thread_spawner.resource_select = $7; - } - } - | VME LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA INTEGER RPAREN - { - $$.bits3.generic.msg_target = - BRW_MESSAGE_TARGET_VME; - - if (IS_GENp(6)) { - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_VME; - $$.bits3.vme_gen6.binding_table_index = $3; - $$.bits3.vme_gen6.search_path_index = $5; - $$.bits3.vme_gen6.lut_subindex = $7; - $$.bits3.vme_gen6.message_type = $9; - $$.bits3.generic_gen5.header_present = 1; - } else { - fprintf (stderr, "Gen6- doesn't have vme function\n"); - YYERROR; - } - } - | CRE LPAREN INTEGER COMMA INTEGER RPAREN - { - if (gen_level < 75) { - fprintf (stderr, "Below Gen7.5 doesn't have CRE function\n"); - YYERROR; - } - $$.bits3.generic.msg_target = - BRW_MESSAGE_TARGET_CRE; - - $$.bits2.send_gen5.sfid = - BRW_MESSAGE_TARGET_CRE; - $$.bits3.cre_gen75.binding_table_index = $3; - $$.bits3.cre_gen75.message_type = $5; - $$.bits3.generic_gen5.header_present = 1; - } - - | DATA_PORT LPAREN INTEGER COMMA INTEGER COMMA INTEGER COMMA - INTEGER COMMA INTEGER COMMA INTEGER RPAREN - { - $$.bits2.send_gen5.sfid = $3; - $$.bits3.generic_gen5.header_present = ($13 != 0); - - if (IS_GENp(7)) { - if ($3 != BRW_MESSAGE_TARGET_DP_SC && - $3 != BRW_MESSAGE_TARGET_DP_RC && - $3 != BRW_MESSAGE_TARGET_DP_CC && - $3 != BRW_MESSAGE_TARGET_DP_DC) { - fprintf (stderr, "error: wrong cache type\n"); - YYERROR; - } - - $$.bits3.dp_gen7.category = $11; - $$.bits3.dp_gen7.binding_table_index = $9; - $$.bits3.dp_gen7.msg_control = $7; - $$.bits3.dp_gen7.msg_type = $5; - } else if (IS_GENx(6)) { - if ($3 != BRW_MESSAGE_TARGET_DP_SC && - $3 != BRW_MESSAGE_TARGET_DP_RC && - $3 != BRW_MESSAGE_TARGET_DP_CC) { - fprintf (stderr, "error: wrong cache type\n"); - YYERROR; - } - - $$.bits3.dp_gen6.send_commit_msg = $11; - $$.bits3.dp_gen6.binding_table_index = $9; - $$.bits3.dp_gen6.msg_control = $7; - $$.bits3.dp_gen6.msg_type = $5; - } else if (!IS_GENp(5)) { - fprintf (stderr, "Gen6- doesn't support data port for sampler/render/constant/data cache\n"); - YYERROR; - } - } -; - -urb_allocate: ALLOCATE { $$ = 1; } - | /* empty */ { $$ = 0; } -; - -urb_used: USED { $$ = 1; } - | /* empty */ { $$ = 0; } -; - -urb_complete: COMPLETE { $$ = 1; } - | /* empty */ { $$ = 0; } -; - -urb_swizzle: TRANSPOSE { $$ = BRW_URB_SWIZZLE_TRANSPOSE; } - | INTERLEAVE { $$ = BRW_URB_SWIZZLE_INTERLEAVE; } - | /* empty */ { $$ = BRW_URB_SWIZZLE_NONE; } -; - -sampler_datatype: - TYPE_F - | TYPE_UD - | TYPE_D -; - -math_function: INV | LOG | EXP | SQRT | POW | SIN | COS | SINCOS | INTDIV - | INTMOD | INTDIVMOD -; - -math_signed: /* empty */ { $$ = 0; } - | SIGNED { $$ = 1; } -; - -math_scalar: /* empty */ { $$ = 0; } - | SCALAR { $$ = 1; } -; - -/* 1.4.2: Destination register */ - -dst: dstoperand | dstoperandex -; - -dstoperand: symbol_reg dstregion - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = $1.base.reg_file; - $$.reg_nr = $1.base.reg_nr; - $$.subreg_nr = $1.base.subreg_nr; - if ($2 == DEFAULT_DSTREGION) { - $$.horiz_stride = $1.dst_region; - } else { - $$.horiz_stride = $2; - } - $$.reg_type = $1.type; - } - | dstreg dstregion writemask regtype - { - /* Returns an instruction with just the destination register - * filled in. - */ - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = $1.reg_file; - $$.reg_nr = $1.reg_nr; - $$.subreg_nr = $1.subreg_nr; - $$.address_mode = $1.address_mode; - $$.address_subreg_nr = $1.address_subreg_nr; - $$.indirect_offset = $1.indirect_offset; - $$.horiz_stride = $2; - $$.writemask_set = $3.writemask_set; - $$.writemask = $3.writemask; - $$.reg_type = $4.type; - } -; - -/* The dstoperandex returns an instruction with just the destination register - * filled in. - */ -dstoperandex: dstoperandex_typed dstregion regtype - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = $1.reg_file; - $$.reg_nr = $1.reg_nr; - $$.subreg_nr = $1.subreg_nr; - $$.horiz_stride = $2; - $$.reg_type = $3.type; - } - | maskstackreg - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = $1.reg_file; - $$.reg_nr = $1.reg_nr; - $$.subreg_nr = $1.subreg_nr; - $$.horiz_stride = 1; - $$.reg_type = BRW_REGISTER_TYPE_UW; - } - | controlreg - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = $1.reg_file; - $$.reg_nr = $1.reg_nr; - $$.subreg_nr = $1.subreg_nr; - $$.horiz_stride = 1; - $$.reg_type = BRW_REGISTER_TYPE_UD; - } - | ipreg - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = $1.reg_file; - $$.reg_nr = $1.reg_nr; - $$.subreg_nr = $1.subreg_nr; - $$.horiz_stride = 1; - $$.reg_type = BRW_REGISTER_TYPE_UD; - } - | nullreg dstregion regtype - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = $1.reg_file; - $$.reg_nr = $1.reg_nr; - $$.subreg_nr = $1.subreg_nr; - $$.horiz_stride = $2; - $$.reg_type = $3.type; - } -; - -dstoperandex_typed: accreg | flagreg | addrreg | maskreg -; - -symbol_reg: STRING %prec STR_SYMBOL_REG - { - struct declared_register *dcl_reg = find_register($1); - - if (dcl_reg == NULL) { - fprintf(stderr, "can't find register %s\n", $1); - YYERROR; - } - - memcpy(&$$, dcl_reg, sizeof(*dcl_reg)); - free($1); // $1 has been malloc'ed by strdup - } - | symbol_reg_p - { - $$=$1; - } -; - -symbol_reg_p: STRING LPAREN exp RPAREN - { - struct declared_register *dcl_reg = find_register($1); - - if (dcl_reg == NULL) { - fprintf(stderr, "can't find register %s\n", $1); - YYERROR; - } - - memcpy(&$$, dcl_reg, sizeof(*dcl_reg)); - $$.base.reg_nr += $3; - free($1); - } - | STRING LPAREN exp COMMA exp RPAREN - { - struct declared_register *dcl_reg = find_register($1); - - if (dcl_reg == NULL) { - fprintf(stderr, "can't find register %s\n", $1); - YYERROR; - } - - memcpy(&$$, dcl_reg, sizeof(*dcl_reg)); - $$.base.reg_nr += $3; - $$.base.subreg_nr += $5; - if(advanced_flag) { - $$.base.reg_nr += $$.base.subreg_nr / (32 / get_type_size(dcl_reg->type)); - $$.base.subreg_nr = $$.base.subreg_nr % (32 / get_type_size(dcl_reg->type)); - } else { - $$.base.reg_nr += $$.base.subreg_nr / 32; - $$.base.subreg_nr = $$.base.subreg_nr % 32; - } - free($1); - } -; -/* Returns a partially complete destination register consisting of the - * direct or indirect register addressing fields, but not stride or writemask. - */ -dstreg: directgenreg - { - memset (&$$, '\0', sizeof ($$)); - $$.address_mode = BRW_ADDRESS_DIRECT; - $$.reg_file = $1.reg_file; - $$.reg_nr = $1.reg_nr; - $$.subreg_nr = $1.subreg_nr; - } - | directmsgreg - { - memset (&$$, '\0', sizeof ($$)); - $$.address_mode = BRW_ADDRESS_DIRECT; - $$.reg_file = $1.reg_file; - $$.reg_nr = $1.reg_nr; - $$.subreg_nr = $1.subreg_nr; - } - | indirectgenreg - { - memset (&$$, '\0', sizeof ($$)); - $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; - $$.reg_file = $1.reg_file; - $$.address_subreg_nr = $1.address_subreg_nr; - $$.indirect_offset = $1.indirect_offset; - } - | indirectmsgreg - { - memset (&$$, '\0', sizeof ($$)); - $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; - $$.reg_file = $1.reg_file; - $$.address_subreg_nr = $1.address_subreg_nr; - $$.indirect_offset = $1.indirect_offset; - } -; - -/* 1.4.3: Source register */ -srcaccimm: srcacc | imm32reg -; - -srcacc: directsrcaccoperand | indirectsrcoperand -; - -srcimm: directsrcoperand | indirectsrcoperand| imm32reg -; - -imm32reg: imm32 srcimmtype - { - union { - int i; - float f; - } intfloat; - uint32_t d; - - switch ($2) { - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_D: - case BRW_REGISTER_TYPE_V: - case BRW_REGISTER_TYPE_VF: - switch ($1.r) { - case imm32_d: - d = $1.u.d; - break; - default: - fprintf (stderr, "%d: non-int D/UD/V/VF representation: %d,type=%d\n", yylineno, $1.r, $2); - YYERROR; - } - break; - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_W: - switch ($1.r) { - case imm32_d: - d = $1.u.d; - break; - default: - fprintf (stderr, "non-int W/UW representation\n"); - YYERROR; - } - d &= 0xffff; - d |= d << 16; - break; - case BRW_REGISTER_TYPE_F: - switch ($1.r) { - case imm32_f: - intfloat.f = $1.u.f; - break; - case imm32_d: - intfloat.f = (float) $1.u.d; - break; - default: - fprintf (stderr, "non-float F representation\n"); - YYERROR; - } - d = intfloat.i; - break; -#if 0 - case BRW_REGISTER_TYPE_VF: - fprintf (stderr, "Immediate type VF not supported yet\n"); - YYERROR; -#endif - default: - fprintf(stderr, "unknown immediate type %d\n", $2); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_IMMEDIATE_VALUE; - $$.reg_type = $2; - $$.imm32 = d; - } -; - -directsrcaccoperand: directsrcoperand - | accreg region regtype - { - set_direct_src_operand(&$$, &$1, $3.type); - $$.vert_stride = $2.vert_stride; - $$.width = $2.width; - $$.horiz_stride = $2.horiz_stride; - $$.default_region = $2.is_default; - } -; - -/* Returns a source operand in the src0 fields of an instruction. */ -srcarchoperandex: srcarchoperandex_typed region regtype - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = $1.reg_file; - $$.reg_type = $3.type; - $$.subreg_nr = $1.subreg_nr; - $$.reg_nr = $1.reg_nr; - $$.vert_stride = $2.vert_stride; - $$.width = $2.width; - $$.horiz_stride = $2.horiz_stride; - $$.default_region = $2.is_default; - $$.negate = 0; - $$.abs = 0; - } - | maskstackreg - { - set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UB); - } - | controlreg - { - set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); - } -/* | statereg - { - set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); - }*/ - | notifyreg - { - set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); - } - | ipreg - { - set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); - } - | nullreg region regtype - { - if ($3.is_default) { - set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); - } else { - set_direct_src_operand(&$$, &$1, $3.type); - } - $$.default_region = 1; - } -; - -srcarchoperandex_typed: flagreg | addrreg | maskreg -; - -sendleadreg: symbol_reg - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = $1.base.reg_file; - $$.reg_nr = $1.base.reg_nr; - $$.subreg_nr = $1.base.subreg_nr; - } - | directgenreg | directmsgreg -; - -src: directsrcoperand | indirectsrcoperand -; - -directsrcoperand: negate abs symbol_reg region regtype - { - memset (&$$, '\0', sizeof ($$)); - $$.address_mode = BRW_ADDRESS_DIRECT; - $$.reg_file = $3.base.reg_file; - $$.reg_nr = $3.base.reg_nr; - $$.subreg_nr = $3.base.subreg_nr; - if ($5.is_default) { - $$.reg_type = $3.type; - } else { - $$.reg_type = $5.type; - } - if ($4.is_default) { - $$.vert_stride = $3.src_region.vert_stride; - $$.width = $3.src_region.width; - $$.horiz_stride = $3.src_region.horiz_stride; - } else { - $$.vert_stride = $4.vert_stride; - $$.width = $4.width; - $$.horiz_stride = $4.horiz_stride; - } - $$.negate = $1; - $$.abs = $2; - } - | statereg region regtype - { - if($2.is_default ==1 && $3.is_default == 1) - { - set_direct_src_operand(&$$, &$1, BRW_REGISTER_TYPE_UD); - } - else{ - memset (&$$, '\0', sizeof ($$)); - $$.address_mode = BRW_ADDRESS_DIRECT; - $$.reg_file = $1.reg_file; - $$.reg_nr = $1.reg_nr; - $$.subreg_nr = $1.subreg_nr; - $$.vert_stride = $2.vert_stride; - $$.width = $2.width; - $$.horiz_stride = $2.horiz_stride; - $$.reg_type = $3.type; - } - } - | negate abs directgenreg region regtype swizzle - { - memset (&$$, '\0', sizeof ($$)); - $$.address_mode = BRW_ADDRESS_DIRECT; - $$.reg_file = $3.reg_file; - $$.reg_nr = $3.reg_nr; - $$.subreg_nr = $3.subreg_nr; - $$.reg_type = $5.type; - $$.vert_stride = $4.vert_stride; - $$.width = $4.width; - $$.horiz_stride = $4.horiz_stride; - $$.default_region = $4.is_default; - $$.negate = $1; - $$.abs = $2; - $$.swizzle_set = $6.swizzle_set; - $$.swizzle_x = $6.swizzle_x; - $$.swizzle_y = $6.swizzle_y; - $$.swizzle_z = $6.swizzle_z; - $$.swizzle_w = $6.swizzle_w; - } - | srcarchoperandex -; - -indirectsrcoperand: - negate abs indirectgenreg indirectregion regtype swizzle - { - memset (&$$, '\0', sizeof ($$)); - $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; - $$.reg_file = $3.reg_file; - $$.address_subreg_nr = $3.address_subreg_nr; - $$.indirect_offset = $3.indirect_offset; - $$.reg_type = $5.type; - $$.vert_stride = $4.vert_stride; - $$.width = $4.width; - $$.horiz_stride = $4.horiz_stride; - $$.negate = $1; - $$.abs = $2; - $$.swizzle_set = $6.swizzle_set; - $$.swizzle_x = $6.swizzle_x; - $$.swizzle_y = $6.swizzle_y; - $$.swizzle_z = $6.swizzle_z; - $$.swizzle_w = $6.swizzle_w; - } -; - -/* 1.4.4: Address Registers */ -/* Returns a partially-completed indirect_reg consisting of the address - * register fields for register-indirect access. - */ -addrparam: addrreg COMMA immaddroffset - { - if ($3 < -512 || $3 > 511) { - fprintf(stderr, "Address immediate offset %d out of" - "range %d\n", $3, yylineno); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.address_subreg_nr = $1.subreg_nr; - $$.indirect_offset = $3; - } - | addrreg - { - memset (&$$, '\0', sizeof ($$)); - $$.address_subreg_nr = $1.subreg_nr; - $$.indirect_offset = 0; - } -; - -/* The immaddroffset provides an immediate offset value added to the addresses - * from the address register in register-indirect register access. - */ -immaddroffset: /* empty */ { $$ = 0; } - | exp -; - - -/* 1.4.5: Register files and register numbers */ -subregnum: DOT exp - { - $$ = $2; - } - | %prec SUBREGNUM - { - /* Default to subreg 0 if unspecified. */ - $$ = 0; - } -; - -directgenreg: GENREG subregnum - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_GENERAL_REGISTER_FILE; - $$.reg_nr = $1; - $$.subreg_nr = $2; - } -; - -indirectgenreg: GENREGFILE LSQUARE addrparam RSQUARE - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_GENERAL_REGISTER_FILE; - $$.address_subreg_nr = $3.address_subreg_nr; - $$.indirect_offset = $3.indirect_offset; - } -; - -directmsgreg: MSGREG subregnum - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_MESSAGE_REGISTER_FILE; - $$.reg_nr = $1; - $$.subreg_nr = $2; - } -; - -indirectmsgreg: MSGREGFILE LSQUARE addrparam RSQUARE - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_MESSAGE_REGISTER_FILE; - $$.address_subreg_nr = $3.address_subreg_nr; - $$.indirect_offset = $3.indirect_offset; - } -; - -addrreg: ADDRESSREG subregnum - { - if ($1 != 0) { - fprintf(stderr, - "address register number %d out of range", $1); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_ADDRESS | $1; - $$.subreg_nr = $2; - } -; - -accreg: ACCREG subregnum - { - if ($1 > 1) { - fprintf(stderr, - "accumulator register number %d out of range", $1); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_ACCUMULATOR | $1; - $$.subreg_nr = $2; - } -; - -flagreg: FLAGREG subregnum - { - if ((!IS_GENp(7) && $1) > 0 || - (IS_GENp(7) && $1 > 1)) { - fprintf(stderr, - "flag register number %d out of range\n", $1); - YYERROR; - } - - if ($2 > 1) { - fprintf(stderr, - "flag subregister number %d out of range\n", $1); - YYERROR; - } - - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_FLAG | $1; - $$.subreg_nr = $2; - } -; - -maskreg: MASKREG subregnum - { - if ($1 > 0) { - fprintf(stderr, - "mask register number %d out of range", $1); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_MASK; - $$.subreg_nr = $2; - } - | mask_subreg - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_MASK; - $$.subreg_nr = $1; - } -; - -mask_subreg: AMASK | IMASK | LMASK | CMASK -; - -maskstackreg: MASKSTACKREG subregnum - { - if ($1 > 0) { - fprintf(stderr, - "mask stack register number %d out of range", $1); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_MASK_STACK; - $$.subreg_nr = $2; - } - | maskstack_subreg - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_MASK_STACK; - $$.subreg_nr = $1; - } -; - -maskstack_subreg: IMS | LMS -; - -/* -maskstackdepthreg: MASKSTACKDEPTHREG subregnum - { - if ($1 > 0) { - fprintf(stderr, - "mask stack register number %d out of range", $1); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_MASK_STACK_DEPTH; - $$.subreg_nr = $2; - } - | maskstackdepth_subreg - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_MASK_STACK_DEPTH; - $$.subreg_nr = $1; - } -; - -maskstackdepth_subreg: IMSD | LMSD -; - */ - -notifyreg: NOTIFYREG regtype - { - int num_notifyreg = (IS_GENp(6)) ? 3 : 2; - - if ($1 > num_notifyreg) { - fprintf(stderr, - "notification register number %d out of range", - $1); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - - if (IS_GENp(6)) { - $$.reg_nr = BRW_ARF_NOTIFICATION_COUNT; - $$.subreg_nr = $1; - } else { - $$.reg_nr = BRW_ARF_NOTIFICATION_COUNT | $1; - $$.subreg_nr = 0; - } - } -/* - | NOTIFYREG regtype - { - if ($1 > 1) { - fprintf(stderr, - "notification register number %d out of range", - $1); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_NOTIFICATION_COUNT; - $$.subreg_nr = 0; - } -*/ -; - -statereg: STATEREG subregnum - { - if ($1 > 0) { - fprintf(stderr, - "state register number %d out of range", $1); - YYERROR; - } - if ($2 > 1) { - fprintf(stderr, - "state subregister number %d out of range", $1); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_STATE | $1; - $$.subreg_nr = $2; - } -; - -controlreg: CONTROLREG subregnum - { - if ($1 > 0) { - fprintf(stderr, - "control register number %d out of range", $1); - YYERROR; - } - if ($2 > 2) { - fprintf(stderr, - "control subregister number %d out of range", $1); - YYERROR; - } - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_CONTROL | $1; - $$.subreg_nr = $2; - } -; - -ipreg: IPREG regtype - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_IP; - $$.subreg_nr = 0; - } -; - -nullreg: NULL_TOKEN - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_ARCHITECTURE_REGISTER_FILE; - $$.reg_nr = BRW_ARF_NULL; - $$.subreg_nr = 0; - } -; - -/* 1.4.6: Relative locations */ -relativelocation: - simple_int - { - if (($1 > 32767) || ($1 < -32768)) { - fprintf(stderr, - "error: relative offset %d out of range \n", - $1); - YYERROR; - } - - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_IMMEDIATE_VALUE; - $$.reg_type = BRW_REGISTER_TYPE_D; - $$.imm32 = $1 & 0x0000ffff; - } - | STRING - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_IMMEDIATE_VALUE; - $$.reg_type = BRW_REGISTER_TYPE_D; - $$.reloc_target = $1; - } -; - -relativelocation2: - STRING - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_IMMEDIATE_VALUE; - $$.reg_type = BRW_REGISTER_TYPE_D; - $$.reloc_target = $1; - } - | exp - { - memset (&$$, '\0', sizeof ($$)); - $$.reg_file = BRW_IMMEDIATE_VALUE; - $$.reg_type = BRW_REGISTER_TYPE_D; - $$.imm32 = $1; - } - | directgenreg region regtype - { - set_direct_src_operand(&$$, &$1, $3.type); - $$.vert_stride = $2.vert_stride; - $$.width = $2.width; - $$.horiz_stride = $2.horiz_stride; - $$.default_region = $2.is_default; - } - | symbol_reg_p - { - memset (&$$, '\0', sizeof ($$)); - $$.address_mode = BRW_ADDRESS_DIRECT; - $$.reg_file = $1.base.reg_file; - $$.reg_nr = $1.base.reg_nr; - $$.subreg_nr = $1.base.subreg_nr; - $$.reg_type = $1.type; - $$.vert_stride = $1.src_region.vert_stride; - $$.width = $1.src_region.width; - $$.horiz_stride = $1.src_region.horiz_stride; - } - | indirectgenreg indirectregion regtype - { - memset (&$$, '\0', sizeof ($$)); - $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER; - $$.reg_file = $1.reg_file; - $$.address_subreg_nr = $1.address_subreg_nr; - $$.indirect_offset = $1.indirect_offset; - $$.reg_type = $3.type; - $$.vert_stride = $2.vert_stride; - $$.width = $2.width; - $$.horiz_stride = $2.horiz_stride; - } -; - -/* 1.4.7: Regions */ -dstregion: /* empty */ - { - $$ = DEFAULT_DSTREGION; - } - |LANGLE exp RANGLE - { - /* Returns a value for a horiz_stride field of an - * instruction. - */ - if ($2 != 1 && $2 != 2 && $2 != 4) { - fprintf(stderr, "Invalid horiz size %d\n", $2); - } - $$ = ffs($2); - } -; - -region: /* empty */ - { - /* XXX is this default value correct?*/ - memset (&$$, '\0', sizeof ($$)); - $$.vert_stride = ffs(0); - $$.width = ffs(1) - 1; - $$.horiz_stride = ffs(0); - $$.is_default = 1; - } - |LANGLE exp RANGLE - { - /* XXX is this default value correct for accreg?*/ - memset (&$$, '\0', sizeof ($$)); - $$.vert_stride = ffs($2); - $$.width = ffs(1) - 1; - $$.horiz_stride = ffs(0); - } - |LANGLE exp COMMA exp COMMA exp RANGLE - { - memset (&$$, '\0', sizeof ($$)); - $$.vert_stride = ffs($2); - $$.width = ffs($4) - 1; - $$.horiz_stride = ffs($6); - } - | LANGLE exp SEMICOLON exp COMMA exp RANGLE - { - memset (&$$, '\0', sizeof ($$)); - $$.vert_stride = ffs($2); - $$.width = ffs($4) - 1; - $$.horiz_stride = ffs($6); - } - -; -/* region_wh is used in specifying indirect operands where rather than having - * a vertical stride, you use subsequent address registers to get a new base - * offset for the next row. - */ -region_wh: LANGLE exp COMMA exp RANGLE - { - memset (&$$, '\0', sizeof ($$)); - $$.vert_stride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL; - $$.width = ffs($2) - 1; - $$.horiz_stride = ffs($4); - } -; - -indirectregion: region | region_wh -; - -/* 1.4.8: Types */ - -/* regtype returns an integer register type suitable for inserting into an - * instruction. - */ -regtype: /* empty */ - { $$.type = program_defaults.register_type;$$.is_default = 1;} - | TYPE_F { $$.type = BRW_REGISTER_TYPE_F;$$.is_default = 0; } - | TYPE_UD { $$.type = BRW_REGISTER_TYPE_UD;$$.is_default = 0; } - | TYPE_D { $$.type = BRW_REGISTER_TYPE_D;$$.is_default = 0; } - | TYPE_UW { $$.type = BRW_REGISTER_TYPE_UW;$$.is_default = 0; } - | TYPE_W { $$.type = BRW_REGISTER_TYPE_W;$$.is_default = 0; } - | TYPE_UB { $$.type = BRW_REGISTER_TYPE_UB;$$.is_default = 0; } - | TYPE_B { $$.type = BRW_REGISTER_TYPE_B;$$.is_default = 0; } -; - -srcimmtype: /* empty */ - { - /* XXX change to default when pragma parse is done */ - $$ = BRW_REGISTER_TYPE_D; - } - |TYPE_F { $$ = BRW_REGISTER_TYPE_F; } - | TYPE_UD { $$ = BRW_REGISTER_TYPE_UD; } - | TYPE_D { $$ = BRW_REGISTER_TYPE_D; } - | TYPE_UW { $$ = BRW_REGISTER_TYPE_UW; } - | TYPE_W { $$ = BRW_REGISTER_TYPE_W; } - | TYPE_V { $$ = BRW_REGISTER_TYPE_V; } - | TYPE_VF { $$ = BRW_REGISTER_TYPE_VF; } -; - -/* 1.4.10: Swizzle control */ -/* Returns the swizzle control for an align16 instruction's source operand - * in the src0 fields. - */ -swizzle: /* empty */ - { - $$.swizzle_set = 0; - $$.swizzle_x = BRW_CHANNEL_X; - $$.swizzle_y = BRW_CHANNEL_Y; - $$.swizzle_z = BRW_CHANNEL_Z; - $$.swizzle_w = BRW_CHANNEL_W; - } - | DOT chansel - { - $$.swizzle_set = 1; - $$.swizzle_x = $2; - $$.swizzle_y = $2; - $$.swizzle_z = $2; - $$.swizzle_w = $2; - } - | DOT chansel chansel chansel chansel - { - $$.swizzle_set = 1; - $$.swizzle_x = $2; - $$.swizzle_y = $3; - $$.swizzle_z = $4; - $$.swizzle_w = $5; - } -; - -chansel: X | Y | Z | W -; - -/* 1.4.9: Write mask */ -/* Returns a partially completed dst_operand, with just the writemask bits - * filled out. - */ -writemask: /* empty */ - { - $$.writemask_set = 0; - $$.writemask = 0xf; - } - | DOT writemask_x writemask_y writemask_z writemask_w - { - $$.writemask_set = 1; - $$.writemask = $2 | $3 | $4 | $5; - } -; - -writemask_x: /* empty */ { $$ = 0; } - | X { $$ = 1 << BRW_CHANNEL_X; } -; - -writemask_y: /* empty */ { $$ = 0; } - | Y { $$ = 1 << BRW_CHANNEL_Y; } -; - -writemask_z: /* empty */ { $$ = 0; } - | Z { $$ = 1 << BRW_CHANNEL_Z; } -; - -writemask_w: /* empty */ { $$ = 0; } - | W { $$ = 1 << BRW_CHANNEL_W; } -; - -/* 1.4.11: Immediate values */ -imm32: exp { $$.r = imm32_d; $$.u.d = $1; } - | NUMBER { $$.r = imm32_f; $$.u.f = $1; } -; - -/* 1.4.12: Predication and modifiers */ -predicate: /* empty */ - { - $$.header.predicate_control = BRW_PREDICATE_NONE; - $$.bits2.da1.flag_reg_nr = 0; - $$.bits2.da1.flag_subreg_nr = 0; - $$.header.predicate_inverse = 0; - } - | LPAREN predstate flagreg predctrl RPAREN - { - $$.header.predicate_control = $4; - /* XXX: Should deal with erroring when the user tries to - * set a predicate for one flag register and conditional - * modification on the other flag register. - */ - $$.bits2.da1.flag_reg_nr = ($3.reg_nr & 0xF); - $$.bits2.da1.flag_subreg_nr = $3.subreg_nr; - $$.header.predicate_inverse = $2; - } -; - -predstate: /* empty */ { $$ = 0; } - | PLUS { $$ = 0; } - | MINUS { $$ = 1; } -; - -predctrl: /* empty */ { $$ = BRW_PREDICATE_NORMAL; } - | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; } - | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; } - | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; } - | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; } - | ANYV { $$ = BRW_PREDICATE_ALIGN1_ANYV; } - | ALLV { $$ = BRW_PREDICATE_ALIGN1_ALLV; } - | ANY2H { $$ = BRW_PREDICATE_ALIGN1_ANY2H; } - | ALL2H { $$ = BRW_PREDICATE_ALIGN1_ALL2H; } - | ANY4H { $$ = BRW_PREDICATE_ALIGN1_ANY4H; } - | ALL4H { $$ = BRW_PREDICATE_ALIGN1_ALL4H; } - | ANY8H { $$ = BRW_PREDICATE_ALIGN1_ANY8H; } - | ALL8H { $$ = BRW_PREDICATE_ALIGN1_ALL8H; } - | ANY16H { $$ = BRW_PREDICATE_ALIGN1_ANY16H; } - | ALL16H { $$ = BRW_PREDICATE_ALIGN1_ALL16H; } -; - -negate: /* empty */ { $$ = 0; } - | MINUS { $$ = 1; } -; - -abs: /* empty */ { $$ = 0; } - | ABS { $$ = 1; } -; - -execsize: /* empty */ %prec EMPTEXECSIZE - { - $$ = ffs(program_defaults.execute_size) - 1; - } - |LPAREN exp RPAREN - { - /* Returns a value for the execution_size field of an - * instruction. - */ - if ($2 != 1 && $2 != 2 && $2 != 4 && $2 != 8 && $2 != 16 && - $2 != 32) { - fprintf(stderr, "Invalid execution size %d\n", $2); - YYERROR; - } - $$ = ffs($2) - 1; - } -; - -saturate: /* empty */ { $$ = BRW_INSTRUCTION_NORMAL; } - | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; } -; -conditionalmodifier: condition - { - $$.cond = $1; - $$.flag_reg_nr = 0; - $$.flag_subreg_nr = -1; - } - | condition DOT flagreg - { - $$.cond = $1; - $$.flag_reg_nr = ($3.reg_nr & 0xF); - $$.flag_subreg_nr = $3.subreg_nr; - } - -condition: /* empty */ { $$ = BRW_CONDITIONAL_NONE; } - | ZERO - | EQUAL - | NOT_ZERO - | NOT_EQUAL - | GREATER - | GREATER_EQUAL - | LESS - | LESS_EQUAL - | ROUND_INCREMENT - | OVERFLOW - | UNORDERED -; - -/* 1.4.13: Instruction options */ -instoptions: /* empty */ - { memset(&$$, 0, sizeof($$)); } - | LCURLY instoption_list RCURLY - { $$ = $2; } -; - -instoption_list:instoption_list COMMA instoption - { - $$ = $1; - switch ($3) { - case ALIGN1: - $$.header.access_mode = BRW_ALIGN_1; - break; - case ALIGN16: - $$.header.access_mode = BRW_ALIGN_16; - break; - case SECHALF: - $$.header.compression_control |= BRW_COMPRESSION_2NDHALF; - break; - case COMPR: - if (!IS_GENp(6)) { - $$.header.compression_control |= - BRW_COMPRESSION_COMPRESSED; - } - break; - case SWITCH: - $$.header.thread_control |= BRW_THREAD_SWITCH; - break; - case ATOMIC: - $$.header.thread_control |= BRW_THREAD_ATOMIC; - break; - case NODDCHK: - $$.header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED; - break; - case NODDCLR: - $$.header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED; - break; - case MASK_DISABLE: - $$.header.mask_control = BRW_MASK_DISABLE; - break; - case BREAKPOINT: - $$.header.debug_control = BRW_DEBUG_BREAKPOINT; - break; - case ACCWRCTRL: - $$.header.acc_wr_control = BRW_ACCWRCTRL_ACCWRCTRL; - } - } - | instoption_list instoption - { - $$ = $1; - switch ($2) { - case ALIGN1: - $$.header.access_mode = BRW_ALIGN_1; - break; - case ALIGN16: - $$.header.access_mode = BRW_ALIGN_16; - break; - case SECHALF: - $$.header.compression_control |= BRW_COMPRESSION_2NDHALF; - break; - case COMPR: - if (!IS_GENp(6)) { - $$.header.compression_control |= - BRW_COMPRESSION_COMPRESSED; - } - break; - case SWITCH: - $$.header.thread_control |= BRW_THREAD_SWITCH; - break; - case ATOMIC: - $$.header.thread_control |= BRW_THREAD_ATOMIC; - break; - case NODDCHK: - $$.header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED; - break; - case NODDCLR: - $$.header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED; - break; - case MASK_DISABLE: - $$.header.mask_control = BRW_MASK_DISABLE; - break; - case BREAKPOINT: - $$.header.debug_control = BRW_DEBUG_BREAKPOINT; - break; - case EOT: - /* XXX: EOT shouldn't be an instoption, I don't think */ - $$.bits3.generic.end_of_thread = 1; - break; - } - } - | /* empty, header defaults to zeroes. */ - { - memset(&$$, 0, sizeof($$)); - } -; - -instoption: ALIGN1 { $$ = ALIGN1; } - | ALIGN16 { $$ = ALIGN16; } - | SECHALF { $$ = SECHALF; } - | COMPR { $$ = COMPR; } - | SWITCH { $$ = SWITCH; } - | ATOMIC { $$ = ATOMIC; } - | NODDCHK { $$ = NODDCHK; } - | NODDCLR { $$ = NODDCLR; } - | MASK_DISABLE { $$ = MASK_DISABLE; } - | BREAKPOINT { $$ = BREAKPOINT; } - | ACCWRCTRL { $$ = ACCWRCTRL; } - | EOT { $$ = EOT; } -; - -%% -extern int yylineno; -extern char *input_filename; - -int errors; - -void yyerror (char *msg) -{ - fprintf(stderr, "%s: %d: %s at \"%s\"\n", - input_filename, yylineno, msg, lex_text()); - ++errors; -} - -static int get_type_size(GLuint type) -{ - int size = 1; - - switch (type) { - case BRW_REGISTER_TYPE_F: - case BRW_REGISTER_TYPE_UD: - case BRW_REGISTER_TYPE_D: - size = 4; - break; - - case BRW_REGISTER_TYPE_UW: - case BRW_REGISTER_TYPE_W: - size = 2; - break; - - case BRW_REGISTER_TYPE_UB: - case BRW_REGISTER_TYPE_B: - size = 1; - break; - - default: - assert(0); - size = 1; - break; - } - - return size; -} - -static int get_subreg_address(GLuint regfile, GLuint type, GLuint subreg, GLuint address_mode) -{ - int unit_size = 1; - - if (address_mode == BRW_ADDRESS_DIRECT) { - if (advanced_flag == 1) { - if ((regfile == BRW_GENERAL_REGISTER_FILE || - regfile == BRW_MESSAGE_REGISTER_FILE || - regfile == BRW_ARCHITECTURE_REGISTER_FILE)) { - - unit_size = get_type_size(type); - } - } - } else { - unit_size = 1; - } - - return subreg * unit_size; -} - -/* only used in indirect address mode. - * input: sub-register number of an address register - * output: the value of AddrSubRegNum in the instruction binary code - * - * input output(advanced_flag==0) output(advanced_flag==1) - * a0.0 0 0 - * a0.1 invalid input 1 - * a0.2 1 2 - * a0.3 invalid input 3 - * a0.4 2 4 - * a0.5 invalid input 5 - * a0.6 3 6 - * a0.7 invalid input 7 - * a0.8 4 invalid input - * a0.10 5 invalid input - * a0.12 6 invalid input - * a0.14 7 invalid input - */ -static int get_indirect_subreg_address(GLuint subreg) -{ - return advanced_flag == 0 ? subreg / 2 : subreg; -} - -static void reset_instruction_src_region(struct brw_instruction *instr, - struct src_operand *src) -{ - if (!src->default_region) - return; - - if (src->reg_file == BRW_ARCHITECTURE_REGISTER_FILE && - ((src->reg_nr & 0xF0) == BRW_ARF_ADDRESS)) { - src->vert_stride = ffs(0); - src->width = ffs(1) - 1; - src->horiz_stride = ffs(0); - } else if (src->reg_file == BRW_ARCHITECTURE_REGISTER_FILE && - ((src->reg_nr & 0xF0) == BRW_ARF_ACCUMULATOR)) { - int horiz_stride = 1, width, vert_stride; - if (instr->header.compression_control == BRW_COMPRESSION_COMPRESSED) { - width = 16; - } else { - width = 8; - } - - if (width > (1 << instr->header.execution_size)) - width = (1 << instr->header.execution_size); - - vert_stride = horiz_stride * width; - src->vert_stride = ffs(vert_stride); - src->width = ffs(width) - 1; - src->horiz_stride = ffs(horiz_stride); - } else if ((src->reg_file == BRW_ARCHITECTURE_REGISTER_FILE) && - (src->reg_nr == BRW_ARF_NULL) && - (instr->header.opcode == BRW_OPCODE_SEND)) { - src->vert_stride = ffs(8); - src->width = ffs(8) - 1; - src->horiz_stride = ffs(1); - } else { - - int horiz_stride = 1, width, vert_stride; - - if (instr->header.execution_size == 0) { /* scalar */ - horiz_stride = 0; - width = 1; - vert_stride = 0; - } else { - if ((instr->header.opcode == BRW_OPCODE_MUL) || - (instr->header.opcode == BRW_OPCODE_MAC) || - (instr->header.opcode == BRW_OPCODE_CMP) || - (instr->header.opcode == BRW_OPCODE_ASR) || - (instr->header.opcode == BRW_OPCODE_ADD) || - (instr->header.opcode == BRW_OPCODE_SHL)) { - horiz_stride = 0; - width = 1; - vert_stride = 0; - } else { - width = (1 << instr->header.execution_size) / horiz_stride; - vert_stride = horiz_stride * width; - - if (get_type_size(src->reg_type) * (width + src->subreg_nr) > 32) { - horiz_stride = 0; - width = 1; - vert_stride = 0; - } - } - } - - src->vert_stride = ffs(vert_stride); - src->width = ffs(width) - 1; - src->horiz_stride = ffs(horiz_stride); - } -} - -/** - * Fills in the destination register information in instr from the bits in dst. - */ -int set_instruction_dest(struct brw_instruction *instr, - struct dst_operand *dest) -{ - if (dest->horiz_stride == DEFAULT_DSTREGION) - dest->horiz_stride = ffs(1); - if (dest->address_mode == BRW_ADDRESS_DIRECT && - instr->header.access_mode == BRW_ALIGN_1) { - instr->bits1.da1.dest_reg_file = dest->reg_file; - instr->bits1.da1.dest_reg_type = dest->reg_type; - instr->bits1.da1.dest_subreg_nr = get_subreg_address(dest->reg_file, dest->reg_type, dest->subreg_nr, dest->address_mode); - instr->bits1.da1.dest_reg_nr = dest->reg_nr; - instr->bits1.da1.dest_horiz_stride = dest->horiz_stride; - instr->bits1.da1.dest_address_mode = dest->address_mode; - if (dest->writemask_set) { - fprintf(stderr, "error: write mask set in align1 " - "instruction\n"); - return 1; - } - } else if (dest->address_mode == BRW_ADDRESS_DIRECT) { - instr->bits1.da16.dest_reg_file = dest->reg_file; - instr->bits1.da16.dest_reg_type = dest->reg_type; - instr->bits1.da16.dest_subreg_nr = get_subreg_address(dest->reg_file, dest->reg_type, dest->subreg_nr, dest->address_mode); - instr->bits1.da16.dest_reg_nr = dest->reg_nr; - instr->bits1.da16.dest_address_mode = dest->address_mode; - instr->bits1.da16.dest_horiz_stride = ffs(1); - instr->bits1.da16.dest_writemask = dest->writemask; - } else if (instr->header.access_mode == BRW_ALIGN_1) { - instr->bits1.ia1.dest_reg_file = dest->reg_file; - instr->bits1.ia1.dest_reg_type = dest->reg_type; - instr->bits1.ia1.dest_subreg_nr = get_indirect_subreg_address(dest->address_subreg_nr); - instr->bits1.ia1.dest_horiz_stride = dest->horiz_stride; - instr->bits1.ia1.dest_indirect_offset = dest->indirect_offset; - instr->bits1.ia1.dest_address_mode = dest->address_mode; - if (dest->writemask_set) { - fprintf(stderr, "error: write mask set in align1 " - "instruction\n"); - return 1; - } - } else { - instr->bits1.ia16.dest_reg_file = dest->reg_file; - instr->bits1.ia16.dest_reg_type = dest->reg_type; - instr->bits1.ia16.dest_subreg_nr = get_indirect_subreg_address(dest->address_subreg_nr); - instr->bits1.ia16.dest_writemask = dest->writemask; - instr->bits1.ia16.dest_horiz_stride = ffs(1); - instr->bits1.ia16.dest_indirect_offset = (dest->indirect_offset >> 4); /* half register aligned */ - instr->bits1.ia16.dest_address_mode = dest->address_mode; - } - - return 0; -} - -/* Sets the first source operand for the instruction. Returns 0 on success. */ -int set_instruction_src0(struct brw_instruction *instr, - struct src_operand *src) -{ - if (advanced_flag) { - reset_instruction_src_region(instr, src); - } - instr->bits1.da1.src0_reg_file = src->reg_file; - instr->bits1.da1.src0_reg_type = src->reg_type; - if (src->reg_file == BRW_IMMEDIATE_VALUE) { - instr->bits3.ud = src->imm32; - } else if (src->address_mode == BRW_ADDRESS_DIRECT) { - if (instr->header.access_mode == BRW_ALIGN_1) { - instr->bits2.da1.src0_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode); - instr->bits2.da1.src0_reg_nr = src->reg_nr; - instr->bits2.da1.src0_vert_stride = src->vert_stride; - instr->bits2.da1.src0_width = src->width; - instr->bits2.da1.src0_horiz_stride = src->horiz_stride; - instr->bits2.da1.src0_negate = src->negate; - instr->bits2.da1.src0_abs = src->abs; - instr->bits2.da1.src0_address_mode = src->address_mode; - if (src->swizzle_set) { - fprintf(stderr, "error: swizzle bits set in align1 " - "instruction\n"); - return 1; - } - } else { - instr->bits2.da16.src0_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode); - instr->bits2.da16.src0_reg_nr = src->reg_nr; - instr->bits2.da16.src0_vert_stride = src->vert_stride; - instr->bits2.da16.src0_negate = src->negate; - instr->bits2.da16.src0_abs = src->abs; - instr->bits2.da16.src0_swz_x = src->swizzle_x; - instr->bits2.da16.src0_swz_y = src->swizzle_y; - instr->bits2.da16.src0_swz_z = src->swizzle_z; - instr->bits2.da16.src0_swz_w = src->swizzle_w; - instr->bits2.da16.src0_address_mode = src->address_mode; - } - } else { - if (instr->header.access_mode == BRW_ALIGN_1) { - instr->bits2.ia1.src0_indirect_offset = src->indirect_offset; - instr->bits2.ia1.src0_subreg_nr = get_indirect_subreg_address(src->address_subreg_nr); - instr->bits2.ia1.src0_abs = src->abs; - instr->bits2.ia1.src0_negate = src->negate; - instr->bits2.ia1.src0_address_mode = src->address_mode; - instr->bits2.ia1.src0_horiz_stride = src->horiz_stride; - instr->bits2.ia1.src0_width = src->width; - instr->bits2.ia1.src0_vert_stride = src->vert_stride; - if (src->swizzle_set) { - fprintf(stderr, "error: swizzle bits set in align1 " - "instruction\n"); - return 1; - } - } else { - instr->bits2.ia16.src0_swz_x = src->swizzle_x; - instr->bits2.ia16.src0_swz_y = src->swizzle_y; - instr->bits2.ia16.src0_indirect_offset = (src->indirect_offset >> 4); /* half register aligned */ - instr->bits2.ia16.src0_subreg_nr = get_indirect_subreg_address(src->address_subreg_nr); - instr->bits2.ia16.src0_abs = src->abs; - instr->bits2.ia16.src0_negate = src->negate; - instr->bits2.ia16.src0_address_mode = src->address_mode; - instr->bits2.ia16.src0_swz_z = src->swizzle_z; - instr->bits2.ia16.src0_swz_w = src->swizzle_w; - instr->bits2.ia16.src0_vert_stride = src->vert_stride; - } - } - - return 0; -} - -/* Sets the second source operand for the instruction. Returns 0 on success. - */ -int set_instruction_src1(struct brw_instruction *instr, - struct src_operand *src) -{ - if (advanced_flag) { - reset_instruction_src_region(instr, src); - } - instr->bits1.da1.src1_reg_file = src->reg_file; - instr->bits1.da1.src1_reg_type = src->reg_type; - if (src->reg_file == BRW_IMMEDIATE_VALUE) { - instr->bits3.ud = src->imm32; - } else if (src->address_mode == BRW_ADDRESS_DIRECT) { - if (instr->header.access_mode == BRW_ALIGN_1) { - instr->bits3.da1.src1_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode); - instr->bits3.da1.src1_reg_nr = src->reg_nr; - instr->bits3.da1.src1_vert_stride = src->vert_stride; - instr->bits3.da1.src1_width = src->width; - instr->bits3.da1.src1_horiz_stride = src->horiz_stride; - instr->bits3.da1.src1_negate = src->negate; - instr->bits3.da1.src1_abs = src->abs; - instr->bits3.da1.src1_address_mode = src->address_mode; - /* XXX why? - if (src->address_mode != BRW_ADDRESS_DIRECT) { - fprintf(stderr, "error: swizzle bits set in align1 " - "instruction\n"); - return 1; - } - */ - if (src->swizzle_set) { - fprintf(stderr, "error: swizzle bits set in align1 " - "instruction\n"); - return 1; - } - } else { - instr->bits3.da16.src1_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode); - instr->bits3.da16.src1_reg_nr = src->reg_nr; - instr->bits3.da16.src1_vert_stride = src->vert_stride; - instr->bits3.da16.src1_negate = src->negate; - instr->bits3.da16.src1_abs = src->abs; - instr->bits3.da16.src1_swz_x = src->swizzle_x; - instr->bits3.da16.src1_swz_y = src->swizzle_y; - instr->bits3.da16.src1_swz_z = src->swizzle_z; - instr->bits3.da16.src1_swz_w = src->swizzle_w; - instr->bits3.da16.src1_address_mode = src->address_mode; - if (src->address_mode != BRW_ADDRESS_DIRECT) { - fprintf(stderr, "error: swizzle bits set in align1 " - "instruction\n"); - return 1; - } - } - } else { - if (instr->header.access_mode == BRW_ALIGN_1) { - instr->bits3.ia1.src1_indirect_offset = src->indirect_offset; - instr->bits3.ia1.src1_subreg_nr = get_indirect_subreg_address(src->address_subreg_nr); - instr->bits3.ia1.src1_abs = src->abs; - instr->bits3.ia1.src1_negate = src->negate; - instr->bits3.ia1.src1_address_mode = src->address_mode; - instr->bits3.ia1.src1_horiz_stride = src->horiz_stride; - instr->bits3.ia1.src1_width = src->width; - instr->bits3.ia1.src1_vert_stride = src->vert_stride; - if (src->swizzle_set) { - fprintf(stderr, "error: swizzle bits set in align1 " - "instruction\n"); - return 1; - } - } else { - instr->bits3.ia16.src1_swz_x = src->swizzle_x; - instr->bits3.ia16.src1_swz_y = src->swizzle_y; - instr->bits3.ia16.src1_indirect_offset = (src->indirect_offset >> 4); /* half register aligned */ - instr->bits3.ia16.src1_subreg_nr = get_indirect_subreg_address(src->address_subreg_nr); - instr->bits3.ia16.src1_abs = src->abs; - instr->bits3.ia16.src1_negate = src->negate; - instr->bits3.ia16.src1_address_mode = src->address_mode; - instr->bits3.ia16.src1_swz_z = src->swizzle_z; - instr->bits3.ia16.src1_swz_w = src->swizzle_w; - instr->bits3.ia16.src1_vert_stride = src->vert_stride; - } - } - - return 0; -} - -/* convert 2-src reg type to 3-src reg type - * - * 2-src reg type: - * 000=UD 001=D 010=UW 011=W 100=UB 101=B 110=DF 111=F - * - * 3-src reg type: - * 00=F 01=D 10=UD 11=DF - */ -static int reg_type_2_to_3(int reg_type) -{ - int r = 0; - switch(reg_type) { - case 7: r = 0; break; - case 1: r = 1; break; - case 0: r = 2; break; - // TODO: supporting DF - } - return r; -} - -int set_instruction_dest_three_src(struct brw_instruction *instr, - struct dst_operand *dest) -{ - instr->bits1.three_src_gen6.dest_reg_file = dest->reg_file; - instr->bits1.three_src_gen6.dest_reg_nr = dest->reg_nr; - instr->bits1.three_src_gen6.dest_subreg_nr = get_subreg_address(dest->reg_file, dest->reg_type, dest->subreg_nr, dest->address_mode) / 4; // in DWORD - instr->bits1.three_src_gen6.dest_writemask = dest->writemask; - instr->bits1.three_src_gen6.dest_reg_type = reg_type_2_to_3(dest->reg_type); - return 0; -} - -int set_instruction_src0_three_src(struct brw_instruction *instr, - struct src_operand *src) -{ - if (advanced_flag) { - reset_instruction_src_region(instr, src); - } - // TODO: supporting src0 swizzle, src0 modifier, src0 rep_ctrl - instr->bits1.three_src_gen6.src_reg_type = reg_type_2_to_3(src->reg_type); - instr->bits2.three_src_gen6.src0_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD - instr->bits2.three_src_gen6.src0_reg_nr = src->reg_nr; - return 0; -} - -int set_instruction_src1_three_src(struct brw_instruction *instr, - struct src_operand *src) -{ - if (advanced_flag) { - reset_instruction_src_region(instr, src); - } - // TODO: supporting src1 swizzle, src1 modifier, src1 rep_ctrl - int v = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD - instr->bits2.three_src_gen6.src1_subreg_nr_low = v % 4; // lower 2 bits - instr->bits3.three_src_gen6.src1_subreg_nr_high = v / 4; // highest bit - instr->bits3.three_src_gen6.src1_reg_nr = src->reg_nr; - return 0; -} - -int set_instruction_src2_three_src(struct brw_instruction *instr, - struct src_operand *src) -{ - if (advanced_flag) { - reset_instruction_src_region(instr, src); - } - // TODO: supporting src2 swizzle, src2 modifier, src2 rep_ctrl - instr->bits3.three_src_gen6.src2_subreg_nr = get_subreg_address(src->reg_file, src->reg_type, src->subreg_nr, src->address_mode) / 4; // in DWORD - instr->bits3.three_src_gen6.src2_reg_nr = src->reg_nr; - return 0; -} - -void set_instruction_options(struct brw_instruction *instr, - struct brw_instruction *options) -{ - /* XXX: more instr options */ - instr->header.access_mode = options->header.access_mode; - instr->header.mask_control = options->header.mask_control; - instr->header.dependency_control = options->header.dependency_control; - instr->header.compression_control = - options->header.compression_control; -} - -void set_instruction_predicate(struct brw_instruction *instr, - struct brw_instruction *predicate) -{ - instr->header.predicate_control = predicate->header.predicate_control; - instr->header.predicate_inverse = predicate->header.predicate_inverse; - instr->bits2.da1.flag_reg_nr = predicate->bits2.da1.flag_reg_nr; - instr->bits2.da1.flag_subreg_nr = predicate->bits2.da1.flag_subreg_nr; -} - -void set_direct_dst_operand(struct dst_operand *dst, struct direct_reg *reg, - int type) -{ - memset(dst, 0, sizeof(*dst)); - dst->address_mode = BRW_ADDRESS_DIRECT; - dst->reg_file = reg->reg_file; - dst->reg_nr = reg->reg_nr; - dst->subreg_nr = reg->subreg_nr; - dst->reg_type = type; - dst->horiz_stride = 1; - dst->writemask_set = 0; - dst->writemask = 0xf; -} - -void set_direct_src_operand(struct src_operand *src, struct direct_reg *reg, - int type) -{ - memset(src, 0, sizeof(*src)); - src->address_mode = BRW_ADDRESS_DIRECT; - src->reg_file = reg->reg_file; - src->reg_type = type; - src->subreg_nr = reg->subreg_nr; - src->reg_nr = reg->reg_nr; - src->vert_stride = 0; - src->width = 0; - src->horiz_stride = 0; - src->negate = 0; - src->abs = 0; - src->swizzle_set = 0; - src->swizzle_x = BRW_CHANNEL_X; - src->swizzle_y = BRW_CHANNEL_Y; - src->swizzle_z = BRW_CHANNEL_Z; - src->swizzle_w = BRW_CHANNEL_W; -} diff --git a/assembler/src/lex.l b/assembler/src/lex.l deleted file mode 100644 index 626042f6..00000000 --- a/assembler/src/lex.l +++ /dev/null @@ -1,428 +0,0 @@ -%option yylineno -%{ -#include -#include "gen4asm.h" -#include "gram.h" -#include "brw_defines.h" - -#include "string.h" -int saved_state = 0; -extern char *input_filename; - -%} -%x BLOCK_COMMENT -%x CHANNEL -%x LINENUMBER -%x FILENAME - -%% -\/\/.*[\r\n] { } /* eat up single-line comments */ -"\.kernel".*[\r\n] { } -"\.end_kernel".*[\r\n] { } -"\.code".*[\r\n] { } -"\.end_code".*[\r\n] { } - - /* eat up multi-line comments, non-nesting. */ -\/\* { - saved_state = YYSTATE; - BEGIN(BLOCK_COMMENT); -} -\*\/ { - BEGIN(saved_state); -} -. { } -[\r\n] { } -"#line"" "* { - saved_state = YYSTATE; - BEGIN(LINENUMBER); -} -[0-9]+" "* { - yylineno = atoi (yytext) - 1; - BEGIN(FILENAME); -} -\"[^\"]+\" { - char *name = malloc (yyleng - 1); - memmove (name, yytext + 1, yyleng - 2); - name[yyleng-1] = '\0'; - input_filename = name; - BEGIN(saved_state); -} - -"x" { - yylval.integer = BRW_CHANNEL_X; - return X; -} -"y" { - yylval.integer = BRW_CHANNEL_Y; - return Y; -} -"z" { - yylval.integer = BRW_CHANNEL_Z; - return Z; -} -"w" { -yylval.integer = BRW_CHANNEL_W; - return W; -} -. { - yyless(0); - BEGIN(INITIAL); -} - - /* used for both null send and null register. */ -"null" { return NULL_TOKEN; } - - /* opcodes */ -"mov" { yylval.integer = BRW_OPCODE_MOV; return MOV; } -"frc" { yylval.integer = BRW_OPCODE_FRC; return FRC; } -"rndu" { yylval.integer = BRW_OPCODE_RNDU; return RNDU; } -"rndd" { yylval.integer = BRW_OPCODE_RNDD; return RNDD; } -"rnde" { yylval.integer = BRW_OPCODE_RNDE; return RNDE; } -"rndz" { yylval.integer = BRW_OPCODE_RNDZ; return RNDZ; } -"not" { yylval.integer = BRW_OPCODE_NOT; return NOT; } -"lzd" { yylval.integer = BRW_OPCODE_LZD; return LZD; } -"f16to32" { yylval.integer = BRW_OPCODE_F16TO32; return F16TO32; } -"f32to16" { yylval.integer = BRW_OPCODE_F32TO16; return F32TO16; } -"fbh" { yylval.integer = BRW_OPCODE_FBH; return FBH; } -"fbl" { yylval.integer = BRW_OPCODE_FBL; return FBL; } - -"mad" { yylval.integer = BRW_OPCODE_MAD; return MAD; } -"lrp" { yylval.integer = BRW_OPCODE_LRP; return LRP; } -"bfe" { yylval.integer = BRW_OPCODE_BFE; return BFE; } -"bfi1" { yylval.integer = BRW_OPCODE_BFI1; return BFI1; } -"bfi2" { yylval.integer = BRW_OPCODE_BFI2; return BFI2; } -"bfrev" { yylval.integer = BRW_OPCODE_BFREV; return BFREV; } -"mul" { yylval.integer = BRW_OPCODE_MUL; return MUL; } -"mac" { yylval.integer = BRW_OPCODE_MAC; return MAC; } -"mach" { yylval.integer = BRW_OPCODE_MACH; return MACH; } -"line" { yylval.integer = BRW_OPCODE_LINE; return LINE; } -"sad2" { yylval.integer = BRW_OPCODE_SAD2; return SAD2; } -"sada2" { yylval.integer = BRW_OPCODE_SADA2; return SADA2; } -"dp4" { yylval.integer = BRW_OPCODE_DP4; return DP4; } -"dph" { yylval.integer = BRW_OPCODE_DPH; return DPH; } -"dp3" { yylval.integer = BRW_OPCODE_DP3; return DP3; } -"dp2" { yylval.integer = BRW_OPCODE_DP2; return DP2; } - -"cbit" { yylval.integer = BRW_OPCODE_CBIT; return CBIT; } -"avg" { yylval.integer = BRW_OPCODE_AVG; return AVG; } -"add" { yylval.integer = BRW_OPCODE_ADD; return ADD; } -"addc" { yylval.integer = BRW_OPCODE_ADDC; return ADDC; } -"sel" { yylval.integer = BRW_OPCODE_SEL; return SEL; } -"and" { yylval.integer = BRW_OPCODE_AND; return AND; } -"or" { yylval.integer = BRW_OPCODE_OR; return OR; } -"xor" { yylval.integer = BRW_OPCODE_XOR; return XOR; } -"shr" { yylval.integer = BRW_OPCODE_SHR; return SHR; } -"shl" { yylval.integer = BRW_OPCODE_SHL; return SHL; } -"asr" { yylval.integer = BRW_OPCODE_ASR; return ASR; } -"cmp" { yylval.integer = BRW_OPCODE_CMP; return CMP; } -"cmpn" { yylval.integer = BRW_OPCODE_CMPN; return CMPN; } -"subb" { yylval.integer = BRW_OPCODE_SUBB; return SUBB; } - -"send" { yylval.integer = BRW_OPCODE_SEND; return SEND; } -"nop" { yylval.integer = BRW_OPCODE_NOP; return NOP; } -"jmpi" { yylval.integer = BRW_OPCODE_JMPI; return JMPI; } -"if" { yylval.integer = BRW_OPCODE_IF; return IF; } -"iff" { yylval.integer = BRW_OPCODE_IFF; return IFF; } -"while" { yylval.integer = BRW_OPCODE_WHILE; return WHILE; } -"else" { yylval.integer = BRW_OPCODE_ELSE; return ELSE; } -"break" { yylval.integer = BRW_OPCODE_BREAK; return BREAK; } -"cont" { yylval.integer = BRW_OPCODE_CONTINUE; return CONT; } -"halt" { yylval.integer = BRW_OPCODE_HALT; return HALT; } -"msave" { yylval.integer = BRW_OPCODE_MSAVE; return MSAVE; } -"push" { yylval.integer = BRW_OPCODE_PUSH; return PUSH; } -"mrest" { yylval.integer = BRW_OPCODE_MRESTORE; return MREST; } -"pop" { yylval.integer = BRW_OPCODE_POP; return POP; } -"wait" { yylval.integer = BRW_OPCODE_WAIT; return WAIT; } -"do" { yylval.integer = BRW_OPCODE_DO; return DO; } -"endif" { yylval.integer = BRW_OPCODE_ENDIF; return ENDIF; } -"call" { yylval.integer = BRW_OPCODE_CALL; return CALL; } -"ret" { yylval.integer = BRW_OPCODE_RET; return RET; } -"brd" { yylval.integer = BRW_OPCODE_BRD; return BRD; } -"brc" { yylval.integer = BRW_OPCODE_BRC; return BRC; } - -"pln" { yylval.integer = BRW_OPCODE_PLN; return PLN; } - - /* send argument tokens */ -"mlen" { return MSGLEN; } -"rlen" { return RETURNLEN; } -"math" { if (IS_GENp(6)) { yylval.integer = BRW_OPCODE_MATH; return MATH_INST; } else return MATH; } -"sampler" { return SAMPLER; } -"gateway" { return GATEWAY; } -"read" { return READ; } -"write" { return WRITE; } -"urb" { return URB; } -"thread_spawner" { return THREAD_SPAWNER; } -"vme" { return VME; } -"cre" { return CRE; } -"data_port" { return DATA_PORT; } - -"allocate" { return ALLOCATE; } -"used" { return USED; } -"complete" { return COMPLETE; } -"transpose" { return TRANSPOSE; } -"interleave" { return INTERLEAVE; } - -";" { return SEMICOLON; } -"(" { return LPAREN; } -")" { return RPAREN; } -"<" { return LANGLE; } -">" { return RANGLE; } -"{" { return LCURLY; } -"}" { return RCURLY; } -"[" { return LSQUARE; } -"]" { return RSQUARE; } -"," { return COMMA; } -"." { BEGIN(CHANNEL); return DOT; } -"+" { return PLUS; } -"-" { return MINUS; } -"*" { return MULTIPLY;} -"/" { return DIVIDE; } -":" { return COLON; } -"=" { return EQ; } -"(abs)" { return ABS; } - - /* Most register accesses are lexed as REGFILE[0-9]+, to prevent the register - * with subreg from being lexed as REGFILE NUMBER instead of - * REGISTER INTEGER DOT INTEGER like we want. The alternative was to use a - * start condition, which wasn't very clean-looking. - * - * However, this means we need to lex the general and message register file - * characters as well, for register-indirect access which is formatted - * like g[a#.#] or m[a#.#]. - */ -"acc"[0-9]+ { - yylval.integer = atoi(yytext + 3); - return ACCREG; -} -"a"[0-9]+ { - yylval.integer = atoi(yytext + 1); - return ADDRESSREG; -} -"m"[0-9]+ { - yylval.integer = atoi(yytext + 1); - return MSGREG; -} -"m" { - return MSGREGFILE; -} -"mask"[0-9]+ { - yylval.integer = atoi(yytext + 4); - return MASKREG; -} -"ms"[0-9]+ { - yylval.integer = atoi(yytext + 2); - return MASKSTACKREG; -} -"msd"[0-9]+ { - yylval.integer = atoi(yytext + 3); - return MASKSTACKDEPTHREG; -} - -"n0."[0-9]+ { - yylval.integer = atoi(yytext + 3); - return NOTIFYREG; -} - -"n"[0-9]+ { - yylval.integer = atoi(yytext + 1); - return NOTIFYREG; -} - -"f"[0-9] { - yylval.integer = atoi(yytext + 1); - return FLAGREG; -} - -[gr][0-9]+ { - yylval.integer = atoi(yytext + 1); - return GENREG; -} -[gr] { - return GENREGFILE; -} -"cr"[0-9]+ { - yylval.integer = atoi(yytext + 2); - return CONTROLREG; -} -"sr"[0-9]+ { - yylval.integer = atoi(yytext + 2); - return STATEREG; -} -"ip" { - return IPREG; -} -"amask" { - yylval.integer = BRW_AMASK; - return AMASK; -} -"imask" { - yylval.integer = BRW_IMASK; - return IMASK; -} -"lmask" { - yylval.integer = BRW_LMASK; - return LMASK; -} -"cmask" { - yylval.integer = BRW_CMASK; - return CMASK; -} -"imsd" { - yylval.integer = 0; - return IMSD; -} -"lmsd" { - yylval.integer = 1; - return LMSD; -} -"ims" { - yylval.integer = 0; - return IMS; -} -"lms" { - yylval.integer = 16; - return LMS; -} - - /* - * Lexing of register types should probably require the ":" symbol specified - * in the BNF of the assembly, but our existing source didn't use that syntax. - */ -"UD" { return TYPE_UD; } -":UD" { return TYPE_UD; } -"D" { return TYPE_D; } -":D" { return TYPE_D; } -"UW" { return TYPE_UW; } -":UW" { return TYPE_UW; } -"W" { return TYPE_W; } -":W" { return TYPE_W; } -"UB" { return TYPE_UB; } -":UB" { return TYPE_UB; } -"B" { return TYPE_B; } -":B" { return TYPE_B; } -"F" { return TYPE_F; } -":F" { return TYPE_F; } -"VF" {return TYPE_VF; } -":VF" {return TYPE_VF; } -"V" { return TYPE_V; } -":V" { return TYPE_V; } - -#".kernel" { return KERNEL_PRAGMA;} -#".end_kernel" { return END_KERNEL_PRAGMA;} -#".code" { return CODE_PRAGMA;} -#".end_code" { return END_CODE_PRAGMA;} -".reg_count_payload" { return REG_COUNT_PAYLOAD_PRAGMA; } -".reg_count_total" { return REG_COUNT_TOTAL_PRAGMA; } -".default_execution_size" { return DEFAULT_EXEC_SIZE_PRAGMA; } -".default_register_type" { return DEFAULT_REG_TYPE_PRAGMA; } -".declare" { return DECLARE_PRAGMA; } -"Base" { return BASE; } -"ElementSize" { return ELEMENTSIZE; } -"SrcRegion" { return SRCREGION; } -"DstRegion" { return DSTREGION; } -"Type" { return TYPE; } - - -".sat" { return SATURATE; } -"align1" { return ALIGN1; } -"align16" { return ALIGN16; } -"sechalf" { return SECHALF; } -"compr" { return COMPR; } -"switch" { return SWITCH; } -"atomic" { return ATOMIC; } -"noddchk" { return NODDCHK; } -"noddclr" { return NODDCLR; } -"mask_disable" { return MASK_DISABLE; } -"nomask" { return MASK_DISABLE; } -"breakpoint" { return BREAKPOINT; } -"accwrctrl" { return ACCWRCTRL; } -"EOT" { return EOT; } - - /* extended math functions */ -"inv" { yylval.integer = BRW_MATH_FUNCTION_INV; return SIN; } -"log" { yylval.integer = BRW_MATH_FUNCTION_LOG; return LOG; } -"exp" { yylval.integer = BRW_MATH_FUNCTION_EXP; return EXP; } -"sqrt" { yylval.integer = BRW_MATH_FUNCTION_SQRT; return SQRT; } -"rsq" { yylval.integer = BRW_MATH_FUNCTION_RSQ; return RSQ; } -"pow" { yylval.integer = BRW_MATH_FUNCTION_POW; return POW; } -"sin" { yylval.integer = BRW_MATH_FUNCTION_SIN; return SIN; } -"cos" { yylval.integer = BRW_MATH_FUNCTION_COS; return COS; } -"sincos" { yylval.integer = BRW_MATH_FUNCTION_SINCOS; return SINCOS; } -"intdiv" { - yylval.integer = BRW_MATH_FUNCTION_INT_DIV_QUOTIENT; - return INTDIV; -} -"intmod" { - yylval.integer = BRW_MATH_FUNCTION_INT_DIV_REMAINDER; - return INTMOD; -} -"intdivmod" { - yylval.integer = BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER; - return INTDIVMOD; -} - -"signed" { return SIGNED; } -"scalar" { return SCALAR; } - - /* predicate control */ -".anyv" { return ANYV; } -".allv" { return ALLV; } -".any2h" { return ANY2H; } -".all2h" { return ALL2H; } -".any4h" { return ANY4H; } -".all4h" { return ALL4H; } -".any8h" { return ANY8H; } -".all8h" { return ALL8H; } -".any16h" { return ANY16H; } -".all16h" { return ALL16H; } - -".z" { yylval.integer = BRW_CONDITIONAL_Z; return ZERO; } -".e" { yylval.integer = BRW_CONDITIONAL_Z; return EQUAL; } -".nz" { yylval.integer = BRW_CONDITIONAL_NZ; return NOT_ZERO; } -".ne" { yylval.integer = BRW_CONDITIONAL_NZ; return NOT_EQUAL; } -".g" { yylval.integer = BRW_CONDITIONAL_G; return GREATER; } -".ge" { yylval.integer = BRW_CONDITIONAL_GE; return GREATER_EQUAL; } -".l" { yylval.integer = BRW_CONDITIONAL_L; return LESS; } -".le" { yylval.integer = BRW_CONDITIONAL_LE; return LESS_EQUAL; } -".r" { yylval.integer = BRW_CONDITIONAL_R; return ROUND_INCREMENT; } -".o" { yylval.integer = BRW_CONDITIONAL_O; return OVERFLOW; } -".u" { yylval.integer = BRW_CONDITIONAL_U; return UNORDERED; } - -[a-zA-Z_][0-9a-zA-Z_]* { - yylval.string = strdup(yytext); - return STRING; -} - -0x[0-9a-fA-F][0-9a-fA-F]* { - yylval.integer = strtoul(yytext + 2, NULL, 16); - return INTEGER; -} -[0-9][0-9]* { - yylval.integer = strtoul(yytext, NULL, 10); - return INTEGER; -} - -[-]?[0-9]+"."[0-9]+ { - yylval.number = strtod(yytext, NULL); - return NUMBER; -} - -[ \t\n]+ { } /* eat up whitespace */ - -. { - fprintf(stderr, "%s: %d: %s at \"%s\"\n", - input_filename, yylineno, "unexpected token", lex_text()); - } -%% - -char * -lex_text(void) -{ - return yytext; - (void) yyunput; -} - -#ifndef yywrap -int yywrap() { return 1; } -#endif - diff --git a/assembler/src/main.c b/assembler/src/main.c deleted file mode 100644 index 15ed5179..00000000 --- a/assembler/src/main.c +++ /dev/null @@ -1,493 +0,0 @@ -/* -*- c-basic-offset: 8 -*- */ -/* - * Copyright © 2006 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - * - * Authors: - * Eric Anholt - * - */ - -#include -#include -#include -#include -#include - -#include "gen4asm.h" - -extern FILE *yyin; - -extern int errors; - -long int gen_level = 40; -int advanced_flag = 0; /* 0: in unit of byte, 1: in unit of data element size */ -int binary_like_output = 0; /* 0: default output style, 1: nice C-style output */ -int need_export = 0; -char *input_filename = ""; -char *export_filename = NULL; - -const char const *binary_prepend = "static const char gen_eu_bytes[] = {\n"; - -struct brw_program compiled_program; -struct program_defaults program_defaults = {.register_type = BRW_REGISTER_TYPE_F}; - -#define HASH_SIZE 37 - -struct hash_item { - char *key; - void *value; - struct hash_item *next; -}; - -typedef struct hash_item *hash_table[HASH_SIZE]; - -static hash_table declared_register_table; - -struct label_item { - char *name; - int addr; - struct label_item *next; -}; -static struct label_item *label_table; - -static const struct option longopts[] = { - {"advanced", no_argument, 0, 'a'}, - {"binary", no_argument, 0, 'b'}, - {"export", required_argument, 0, 'e'}, - {"input_list", required_argument, 0, 'l'}, - {"output", required_argument, 0, 'o'}, - {"gen", required_argument, 0, 'g'}, - { NULL, 0, NULL, 0 } -}; - -// jump distance used in branch instructions as JIP or UIP -static int jump_distance(int offset) -{ - // Gen4- bspec: the jump distance is in number of sixteen-byte units - // Gen5+ bspec: the jump distance is in number of eight-byte units - if(IS_GENp(5)) - offset *= 2; - return offset; -} - -static void usage(void) -{ - fprintf(stderr, "usage: intel-gen4asm [options] inputfile\n"); - fprintf(stderr, "OPTIONS:\n"); - fprintf(stderr, "\t-a, --advanced Set advanced flag\n"); - fprintf(stderr, "\t-b, --binary C style binary output\n"); - fprintf(stderr, "\t-e, --export {exportfile} Export label file\n"); - fprintf(stderr, "\t-l, --input_list {entrytablefile} Input entry_table_list file\n"); - fprintf(stderr, "\t-o, --output {outputfile} Specify output file\n"); - fprintf(stderr, "\t-g, --gen <4|5|6|7> Specify GPU generation\n"); -} - -static int hash(char *key) -{ - unsigned ret = 0; - while(*key) - ret = (ret << 1) + (*key++); - return ret % HASH_SIZE; -} - -static void *find_hash_item(hash_table t, char *key) -{ - struct hash_item *p; - for(p = t[hash(key)]; p; p = p->next) - if(strcasecmp(p->key, key) == 0) - return p->value; - return NULL; -} - -static void insert_hash_item(hash_table t, char *key, void *v) -{ - int index = hash(key); - struct hash_item *p = malloc(sizeof(*p)); - p->key = key; - p->value = v; - p->next = t[index]; - t[index] = p; -} - -static void free_hash_table(hash_table t) -{ - struct hash_item *p, *next; - int i; - for (i = 0; i < HASH_SIZE; i++) { - p = t[i]; - while(p) { - next = p->next; - free(p->key); - free(p->value); - free(p); - p = next; - } - } -} - -struct declared_register *find_register(char *name) -{ - return find_hash_item(declared_register_table, name); -} - -void insert_register(struct declared_register *reg) -{ - insert_hash_item(declared_register_table, reg->name, reg); -} - -void add_label(char *name, int addr) -{ - struct label_item **p = &label_table; - while(*p) - p = &((*p)->next); - *p = calloc(1, sizeof(**p)); - (*p)->name = name; - (*p)->addr = addr; -} - -/* Some assembly code have duplicated labels. - Start from start_addr. Search as a loop. Return the first label found. */ -int label_to_addr(char *name, int start_addr) -{ - /* return the first label just after start_addr, or the first label from the head */ - struct label_item *p; - int r = -1; - for(p = label_table; p; p = p->next) { - if(strcmp(p->name, name) == 0) { - if(p->addr >= start_addr) // the first label just after start_addr - return p->addr; - else if(r == -1) // the first label from the head - r = p->addr; - } - } - if(r == -1) { - fprintf(stderr, "Can't find label %s\n", name); - exit(1); - } - return r; -} - -static void free_label_table(struct label_item *p) -{ - if(p) { - free_label_table(p->next); - free(p); - } -} - -struct entry_point_item { - char *str; - struct entry_point_item *next; -} *entry_point_table; - -static int read_entry_file(char *fn) -{ - FILE *entry_table_file; - char buf[2048]; - struct entry_point_item **p = &entry_point_table; - if (!fn) - return 0; - if ((entry_table_file = fopen(fn, "r")) == NULL) - return -1; - while (fgets(buf, sizeof(buf)-1, entry_table_file) != NULL) { - // drop the final char '\n' - if(buf[strlen(buf)-1] == '\n') - buf[strlen(buf)-1] = 0; - *p = calloc(1, sizeof(struct entry_point_item)); - (*p)->str = strdup(buf); - p = &((*p)->next); - } - fclose(entry_table_file); - return 0; -} - -static int is_entry_point(char *s) -{ - struct entry_point_item *p; - for (p = entry_point_table; p; p = p->next) { - if (strcmp(p->str, s) == 0) - return 1; - } - return 0; -} - -static void free_entry_point_table(struct entry_point_item *p) { - if (p) { - free_entry_point_table(p->next); - free(p->str); - free(p); - } -} - -static void -print_instruction(FILE *output, struct brw_program_instruction *entry) -{ - if (binary_like_output) { - fprintf(output, "\t0x%02x, 0x%02x, 0x%02x, 0x%02x, " - "0x%02x, 0x%02x, 0x%02x, 0x%02x,\n" - "\t0x%02x, 0x%02x, 0x%02x, 0x%02x, " - "0x%02x, 0x%02x, 0x%02x, 0x%02x,\n", - ((unsigned char *)(&entry->instruction))[0], - ((unsigned char *)(&entry->instruction))[1], - ((unsigned char *)(&entry->instruction))[2], - ((unsigned char *)(&entry->instruction))[3], - ((unsigned char *)(&entry->instruction))[4], - ((unsigned char *)(&entry->instruction))[5], - ((unsigned char *)(&entry->instruction))[6], - ((unsigned char *)(&entry->instruction))[7], - ((unsigned char *)(&entry->instruction))[8], - ((unsigned char *)(&entry->instruction))[9], - ((unsigned char *)(&entry->instruction))[10], - ((unsigned char *)(&entry->instruction))[11], - ((unsigned char *)(&entry->instruction))[12], - ((unsigned char *)(&entry->instruction))[13], - ((unsigned char *)(&entry->instruction))[14], - ((unsigned char *)(&entry->instruction))[15]); - } else { - fprintf(output, " { 0x%08x, 0x%08x, 0x%08x, 0x%08x },\n", - ((int *)(&entry->instruction))[0], - ((int *)(&entry->instruction))[1], - ((int *)(&entry->instruction))[2], - ((int *)(&entry->instruction))[3]); - } -} -int main(int argc, char **argv) -{ - char *output_file = NULL; - char *entry_table_file = NULL; - FILE *output = stdout; - FILE *export_file; - struct brw_program_instruction *entry, *entry1, *tmp_entry; - int err, inst_offset; - char o; - while ((o = getopt_long(argc, argv, "e:l:o:g:ab", longopts, NULL)) != -1) { - switch (o) { - case 'o': - if (strcmp(optarg, "-") != 0) - output_file = optarg; - - break; - - case 'g': { - char *dec_ptr, *end_ptr; - unsigned long decimal; - - gen_level = strtol(optarg, &dec_ptr, 10) * 10; - - if (*dec_ptr == '.') { - decimal = strtoul(++dec_ptr, &end_ptr, 10); - if (end_ptr != dec_ptr && *end_ptr == '\0') { - if (decimal > 10) { - fprintf(stderr, "Invalid Gen X decimal version\n"); - exit(1); - } - gen_level += decimal; - } - } - - if (gen_level < 40 || gen_level > 75) { - usage(); - exit(1); - } - - break; - } - - case 'a': - advanced_flag = 1; - break; - case 'b': - binary_like_output = 1; - break; - - case 'e': - need_export = 1; - if (strcmp(optarg, "-") != 0) - export_filename = optarg; - break; - - case 'l': - if (strcmp(optarg, "-") != 0) - entry_table_file = optarg; - break; - - default: - usage(); - exit(1); - } - } - argc -= optind; - argv += optind; - if (argc != 1) { - usage(); - exit(1); - } - - if (strcmp(argv[0], "-") != 0) { - input_filename = argv[0]; - yyin = fopen(input_filename, "r"); - if (yyin == NULL) { - perror("Couldn't open input file"); - exit(1); - } - } - - err = yyparse(); - - if (strcmp(argv[0], "-")) - fclose(yyin); - - yylex_destroy(); - - if (err || errors) - exit (1); - - if (output_file) { - output = fopen(output_file, "w"); - if (output == NULL) { - perror("Couldn't open output file"); - exit(1); - } - - } - - if (read_entry_file(entry_table_file)) { - fprintf(stderr, "Read entry file error\n"); - exit(1); - } - inst_offset = 0 ; - for (entry = compiled_program.first; - entry != NULL; entry = entry->next) { - entry->inst_offset = inst_offset; - entry1 = entry->next; - if (entry1 && entry1->islabel && is_entry_point(entry1->string)) { - // insert NOP instructions until (inst_offset+1) % 4 == 0 - while (((inst_offset+1) % 4) != 0) { - tmp_entry = calloc(sizeof(*tmp_entry), 1); - tmp_entry->instruction.header.opcode = BRW_OPCODE_NOP; - entry->next = tmp_entry; - tmp_entry->next = entry1; - entry = tmp_entry; - tmp_entry->inst_offset = ++inst_offset; - } - } - if (!entry->islabel) - inst_offset++; - } - - for (entry = compiled_program.first; entry; entry = entry->next) - if (entry->islabel) - add_label(entry->string, entry->inst_offset); - - if (need_export) { - if (export_filename) { - export_file = fopen(export_filename, "w"); - } else { - export_file = fopen("export.inc", "w"); - } - for (entry = compiled_program.first; - entry != NULL; entry = entry->next) { - if (entry->islabel) - fprintf(export_file, "#define %s_IP %d\n", - entry->string, (IS_GENx(5) ? 2 : 1)*(entry->inst_offset)); - } - fclose(export_file); - } - - for (entry = compiled_program.first; entry; entry = entry->next) { - struct brw_instruction *inst = & entry->instruction; - - if (inst->first_reloc_target) - inst->first_reloc_offset = label_to_addr(inst->first_reloc_target, entry->inst_offset) - entry->inst_offset; - - if (inst->second_reloc_target) - inst->second_reloc_offset = label_to_addr(inst->second_reloc_target, entry->inst_offset) - entry->inst_offset; - - if (inst->second_reloc_offset) { - // this is a branch instruction with two offset arguments - entry->instruction.bits3.branch_2_offset.JIP = jump_distance(inst->first_reloc_offset); - entry->instruction.bits3.branch_2_offset.UIP = jump_distance(inst->second_reloc_offset); - } else if (inst->first_reloc_offset) { - // this is a branch instruction with one offset argument - int offset = inst->first_reloc_offset; - /* bspec: Unlike other flow control instructions, the offset used by JMPI is relative to the incremented instruction pointer rather than the IP value for the instruction itself. */ - - int is_jmpi = entry->instruction.header.opcode == BRW_OPCODE_JMPI; // target relative to the post-incremented IP, so delta == 1 if JMPI - if(is_jmpi) - offset --; - offset = jump_distance(offset); - if (is_jmpi && (gen_level == 75)) - offset = offset * 8; - - if(!IS_GENp(6)) { - entry->instruction.bits3.JIP = offset; - if(entry->instruction.header.opcode == BRW_OPCODE_ELSE) - entry->instruction.bits3.branch_2_offset.UIP = 1; /* Set the istack pop count, which must always be 1. */ - } else if(IS_GENx(6)) { - /* TODO: endif JIP pos is not in Gen6 spec. may be bits1 */ - int opcode = entry->instruction.header.opcode; - if(opcode == BRW_OPCODE_CALL || opcode == BRW_OPCODE_JMPI) - entry->instruction.bits3.JIP = offset; // for CALL, JMPI - else - entry->instruction.bits1.branch.JIP = offset; // for CASE,ELSE,FORK,IF,WHILE - } else if(IS_GENp(7)) { - int opcode = entry->instruction.header.opcode; - /* Gen7 JMPI Restrictions in bspec: - * The JIP data type must be Signed DWord - */ - if(opcode == BRW_OPCODE_JMPI) - entry->instruction.bits3.JIP = offset; - else - entry->instruction.bits3.branch_2_offset.JIP = offset; - } - } - } - - if (binary_like_output) - fprintf(output, "%s", binary_prepend); - - for (entry = compiled_program.first; - entry != NULL; - entry = entry1) { - entry1 = entry->next; - if (!entry->islabel) - print_instruction(output, entry); - else - free(entry->string); - free(entry); - } - if (binary_like_output) - fprintf(output, "};"); - - free_entry_point_table(entry_point_table); - free_hash_table(declared_register_table); - free_label_table(label_table); - - fflush (output); - if (ferror (output)) { - perror ("Could not flush output file"); - if (output_file) - unlink (output_file); - err = 1; - } - return err; -} diff --git a/configure.ac b/configure.ac index 5e2dbed7..832da27e 100644 --- a/configure.ac +++ b/configure.ac @@ -38,7 +38,12 @@ AM_INIT_AUTOMAKE([foreign dist-bzip2]) AM_PATH_PYTHON([3],, [:]) AM_MAINTAINER_MODE +AC_PROG_CC +AM_PROG_LEX +AC_PROG_YACC + # Checks for functions, headers, structures, etc. +AC_HEADER_STDC AC_CHECK_HEADERS([termios.h]) AC_CHECK_MEMBERS([struct sysinfo.totalram],[],[],[AC_INCLUDES_DEFAULT #include @@ -56,6 +61,16 @@ m4_ifndef([XORG_MACROS_VERSION], XORG_MACROS_VERSION(1.16) XORG_DEFAULT_OPTIONS +# warning flags for the assembler. We can't quite use CWARNFLAGS for it yet as +# it generates waaaay to many warnings. +ASSEMBLER_WARN_CFLAGS="" +if test "x$GCC" = "xyes"; then + ASSEMBLER_WARN_CFLAGS="-Wall -Wpointer-arith -Wstrict-prototypes \ + -Wmissing-prototypes -Wmissing-declarations \ + -Wnested-externs -fno-strict-aliasing" +fi +AC_SUBST(ASSEMBLER_WARN_CFLAGS) + PKG_CHECK_MODULES(DRM, [libdrm_intel >= 2.4.38 libdrm]) PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10]) @@ -157,6 +172,10 @@ AC_CONFIG_FILES([ tools/quick_dump/Makefile debugger/Makefile debugger/system_routine/Makefile + assembler/Makefile + assembler/doc/Makefile + assembler/test/Makefile + assembler/intel-gen4asm.pc ]) AC_OUTPUT -- cgit v1.2.3