From 435c5093aa2043eb832a5f4cb468d7141488e14c Mon Sep 17 00:00:00 2001 From: Lukasz Kalamarz Date: Thu, 12 Jul 2018 16:15:23 +0200 Subject: lib/rendercopy: Use gen4 definitions if applicable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of using definitions duplicated in gen7_render header, we should use the oldest definition that is working with chosen gen. This patch reuse gen6 definitons if registers/fields/shifts that were introduced in other genX_render headers. v3: Rebase and checkpatch Signed-off-by: Lukasz Kalamarz Cc: Katarzyna Dec Cc: Antonio Argenziano Cc: Daniele Ceraolo Spurio Cc: Ville Syrjälä Reviewed-by: Katarzyna Dec --- lib/gen6_render.h | 103 +++++++++++--------------- lib/gen7_render.h | 56 +++++++------- lib/gen8_render.h | 56 +++++++------- lib/gen9_render.h | 4 +- lib/rendercopy_gen6.c | 98 ++++++++++++------------ lib/rendercopy_gen7.c | 64 ++++++++-------- lib/rendercopy_gen8.c | 58 +++++++-------- lib/rendercopy_gen9.c | 58 +++++++-------- tools/null_state_gen/intel_renderstate_gen6.c | 92 +++++++++++------------ tools/null_state_gen/intel_renderstate_gen7.c | 62 ++++++++-------- tools/null_state_gen/intel_renderstate_gen8.c | 38 +++++----- tools/null_state_gen/intel_renderstate_gen9.c | 36 ++++----- 12 files changed, 356 insertions(+), 369 deletions(-) diff --git a/lib/gen6_render.h b/lib/gen6_render.h index 8f0beda2..6bf468df 100644 --- a/lib/gen6_render.h +++ b/lib/gen6_render.h @@ -3,37 +3,38 @@ #include #include "surfaceformat.h" +#include "gen4_render.h" #define GEN6_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \ ((Pipeline) << 27) | \ ((Opcode) << 24) | \ ((Subopcode) << 16)) -#define GEN6_STATE_BASE_ADDRESS GEN6_3D(0, 1, 1) +#define GEN6_STATE_BASE_ADDRESS GEN4_3D(0, 1, 1) # define BASE_ADDRESS_MODIFY (1 << 0) # define BUFFER_SIZE_MODIFY (1 << 0) -#define GEN6_STATE_SIP GEN6_3D(0, 1, 2) +#define GEN6_STATE_SIP GEN4_3D(0, 1, 2) -#define GEN6_3DSTATE_VF_STATISTICS GEN6_3D(1, 0, 0xB) -#define GEN6_PIPELINE_SELECT GEN6_3D(1, 1, 4) +#define GEN6_3DSTATE_VF_STATISTICS GEN4_3D(1, 0, 0xB) +#define GEN6_PIPELINE_SELECT GEN4_3D(1, 1, 4) # define PIPELINE_SELECT_3D 0 # define PIPELINE_SELECT_MEDIA 1 -#define GEN6_MEDIA_STATE_POINTERS GEN6_3D(2, 0, 0) -#define GEN6_MEDIA_OBJECT GEN6_3D(2, 1, 0) +#define GEN6_MEDIA_STATE_POINTERS GEN4_3D(2, 0, 0) +#define GEN6_MEDIA_OBJECT GEN4_3D(2, 1, 0) -#define GEN6_3DSTATE_BINDING_TABLE_POINTERS GEN6_3D(3, 0, 0x01) +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS GEN4_3D(3, 0, 0x01) # define GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS (1 << 12)/* for GEN6 */ # define GEN6_3DSTATE_BINDING_TABLE_MODIFY_GS (1 << 9) /* for GEN6 */ # define GEN6_3DSTATE_BINDING_TABLE_MODIFY_VS (1 << 8) /* for GEN6 */ -#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS GEN6_3D(3, 0, 0x02) +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS GEN4_3D(3, 0, 0x02) # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS (1 << 12) # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_GS (1 << 9) # define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_VS (1 << 8) -#define GEN6_3DSTATE_URB GEN6_3D(3, 0, 0x05) +#define GEN6_3DSTATE_URB GEN4_3D(3, 0, 0x05) /* DW1 */ # define GEN6_3DSTATE_URB_VS_SIZE_SHIFT 16 # define GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT 0 @@ -41,25 +42,25 @@ # define GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT 8 # define GEN6_3DSTATE_URB_GS_SIZE_SHIFT 0 -#define GEN6_3DSTATE_VERTEX_BUFFERS GEN6_3D(3, 0, 0x08) -#define GEN6_3DSTATE_VERTEX_ELEMENTS GEN6_3D(3, 0, 0x09) -#define GEN6_3DSTATE_INDEX_BUFFER GEN6_3D(3, 0, 0x0A) -#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS GEN6_3D(3, 0, 0x0D) +#define GEN6_3DSTATE_VERTEX_BUFFERS GEN4_3D(3, 0, 0x08) +#define GEN6_3DSTATE_VERTEX_ELEMENTS GEN4_3D(3, 0, 0x09) +#define GEN6_3DSTATE_INDEX_BUFFER GEN4_3D(3, 0, 0x0A) +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS GEN4_3D(3, 0, 0x0D) # define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC (1 << 12) # define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_SF (1 << 11) # define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CLIP (1 << 10) -#define GEN6_3DSTATE_CC_STATE_POINTERS GEN6_3D(3, 0, 0x0E) +#define GEN6_3DSTATE_CC_STATE_POINTERS GEN4_3D(3, 0, 0x0E) -#define GEN6_3DSTATE_VS GEN6_3D(3, 0, 0x10) +#define GEN6_3DSTATE_VS GEN4_3D(3, 0, 0x10) -#define GEN6_3DSTATE_GS GEN6_3D(3, 0, 0x11) +#define GEN6_3DSTATE_GS GEN4_3D(3, 0, 0x11) /* DW4 */ # define GEN6_3DSTATE_GS_DISPATCH_START_GRF_SHIFT 0 -#define GEN6_3DSTATE_CLIP GEN6_3D(3, 0, 0x12) +#define GEN6_3DSTATE_CLIP GEN4_3D(3, 0, 0x12) -#define GEN6_3DSTATE_SF GEN6_3D(3, 0, 0x13) +#define GEN6_3DSTATE_SF GEN4_3D(3, 0, 0x13) /* DW1 */ # define GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT 22 # define GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT 11 @@ -76,7 +77,7 @@ # define GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT 25 # define GEN6_3DSTATE_SF_VERTEX_SUB_PIXEL_PRECISION_SHIFT 12 -#define GEN6_3DSTATE_WM GEN6_3D(3, 0, 0x14) +#define GEN6_3DSTATE_WM GEN4_3D(3, 0, 0x14) /* DW2 */ # define GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT 27 # define GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 @@ -96,28 +97,28 @@ # define GEN6_3DSTATE_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11) # define GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10) -#define GEN6_3DSTATE_CONSTANT_VS GEN6_3D(3, 0, 0x15) -#define GEN6_3DSTATE_CONSTANT_GS GEN6_3D(3, 0, 0x16) -#define GEN6_3DSTATE_CONSTANT_PS GEN6_3D(3, 0, 0x17) +#define GEN6_3DSTATE_CONSTANT_VS GEN4_3D(3, 0, 0x15) +#define GEN6_3DSTATE_CONSTANT_GS GEN4_3D(3, 0, 0x16) +#define GEN6_3DSTATE_CONSTANT_PS GEN4_3D(3, 0, 0x17) -#define GEN6_3DSTATE_SAMPLE_MASK GEN6_3D(3, 0, 0x18) +#define GEN6_3DSTATE_SAMPLE_MASK GEN4_3D(3, 0, 0x18) -#define GEN6_3DSTATE_DRAWING_RECTANGLE GEN6_3D(3, 1, 0x00) -#define GEN6_3DSTATE_CONSTANT_COLOR GEN6_3D(3, 1, 0x01) -#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD GEN6_3D(3, 1, 0x02) -#define GEN6_3DSTATE_CHROMA_KEY GEN6_3D(3, 1, 0x04) -#define GEN6_3DSTATE_DEPTH_BUFFER GEN6_3D(3, 1, 0x05) +#define GEN6_3DSTATE_DRAWING_RECTANGLE GEN4_3D(3, 1, 0x00) +#define GEN6_3DSTATE_CONSTANT_COLOR GEN4_3D(3, 1, 0x01) +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD GEN4_3D(3, 1, 0x02) +#define GEN6_3DSTATE_CHROMA_KEY GEN4_3D(3, 1, 0x04) +#define GEN6_3DSTATE_DEPTH_BUFFER GEN4_3D(3, 1, 0x05) # define GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29 # define GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18 -#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET GEN6_3D(3, 1, 0x06) -#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN GEN6_3D(3, 1, 0x07) -#define GEN6_3DSTATE_LINE_STIPPLE GEN6_3D(3, 1, 0x08) -#define GEN6_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP GEN6_3D(3, 1, 0x09) +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET GEN4_3D(3, 1, 0x06) +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN GEN4_3D(3, 1, 0x07) +#define GEN6_3DSTATE_LINE_STIPPLE GEN4_3D(3, 1, 0x08) +#define GEN6_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP GEN4_3D(3, 1, 0x09) /* These two are BLC and CTG only, not BW or CL */ -#define GEN6_3DSTATE_AA_LINE_PARAMS GEN6_3D(3, 1, 0x0A) -#define GEN6_3DSTATE_GS_SVB_INDEX GEN6_3D(3, 1, 0x0B) -#define GEN6_3DSTATE_MULTISAMPLE GEN6_3D(3, 1, 0x0D) +#define GEN6_3DSTATE_AA_LINE_PARAMS GEN4_3D(3, 1, 0x0A) +#define GEN6_3DSTATE_GS_SVB_INDEX GEN4_3D(3, 1, 0x0B) +#define GEN6_3DSTATE_MULTISAMPLE GEN4_3D(3, 1, 0x0D) /* DW1 */ # define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER (0 << 4) # define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT (1 << 4) @@ -125,7 +126,7 @@ # define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1) # define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1) -#define GEN6_3DSTATE_CLEAR_PARAMS GEN6_3D(3, 1, 0x10) +#define GEN6_3DSTATE_CLEAR_PARAMS GEN4_3D(3, 1, 0x10) /* DW1 */ # define GEN6_3DSTATE_DEPTH_CLEAR_VALID (1 << 15) # define GEN6_PIPE_CONTROL_NOWRITE (0 << 14) @@ -141,25 +142,25 @@ # define GEN6_PIPE_CONTROL_LOCAL_PGTT (0 << 2) # define GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) -#define GEN6_3DSTATE_MONOFILTER_SIZE GEN6_3D(3, 1, 0x11) -#define GEN6_PIPE_CONTROL GEN6_3D(3, 2, 0) +#define GEN6_3DSTATE_MONOFILTER_SIZE GEN4_3D(3, 1, 0x11) +#define GEN6_PIPE_CONTROL GEN4_3D(3, 2, 0) -#define GEN6_3DPRIMITIVE GEN6_3D(3, 3, 0) +#define GEN6_3DPRIMITIVE GEN4_3D(3, 3, 0) # define GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) # define GEN6_3DPRIMITIVE_VERTEX_RANDOM (1 << 15) /* Primitive types are in gen6_defines.h */ # define GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT 10 /* VERTEX_BUFFER_STATE Structure */ -#define VB0_BUFFER_INDEX_SHIFT 26 -#define VB0_VERTEXDATA (0 << 20) -#define VB0_INSTANCEDATA (1 << 20) +#define GEN6_VB0_BUFFER_INDEX_SHIFT 26 +#define GEN6_VB0_VERTEXDATA (0 << 20) +#define GEN6_VB0_INSTANCEDATA (1 << 20) #define VB0_BUFFER_PITCH_SHIFT 0 #define VB0_NULL_VERTEX_BUFFER (1 << 13) /* VERTEX_ELEMENT_STATE Structure */ -#define VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */ -#define VE0_VALID (1 << 25) /* for GEN6 */ +#define GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */ +#define GEN6_VE0_VALID (1 << 25) /* for GEN6 */ #define VE0_FORMAT_SHIFT 16 #define VE0_OFFSET_SHIFT 0 #define VE1_VFCOMPONENT_0_SHIFT 28 @@ -1072,18 +1073,4 @@ struct gen6_cc_viewport { float max_depth; }; -typedef enum { - SAMPLER_FILTER_NEAREST = 0, - SAMPLER_FILTER_BILINEAR, - FILTER_COUNT -} sampler_filter_t; - -typedef enum { - SAMPLER_EXTEND_NONE = 0, - SAMPLER_EXTEND_REPEAT, - SAMPLER_EXTEND_PAD, - SAMPLER_EXTEND_REFLECT, - EXTEND_COUNT -} sampler_extend_t; - #endif diff --git a/lib/gen7_render.h b/lib/gen7_render.h index 60e9aad4..4bde0d5f 100644 --- a/lib/gen7_render.h +++ b/lib/gen7_render.h @@ -85,21 +85,21 @@ # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8) # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 8) -#define GEN7_3DSTATE_CLEAR_PARAMS GEN6_3D(3, 0, 0x04) -#define GEN7_3DSTATE_DEPTH_BUFFER GEN6_3D(3, 0, 0x05) +#define GEN7_3DSTATE_CLEAR_PARAMS GEN4_3D(3, 0, 0x04) +#define GEN7_3DSTATE_DEPTH_BUFFER GEN4_3D(3, 0, 0x05) # define GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29 # define GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18 /* DW1 */ # define GEN7_3DSTATE_DEPTH_CLEAR_VALID (1 << 15) -#define GEN7_3DSTATE_CONSTANT_HS GEN6_3D(3, 0, 0x19) -#define GEN7_3DSTATE_CONSTANT_DS GEN6_3D(3, 0, 0x1a) +#define GEN7_3DSTATE_CONSTANT_HS GEN4_3D(3, 0, 0x19) +#define GEN7_3DSTATE_CONSTANT_DS GEN4_3D(3, 0, 0x1a) -#define GEN7_3DSTATE_HS GEN6_3D(3, 0, 0x1b) -#define GEN7_3DSTATE_TE GEN6_3D(3, 0, 0x1c) -#define GEN7_3DSTATE_DS GEN6_3D(3, 0, 0x1d) -#define GEN7_3DSTATE_STREAMOUT GEN6_3D(3, 0, 0x1e) -#define GEN7_3DSTATE_SBE GEN6_3D(3, 0, 0x1f) +#define GEN7_3DSTATE_HS GEN4_3D(3, 0, 0x1b) +#define GEN7_3DSTATE_TE GEN4_3D(3, 0, 0x1c) +#define GEN7_3DSTATE_DS GEN4_3D(3, 0, 0x1d) +#define GEN7_3DSTATE_STREAMOUT GEN4_3D(3, 0, 0x1e) +#define GEN7_3DSTATE_SBE GEN4_3D(3, 0, 0x1f) /* DW1 */ # define GEN7_SBE_SWIZZLE_CONTROL_MODE (1 << 28) @@ -109,7 +109,7 @@ # define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11 # define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4 -#define GEN7_3DSTATE_PS GEN6_3D(3, 0, 0x20) +#define GEN7_3DSTATE_PS GEN4_3D(3, 0, 0x20) /* DW1: kernel pointer */ /* DW2 */ # define GEN7_PS_SPF_MODE (1 << 31) @@ -140,33 +140,33 @@ /* DW6: kernel 1 pointer */ /* DW7: kernel 2 pointer */ -#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL GEN6_3D(3, 0, 0x21) -#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC GEN6_3D(3, 0, 0x23) +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL GEN4_3D(3, 0, 0x21) +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC GEN4_3D(3, 0, 0x23) -#define GEN7_3DSTATE_BLEND_STATE_POINTERS GEN6_3D(3, 0, 0x24) -#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS GEN6_3D(3, 0, 0x25) +#define GEN7_3DSTATE_BLEND_STATE_POINTERS GEN4_3D(3, 0, 0x24) +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS GEN4_3D(3, 0, 0x25) -#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS GEN6_3D(3, 0, 0x26) -#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS GEN6_3D(3, 0, 0x27) -#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS GEN6_3D(3, 0, 0x28) -#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS GEN6_3D(3, 0, 0x29) -#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS GEN6_3D(3, 0, 0x2a) +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS GEN4_3D(3, 0, 0x26) +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS GEN4_3D(3, 0, 0x27) +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS GEN4_3D(3, 0, 0x28) +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS GEN4_3D(3, 0, 0x29) +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS GEN4_3D(3, 0, 0x2a) -#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS GEN6_3D(3, 0, 0x2b) -#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS GEN6_3D(3, 0, 0x2e) -#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS GEN6_3D(3, 0, 0x2f) +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS GEN4_3D(3, 0, 0x2b) +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS GEN4_3D(3, 0, 0x2e) +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS GEN4_3D(3, 0, 0x2f) -#define GEN7_3DSTATE_URB_VS GEN6_3D(3, 0, 0x30) -#define GEN7_3DSTATE_URB_HS GEN6_3D(3, 0, 0x31) -#define GEN7_3DSTATE_URB_DS GEN6_3D(3, 0, 0x32) -#define GEN7_3DSTATE_URB_GS GEN6_3D(3, 0, 0x33) +#define GEN7_3DSTATE_URB_VS GEN4_3D(3, 0, 0x30) +#define GEN7_3DSTATE_URB_HS GEN4_3D(3, 0, 0x31) +#define GEN7_3DSTATE_URB_DS GEN4_3D(3, 0, 0x32) +#define GEN7_3DSTATE_URB_GS GEN4_3D(3, 0, 0x33) /* DW1 */ # define GEN7_URB_ENTRY_NUMBER_SHIFT 0 # define GEN7_URB_ENTRY_SIZE_SHIFT 16 # define GEN7_URB_STARTING_ADDRESS_SHIFT 25 -#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS GEN6_3D(3, 1, 0x12) -#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS GEN6_3D(3, 1, 0x16) +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS GEN4_3D(3, 1, 0x12) +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS GEN4_3D(3, 1, 0x16) /* DW1 */ # define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16 diff --git a/lib/gen8_render.h b/lib/gen8_render.h index 470dca0f..c62047d8 100644 --- a/lib/gen8_render.h +++ b/lib/gen8_render.h @@ -5,21 +5,21 @@ # define GEN8_WM_LEGACY_DIAMOND_LINE_RASTERIZATION (1 << 26) -#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS GEN6_3D(3, 0, 0xf) -#define GEN8_3DSTATE_STENCIL_BUFFER GEN6_3D(3, 0, 0x06) -#define GEN8_3DSTATE_HIER_DEPTH_BUFFER GEN6_3D(3, 0, 0x07) -#define GEN8_3DSTATE_MULTISAMPLE GEN6_3D(3, 0, 0x0d) +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS GEN4_3D(3, 0, 0xf) +#define GEN8_3DSTATE_STENCIL_BUFFER GEN4_3D(3, 0, 0x06) +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER GEN4_3D(3, 0, 0x07) +#define GEN8_3DSTATE_MULTISAMPLE GEN4_3D(3, 0, 0x0d) # define GEN8_3DSTATE_MULTISAMPLE_NUMSAMPLES_2 (1 << 1) # define GEN9_3DSTATE_MULTISAMPLE_NUMSAMPLES_16 (4 << 1) -#define GEN8_3DSTATE_WM_HZ_OP GEN6_3D(3, 0, 0x52) +#define GEN8_3DSTATE_WM_HZ_OP GEN4_3D(3, 0, 0x52) -#define GEN8_3DSTATE_VF_INSTANCING GEN6_3D(3, 0, 0x49) +#define GEN8_3DSTATE_VF_INSTANCING GEN4_3D(3, 0, 0x49) # define GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH (1 << 29) # define GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET (1 << 28) # define GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT 5 -#define GEN8_3DSTATE_SBE_SWIZ GEN6_3D(3, 0, 0x51) -#define GEN8_3DSTATE_RASTER GEN6_3D(3, 0, 0x50) +#define GEN8_3DSTATE_SBE_SWIZ GEN4_3D(3, 0, 0x51) +#define GEN8_3DSTATE_RASTER GEN4_3D(3, 0, 0x50) # define GEN8_RASTER_FRONT_WINDING_CCW (1 << 21) # define GEN8_RASTER_CULL_NONE (1 << 16) @@ -28,34 +28,34 @@ # define GEN8_VS_FLOATING_POINT_MODE_ALTERNATE (1 << 16) #define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP \ - GEN6_3D(3, 0, 0x21) -#define GEN8_3DSTATE_PS_BLEND GEN6_3D(3, 0, 0x4d) + GEN4_3D(3, 0, 0x21) +#define GEN8_3DSTATE_PS_BLEND GEN4_3D(3, 0, 0x4d) # define GEN8_PS_BLEND_HAS_WRITEABLE_RT (1 << 30) -#define GEN8_3DSTATE_WM_DEPTH_STENCIL GEN6_3D(3, 0, 0x4e) -#define GEN8_3DSTATE_PS_EXTRA GEN6_3D(3,0, 0x4f) +#define GEN8_3DSTATE_WM_DEPTH_STENCIL GEN4_3D(3, 0, 0x4e) +#define GEN8_3DSTATE_PS_EXTRA GEN4_3D(3, 0, 0x4f) # define GEN8_PSX_PIXEL_SHADER_VALID (1 << 31) # define GEN8_PSX_ATTRIBUTE_ENABLE (1 << 8) -#define GEN8_3DSTATE_DS_STATE_POINTERS GEN6_3D(3, 0, 0x25) +#define GEN8_3DSTATE_DS_STATE_POINTERS GEN4_3D(3, 0, 0x25) -#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS GEN6_3D(3, 0, 0x2c) -#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS GEN6_3D(3, 0, 0x2d) +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS GEN4_3D(3, 0, 0x2c) +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS GEN4_3D(3, 0, 0x2d) -#define GEN8_3DSTATE_VF GEN6_3D(3, 0, 0x0c) -#define GEN8_3DSTATE_VF_TOPOLOGY GEN6_3D(3, 0, 0x4b) +#define GEN8_3DSTATE_VF GEN4_3D(3, 0, 0x0c) +#define GEN8_3DSTATE_VF_TOPOLOGY GEN4_3D(3, 0, 0x4b) -#define GEN8_3DSTATE_BIND_TABLE_POOL_ALLOC GEN6_3D(3, 1, 0x19) -#define GEN8_3DSTATE_GATHER_POOL_ALLOC GEN6_3D(3, 1, 0x1a) -#define GEN8_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC GEN6_3D(3, 1, 0x1b) -#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS GEN6_3D(3, 1, 0x13) -#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS GEN6_3D(3, 1, 0x14) -#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS GEN6_3D(3, 1, 0x15) +#define GEN8_3DSTATE_BIND_TABLE_POOL_ALLOC GEN4_3D(3, 1, 0x19) +#define GEN8_3DSTATE_GATHER_POOL_ALLOC GEN4_3D(3, 1, 0x1a) +#define GEN8_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC GEN4_3D(3, 1, 0x1b) +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS GEN4_3D(3, 1, 0x13) +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS GEN4_3D(3, 1, 0x14) +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS GEN4_3D(3, 1, 0x15) -#define GEN8_3DSTATE_VF_SGVS GEN6_3D(3, 0, 0x4a) -#define GEN8_3DSTATE_SO_DECL_LIST GEN6_3D(3, 1, 0x17) -#define GEN8_3DSTATE_SO_BUFFER GEN6_3D(3, 1, 0x18) -#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0 GEN6_3D(3, 1, 0x02) -#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1 GEN6_3D(3, 1, 0x0c) +#define GEN8_3DSTATE_VF_SGVS GEN4_3D(3, 0, 0x4a) +#define GEN8_3DSTATE_SO_DECL_LIST GEN4_3D(3, 1, 0x17) +#define GEN8_3DSTATE_SO_BUFFER GEN4_3D(3, 1, 0x18) +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0 GEN4_3D(3, 1, 0x02) +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1 GEN4_3D(3, 1, 0x0c) /* Some random bits that we care about */ #define GEN8_VB0_BUFFER_ADDR_MOD_EN (1 << 14) diff --git a/lib/gen9_render.h b/lib/gen9_render.h index 90f56053..77f4966c 100644 --- a/lib/gen9_render.h +++ b/lib/gen9_render.h @@ -3,7 +3,7 @@ #include "gen8_render.h" -#define GEN9_3DSTATE_COMPONENT_PACKING GEN6_3D(3, 0, 0x55) +#define GEN9_3DSTATE_COMPONENT_PACKING GEN4_3D(3, 0, 0x55) #define GEN9_SBE_ACTIVE_COMPONENT_NONE 0 #define GEN9_SBE_ACTIVE_COMPONENT_XY 1 @@ -11,6 +11,6 @@ #define GEN9_SBE_ACTIVE_COMPONENT_XYZW 3 #define GEN9_PIPELINE_SELECTION_MASK (3 << 8) -#define GEN9_PIPELINE_SELECT (GEN6_3D(1, 1, 4) | (3 << 8)) +#define GEN9_PIPELINE_SELECT (GEN4_3D(1, 1, 4) | (3 << 8)) #endif diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c index eebc9bf2..87916927 100644 --- a/lib/rendercopy_gen6.c +++ b/lib/rendercopy_gen6.c @@ -129,7 +129,7 @@ gen6_bind_surfaces(struct intel_batchbuffer *batch, static void gen6_emit_sip(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_STATE_SIP | 0); + OUT_BATCH(GEN4_STATE_SIP | 0); OUT_BATCH(0); } @@ -146,7 +146,7 @@ gen6_emit_urb(struct intel_batchbuffer *batch) static void gen6_emit_state_base_address(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2)); + OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2)); OUT_BATCH(0); /* general */ OUT_RELOC(batch->bo, /* surface */ I915_GEM_DOMAIN_INSTRUCTION, 0, @@ -237,23 +237,23 @@ gen6_emit_wm_constants(struct intel_batchbuffer *batch) static void gen6_emit_null_depth_buffer(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_3DSTATE_DEPTH_BUFFER | (7 - 2)); - OUT_BATCH(SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT | - GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT); + OUT_BATCH(GEN4_3DSTATE_DEPTH_BUFFER | (7 - 2)); + OUT_BATCH(SURFACE_NULL << GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT | + GEN4_DEPTHFORMAT_D32_FLOAT << GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); - OUT_BATCH(GEN6_3DSTATE_CLEAR_PARAMS | (2 - 2)); + OUT_BATCH(GEN4_3DSTATE_CLEAR_PARAMS | (2 - 2)); OUT_BATCH(0); } static void gen6_emit_invariant(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D); + OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D); OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2)); OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | @@ -332,7 +332,7 @@ gen6_emit_wm(struct intel_batchbuffer *batch, int kernel) static void gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table) { - OUT_BATCH(GEN6_3DSTATE_BINDING_TABLE_POINTERS | + OUT_BATCH(GEN4_3DSTATE_BINDING_TABLE_POINTERS | GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS | (4 - 2)); OUT_BATCH(0); /* vs */ @@ -343,7 +343,7 @@ gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table) static void gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, const struct igt_buf *dst) { - OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); + OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); OUT_BATCH(0); OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1)); OUT_BATCH(0); @@ -359,39 +359,39 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) * * dword 4-11 are fetched from vertex buffer */ - OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2)); + OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2)); - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); /* x,y */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); /* u0, v0 */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT | 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); } static uint32_t gen6_create_cc_viewport(struct intel_batchbuffer *batch) { - struct gen6_cc_viewport *vp; + struct gen4_cc_viewport *vp; vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32); @@ -439,41 +439,41 @@ gen6_create_sampler(struct intel_batchbuffer *batch, /* We use the legacy mode to get the semantics specified by * the Render extension. */ - ss->ss0.border_color_mode = GEN6_BORDER_COLOR_MODE_LEGACY; + ss->ss0.border_color_mode = GEN4_BORDER_COLOR_MODE_LEGACY; switch (filter) { default: case SAMPLER_FILTER_NEAREST: - ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST; - ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST; + ss->ss0.min_filter = GEN4_MAPFILTER_NEAREST; + ss->ss0.mag_filter = GEN4_MAPFILTER_NEAREST; break; case SAMPLER_FILTER_BILINEAR: - ss->ss0.min_filter = GEN6_MAPFILTER_LINEAR; - ss->ss0.mag_filter = GEN6_MAPFILTER_LINEAR; + ss->ss0.min_filter = GEN4_MAPFILTER_LINEAR; + ss->ss0.mag_filter = GEN4_MAPFILTER_LINEAR; break; } switch (extend) { default: case SAMPLER_EXTEND_NONE: - ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER; - ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER; - ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER; + ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER; + ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER; + ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER; break; case SAMPLER_EXTEND_REPEAT: - ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_WRAP; - ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_WRAP; - ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_WRAP; + ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_WRAP; + ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_WRAP; + ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_WRAP; break; case SAMPLER_EXTEND_PAD: - ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; + ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; break; case SAMPLER_EXTEND_REFLECT: - ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_MIRROR; - ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_MIRROR; - ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_MIRROR; + ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_MIRROR; + ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_MIRROR; + ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_MIRROR; break; } @@ -482,9 +482,9 @@ gen6_create_sampler(struct intel_batchbuffer *batch, static void gen6_emit_vertex_buffer(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | 3); - OUT_BATCH(VB0_VERTEXDATA | - 0 << VB0_BUFFER_INDEX_SHIFT | + OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | 3); + OUT_BATCH(GEN6_VB0_VERTEXDATA | + 0 << GEN6_VB0_BUFFER_INDEX_SHIFT | VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT); OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, 0); OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, batch->bo->size-1); @@ -495,9 +495,9 @@ static uint32_t gen6_emit_primitive(struct intel_batchbuffer *batch) { uint32_t offset; - OUT_BATCH(GEN6_3DPRIMITIVE | - GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | - _3DPRIM_RECTLIST << GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT | + OUT_BATCH(GEN4_3DPRIMITIVE | + GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL | + _3DPRIM_RECTLIST << GEN4_3DPRIMITIVE_TOPOLOGY_SHIFT | 0 << 9 | 4); OUT_BATCH(3); /* vertex count */ diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c index caaa05ca..9ad619d8 100644 --- a/lib/rendercopy_gen7.c +++ b/lib/rendercopy_gen7.c @@ -101,35 +101,35 @@ gen7_bind_buf(struct intel_batchbuffer *batch, static void gen7_emit_vertex_elements(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | + OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | ((2 * (1 + 2)) + 1 - 2)); - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); /* x,y */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); /* s,t */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); } static uint32_t @@ -166,9 +166,9 @@ static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch, int width, int height, uint32_t offset) { - OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (5 - 2)); - OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | - VB0_VERTEXDATA | + OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (5 - 2)); + OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT | + GEN6_VB0_VERTEXDATA | GEN7_VB0_ADDRESS_MODIFY_ENABLE | 4 * 2 << VB0_BUFFER_PITCH_SHIFT); @@ -207,7 +207,7 @@ gen7_emit_binding_table(struct intel_batchbuffer *batch, static void gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch, const struct igt_buf *dst) { - OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); + OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); OUT_BATCH(0); OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1)); OUT_BATCH(0); @@ -232,7 +232,7 @@ gen7_create_blend_state(struct intel_batchbuffer *batch) static void gen7_emit_state_base_address(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2)); + OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2)); OUT_BATCH(0); OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); @@ -248,7 +248,7 @@ gen7_emit_state_base_address(struct intel_batchbuffer *batch) static uint32_t gen7_create_cc_viewport(struct intel_batchbuffer *batch) { - struct gen6_cc_viewport *vp; + struct gen4_cc_viewport *vp; vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32); vp->min_depth = -1.e35; @@ -275,12 +275,12 @@ gen7_create_sampler(struct intel_batchbuffer *batch) ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 32); - ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST; - ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST; + ss->ss0.min_filter = GEN4_MAPFILTER_NEAREST; + ss->ss0.mag_filter = GEN4_MAPFILTER_NEAREST; - ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; + ss->ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss->ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss->ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; ss->ss3.non_normalized_coord = 1; @@ -476,8 +476,8 @@ static void gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch) { OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2)); - OUT_BATCH(SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT | - GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT); + OUT_BATCH(SURFACE_NULL << GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT | + GEN4_DEPTHFORMAT_D32_FLOAT << GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT); OUT_BATCH(0); /* disable depth, stencil and hiz */ OUT_BATCH(0); OUT_BATCH(0); @@ -520,7 +520,7 @@ void gen7_render_copyfunc(struct intel_batchbuffer *batch, igt_assert(batch->ptr < &batch->buffer[4095]); batch->ptr = batch->buffer; - OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D); + OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D); gen7_emit_state_base_address(batch); gen7_emit_multisample(batch); @@ -546,8 +546,8 @@ void gen7_render_copyfunc(struct intel_batchbuffer *batch, gen7_emit_binding_table(batch, src, dst, ps_binding_table); gen7_emit_drawing_rectangle(batch, dst); - OUT_BATCH(GEN6_3DPRIMITIVE | (7 - 2)); - OUT_BATCH(GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST); + OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2)); + OUT_BATCH(GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST); OUT_BATCH(3); OUT_BATCH(0); OUT_BATCH(1); /* single instance */ diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c index 5a9bf32e..1319b9e4 100644 --- a/lib/rendercopy_gen8.c +++ b/lib/rendercopy_gen8.c @@ -228,11 +228,11 @@ gen8_create_sampler(struct intel_batchbuffer *batch, annotation_add_state(aub, AUB_TRACE_SAMPLER_STATE, offset, sizeof(*ss)); - ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST; - ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST; - ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; + ss->ss0.min_filter = GEN4_MAPFILTER_NEAREST; + ss->ss0.mag_filter = GEN4_MAPFILTER_NEAREST; + ss->ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss->ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss->ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; /* I've experimented with non-normalized coordinates and using the LD * sampler fetch, but couldn't make it work. */ @@ -314,18 +314,18 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) { * dword 4-7: position (x, y, 0, 1.0), * dword 8-11: texture coordinate 0 (u0, v0, 0, 1.0) */ - OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2)); + OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2)); /* Element state 0. These are 4 dwords of 0 required for the VUE format. * We don't really know or care what they do. */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); /* we specify 0, but it's really does not exist */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); /* Element state 1 - Our "destination" vertices. These are passed down * through the pipeline, and eventually make it to the pixel shader as @@ -333,25 +333,25 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) { * signed/scaled because of gen6 rendercopy. I see no particular reason * for doing this though. */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); /* Element state 2. Last but not least we store the U,V components as * normalized floats. These will be used in the pixel shader to sample * from the source buffer. */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT | 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); } /* @@ -362,8 +362,8 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) { */ static void gen8_emit_vertex_buffer(struct intel_batchbuffer *batch, uint32_t offset) { - OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2)); - OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */ + OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2)); + OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */ GEN8_VB0_BUFFER_ADDR_MOD_EN | /* Address Modify Enable */ VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT); OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset); @@ -414,7 +414,7 @@ static uint32_t gen6_create_cc_viewport(struct intel_batchbuffer *batch, struct annotations_context *aub) { - struct gen6_cc_viewport *vp; + struct gen4_cc_viewport *vp; uint32_t offset; vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32); @@ -468,7 +468,7 @@ gen6_create_scissor_rect(struct intel_batchbuffer *batch, static void gen8_emit_sip(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_STATE_SIP | (3 - 2)); + OUT_BATCH(GEN4_STATE_SIP | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); } @@ -489,7 +489,7 @@ gen7_emit_push_constants(struct intel_batchbuffer *batch) { static void gen8_emit_state_base_address(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (16 - 2)); + OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (16 - 2)); /* general */ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); @@ -826,7 +826,7 @@ gen7_emit_clear(struct intel_batchbuffer *batch) { static void gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, const struct igt_buf *dst) { - OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); + OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); OUT_BATCH(0); OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1)); OUT_BATCH(0); @@ -845,7 +845,7 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset OUT_BATCH(0); OUT_BATCH(0); - OUT_BATCH(GEN6_3DPRIMITIVE | (7-2)); + OUT_BATCH(GEN4_3DPRIMITIVE | (7-2)); OUT_BATCH(0); /* gen8+ ignore the topology type field */ OUT_BATCH(3); /* vertex count */ OUT_BATCH(0); /* We're specifying this instead with offset in GEN6_3DSTATE_VERTEX_BUFFERS */ @@ -929,7 +929,7 @@ void gen8_render_copyfunc(struct intel_batchbuffer *batch, /* Start emitting the commands. The order roughly follows the mesa blorp * order */ - OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D); + OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D); gen8_emit_sip(batch); diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index d9e7eaf9..0ed89776 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -237,11 +237,11 @@ gen8_create_sampler(struct intel_batchbuffer *batch) { annotation_add_state(&aub_annotations, AUB_TRACE_SAMPLER_STATE, offset, sizeof(*ss)); - ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST; - ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST; - ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; + ss->ss0.min_filter = GEN4_MAPFILTER_NEAREST; + ss->ss0.mag_filter = GEN4_MAPFILTER_NEAREST; + ss->ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss->ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss->ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; /* I've experimented with non-normalized coordinates and using the LD * sampler fetch, but couldn't make it work. */ @@ -322,18 +322,18 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) { * dword 4-7: position (x, y, 0, 1.0), * dword 8-11: texture coordinate 0 (u0, v0, 0, 1.0) */ - OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2)); + OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2)); /* Element state 0. These are 4 dwords of 0 required for the VUE format. * We don't really know or care what they do. */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); /* we specify 0, but it's really does not exist */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); /* Element state 1 - Our "destination" vertices. These are passed down * through the pipeline, and eventually make it to the pixel shader as @@ -341,25 +341,25 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) { * signed/scaled because of gen6 rendercopy. I see no particular reason * for doing this though. */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); /* Element state 2. Last but not least we store the U,V components as * normalized floats. These will be used in the pixel shader to sample * from the source buffer. */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT | 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); } /* @@ -370,8 +370,8 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) { */ static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch, uint32_t offset) { - OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2)); - OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */ + OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2)); + OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */ GEN8_VB0_BUFFER_ADDR_MOD_EN | /* Address Modify Enable */ VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT); OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset); @@ -419,7 +419,7 @@ gen8_create_blend_state(struct intel_batchbuffer *batch) static uint32_t gen6_create_cc_viewport(struct intel_batchbuffer *batch) { - struct gen6_cc_viewport *vp; + struct gen4_cc_viewport *vp; uint32_t offset; vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32); @@ -470,7 +470,7 @@ gen6_create_scissor_rect(struct intel_batchbuffer *batch) static void gen8_emit_sip(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_STATE_SIP | (3 - 2)); + OUT_BATCH(GEN4_STATE_SIP | (3 - 2)); OUT_BATCH(0); OUT_BATCH(0); } @@ -495,7 +495,7 @@ gen9_emit_state_base_address(struct intel_batchbuffer *batch) { /* WaBindlessSurfaceStateModifyEnable:skl,bxt */ /* The length has to be one less if we dont modify bindless state */ - OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (19 - 1 - 2)); + OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (19 - 1 - 2)); /* general */ OUT_BATCH(0 | BASE_ADDRESS_MODIFY); @@ -844,7 +844,7 @@ gen7_emit_clear(struct intel_batchbuffer *batch) { static void gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, const struct igt_buf *dst) { - OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); + OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); OUT_BATCH(0); OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1)); OUT_BATCH(0); @@ -866,7 +866,7 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset OUT_BATCH(0); OUT_BATCH(0); - OUT_BATCH(GEN6_3DPRIMITIVE | (7-2)); + OUT_BATCH(GEN4_3DPRIMITIVE | (7-2)); OUT_BATCH(0); /* gen8+ ignore the topology type field */ OUT_BATCH(3); /* vertex count */ OUT_BATCH(0); /* We're specifying this instead with offset in GEN6_3DSTATE_VERTEX_BUFFERS */ @@ -946,7 +946,7 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch, /* Start emitting the commands. The order roughly follows the mesa blorp * order */ - OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D | + OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D | GEN9_PIPELINE_SELECTION_MASK); gen8_emit_sip(batch); diff --git a/tools/null_state_gen/intel_renderstate_gen6.c b/tools/null_state_gen/intel_renderstate_gen6.c index 13b1e92e..c779ea42 100644 --- a/tools/null_state_gen/intel_renderstate_gen6.c +++ b/tools/null_state_gen/intel_renderstate_gen6.c @@ -81,7 +81,7 @@ gen6_bind_surfaces(struct intel_batchbuffer *batch) static void gen6_emit_sip(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_STATE_SIP | 0); + OUT_BATCH(GEN4_STATE_SIP | 0); OUT_BATCH(0); } @@ -98,7 +98,7 @@ gen6_emit_urb(struct intel_batchbuffer *batch) static void gen6_emit_state_base_address(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2)); + OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2)); OUT_BATCH(0); /* general */ OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, @@ -189,23 +189,23 @@ gen6_emit_wm_constants(struct intel_batchbuffer *batch) static void gen6_emit_null_depth_buffer(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_3DSTATE_DEPTH_BUFFER | (7 - 2)); - OUT_BATCH(SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT | - GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT); + OUT_BATCH(GEN4_3DSTATE_DEPTH_BUFFER | (7 - 2)); + OUT_BATCH(SURFACE_NULL << GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT | + GEN4_DEPTHFORMAT_D32_FLOAT << GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); - OUT_BATCH(GEN6_3DSTATE_CLEAR_PARAMS | (2 - 2)); + OUT_BATCH(GEN4_3DSTATE_CLEAR_PARAMS | (2 - 2)); OUT_BATCH(0); } static void gen6_emit_invariant(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D); + OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D); OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2)); OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | @@ -284,7 +284,7 @@ gen6_emit_wm(struct intel_batchbuffer *batch, int kernel) static void gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table) { - OUT_BATCH(GEN6_3DSTATE_BINDING_TABLE_POINTERS | + OUT_BATCH(GEN4_3DSTATE_BINDING_TABLE_POINTERS | GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS | (4 - 2)); OUT_BATCH(0); /* vs */ @@ -295,7 +295,7 @@ gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table) static void gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); + OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); OUT_BATCH(0xffffffff); OUT_BATCH(0 | 0); OUT_BATCH(0); @@ -311,39 +311,39 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) * * dword 4-11 are fetched from vertex buffer */ - OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2)); + OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2)); - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); /* x,y */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); /* u0, v0 */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT | 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); } static uint32_t gen6_create_cc_viewport(struct intel_batchbuffer *batch) { - struct gen6_cc_viewport vp; + struct gen4_cc_viewport vp; memset(&vp, 0, sizeof(vp)); @@ -392,41 +392,41 @@ gen6_create_sampler(struct intel_batchbuffer *batch, /* We use the legacy mode to get the semantics specified by * the Render extension. */ - ss.ss0.border_color_mode = GEN6_BORDER_COLOR_MODE_LEGACY; + ss.ss0.border_color_mode = GEN4_BORDER_COLOR_MODE_LEGACY; switch (filter) { default: case SAMPLER_FILTER_NEAREST: - ss.ss0.min_filter = GEN6_MAPFILTER_NEAREST; - ss.ss0.mag_filter = GEN6_MAPFILTER_NEAREST; + ss.ss0.min_filter = GEN4_MAPFILTER_NEAREST; + ss.ss0.mag_filter = GEN4_MAPFILTER_NEAREST; break; case SAMPLER_FILTER_BILINEAR: - ss.ss0.min_filter = GEN6_MAPFILTER_LINEAR; - ss.ss0.mag_filter = GEN6_MAPFILTER_LINEAR; + ss.ss0.min_filter = GEN4_MAPFILTER_LINEAR; + ss.ss0.mag_filter = GEN4_MAPFILTER_LINEAR; break; } switch (extend) { default: case SAMPLER_EXTEND_NONE: - ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER; - ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER; - ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER; + ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER; + ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER; + ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER; break; case SAMPLER_EXTEND_REPEAT: - ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_WRAP; - ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_WRAP; - ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_WRAP; + ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_WRAP; + ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_WRAP; + ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_WRAP; break; case SAMPLER_EXTEND_PAD: - ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; + ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; break; case SAMPLER_EXTEND_REFLECT: - ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_MIRROR; - ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_MIRROR; - ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_MIRROR; + ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_MIRROR; + ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_MIRROR; + ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_MIRROR; break; } @@ -450,9 +450,9 @@ static void gen6_emit_vertex_buffer(struct intel_batchbuffer *batch) offset = gen6_create_vertex_buffer(batch); - OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | 3); - OUT_BATCH(VB0_VERTEXDATA | - 0 << VB0_BUFFER_INDEX_SHIFT | + OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | 3); + OUT_BATCH(GEN6_VB0_VERTEXDATA | + 0 << GEN6_VB0_BUFFER_INDEX_SHIFT | VB0_NULL_VERTEX_BUFFER | 0 << VB0_BUFFER_PITCH_SHIFT); OUT_RELOC_STATE(batch, I915_GEM_DOMAIN_VERTEX, 0, offset); diff --git a/tools/null_state_gen/intel_renderstate_gen7.c b/tools/null_state_gen/intel_renderstate_gen7.c index 75ee9d6d..519ad30a 100644 --- a/tools/null_state_gen/intel_renderstate_gen7.c +++ b/tools/null_state_gen/intel_renderstate_gen7.c @@ -49,36 +49,36 @@ gen7_bind_buf_null(struct intel_batchbuffer *batch) static void gen7_emit_vertex_elements(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | + OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | ((2 * (1 + 2)) + 1 - 2)); - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); /* x,y */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); /* s,t */ - OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | + OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID | SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */ - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); + OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); } static uint32_t @@ -95,9 +95,9 @@ static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch) offset = gen7_create_vertex_buffer(batch); - OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (5 - 2)); - OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | - VB0_VERTEXDATA | + OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (5 - 2)); + OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT | + GEN6_VB0_VERTEXDATA | GEN7_VB0_ADDRESS_MODIFY_ENABLE | VB0_NULL_VERTEX_BUFFER | 4*2 << VB0_BUFFER_PITCH_SHIFT); @@ -130,7 +130,7 @@ gen7_emit_binding_table(struct intel_batchbuffer *batch) static void gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); + OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); /* Purposedly set min > max for null rectangle */ OUT_BATCH(0xffffffff); OUT_BATCH(0 | 0); @@ -155,7 +155,7 @@ gen7_create_blend_state(struct intel_batchbuffer *batch) static void gen7_emit_state_base_address(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2)); + OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2)); OUT_BATCH(0); OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); @@ -171,7 +171,7 @@ gen7_emit_state_base_address(struct intel_batchbuffer *batch) static uint32_t gen7_create_cc_viewport(struct intel_batchbuffer *batch) { - struct gen6_cc_viewport vp; + struct gen4_cc_viewport vp; memset(&vp, 0, sizeof(vp)); vp.min_depth = -1.e35; @@ -196,12 +196,12 @@ gen7_create_sampler(struct intel_batchbuffer *batch) struct gen7_sampler_state ss; memset(&ss, 0, sizeof(ss)); - ss.ss0.min_filter = GEN6_MAPFILTER_NEAREST; - ss.ss0.mag_filter = GEN6_MAPFILTER_NEAREST; + ss.ss0.min_filter = GEN4_MAPFILTER_NEAREST; + ss.ss0.mag_filter = GEN4_MAPFILTER_NEAREST; - ss.ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss.ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; - ss.ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP; + ss.ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss.ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; + ss.ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP; ss.ss3.non_normalized_coord = 1; @@ -402,7 +402,7 @@ gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch) { OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2)); OUT_BATCH(SURFACE_NULL << GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT | - GEN6_DEPTHFORMAT_D32_FLOAT << + GEN4_DEPTHFORMAT_D32_FLOAT << GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT); OUT_BATCH(0); /* disable depth, stencil and hiz */ OUT_BATCH(0); @@ -417,7 +417,7 @@ gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch) void gen7_setup_null_render_state(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D); + OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D); gen7_emit_state_base_address(batch); gen7_emit_multisample(batch); @@ -442,8 +442,8 @@ void gen7_setup_null_render_state(struct intel_batchbuffer *batch) gen7_emit_binding_table(batch); gen7_emit_drawing_rectangle(batch); - OUT_BATCH(GEN6_3DPRIMITIVE | (7 - 2)); - OUT_BATCH(GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST); + OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2)); + OUT_BATCH(GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST); OUT_BATCH(3); OUT_BATCH(0); OUT_BATCH(1); /* single instance */ diff --git a/tools/null_state_gen/intel_renderstate_gen8.c b/tools/null_state_gen/intel_renderstate_gen8.c index c6973e0e..17822c44 100644 --- a/tools/null_state_gen/intel_renderstate_gen8.c +++ b/tools/null_state_gen/intel_renderstate_gen8.c @@ -152,7 +152,7 @@ static void gen8_emit_so_buffer(struct intel_batchbuffer *batch, const int index static void gen8_emit_state_base_address(struct intel_batchbuffer *batch) { const unsigned offset = 0; - OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (16 - 2)); + OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (16 - 2)); /* general */ OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY); @@ -200,10 +200,10 @@ static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch) const int buffers = 33; int i; - OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | ((4 * buffers) - 1)); + OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | ((4 * buffers) - 1)); for (i = 0; i < buffers; i++) { - OUT_BATCH(i << VB0_BUFFER_INDEX_SHIFT | + OUT_BATCH(i << GEN6_VB0_BUFFER_INDEX_SHIFT | GEN8_VB0_BUFFER_ADDR_MOD_EN); OUT_BATCH(0); /* Addr */ OUT_BATCH(0); @@ -216,16 +216,16 @@ static void gen6_emit_vertex_elements(struct intel_batchbuffer *batch) const int elements = 34; int i; - OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | ((2 * elements - 1))); + OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | ((2 * elements - 1))); for (i = 0; i < elements; i++) { if (i == 0) { - OUT_BATCH(VE0_VALID | i); + OUT_BATCH(GEN6_VE0_VALID | i); OUT_BATCH( - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT ); } else { OUT_BATCH(0); @@ -314,13 +314,13 @@ static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer * static void gen8_emit_primitive(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_3DPRIMITIVE | (7-2)); - OUT_BATCH(4); /* gen8+ ignore the topology type field */ - OUT_BATCH(1); /* vertex count */ - OUT_BATCH(0); - OUT_BATCH(1); /* single instance */ - OUT_BATCH(0); /* start instance location */ - OUT_BATCH(0); /* index buffer offset, ignored */ + OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2)); + OUT_BATCH(4); /* gen8+ ignore the topology type field */ + OUT_BATCH(1); /* vertex count */ + OUT_BATCH(0); + OUT_BATCH(1); /* single instance */ + OUT_BATCH(0); /* start instance location */ + OUT_BATCH(0); /* index buffer offset, ignored */ } void gen8_setup_null_render_state(struct intel_batchbuffer *batch) @@ -334,7 +334,7 @@ void gen8_setup_null_render_state(struct intel_batchbuffer *batch) OUT_BATCH(0); OUT_BATCH(0); - OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D); + OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D); gen8_emit_wm(batch); gen8_emit_ps(batch); @@ -383,8 +383,8 @@ void gen8_setup_null_render_state(struct intel_batchbuffer *batch) gen8_emit_state_base_address(batch); - OUT_CMD(GEN6_STATE_SIP, 3); - OUT_CMD(GEN6_3DSTATE_DRAWING_RECTANGLE, 4); + OUT_CMD(GEN4_STATE_SIP, 3); + OUT_CMD(GEN4_3DSTATE_DRAWING_RECTANGLE, 4); OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8); gen8_emit_chroma_key(batch, 0); diff --git a/tools/null_state_gen/intel_renderstate_gen9.c b/tools/null_state_gen/intel_renderstate_gen9.c index 9f338bbf..3701acd1 100644 --- a/tools/null_state_gen/intel_renderstate_gen9.c +++ b/tools/null_state_gen/intel_renderstate_gen9.c @@ -163,11 +163,11 @@ static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch) const int buffers = 33; int i; - OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | + OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (((4 * buffers) + 1)- 2) /* DWORD count - 2 */); for (i = 0; i < buffers; i++) { - OUT_BATCH(i << VB0_BUFFER_INDEX_SHIFT | + OUT_BATCH(i << GEN6_VB0_BUFFER_INDEX_SHIFT | GEN8_VB0_BUFFER_ADDR_MOD_EN); OUT_BATCH(0); /* Address */ OUT_BATCH(0); @@ -180,16 +180,16 @@ static void gen8_emit_vertex_elements(struct intel_batchbuffer *batch) const int elements = 34; int i; - OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | + OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (((2 * elements) + 1) - 2) /* DWORD count - 2 */); /* Element 0 */ - OUT_BATCH(VE0_VALID); + OUT_BATCH(GEN6_VE0_VALID); OUT_BATCH( - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | + GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); /* Elements 1 -> 33 */ for (i = 1; i < elements; i++) { OUT_BATCH(0); @@ -277,18 +277,18 @@ static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer * static void gen8_emit_primitive(struct intel_batchbuffer *batch) { - OUT_BATCH(GEN6_3DPRIMITIVE | (7-2)); - OUT_BATCH(4); /* gen8+ ignore the topology type field */ - OUT_BATCH(1); /* vertex count */ - OUT_BATCH(0); - OUT_BATCH(1); /* single instance */ - OUT_BATCH(0); /* start instance location */ - OUT_BATCH(0); /* index buffer offset, ignored */ + OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2)); + OUT_BATCH(4); /* gen8+ ignore the topology type field */ + OUT_BATCH(1); /* vertex count */ + OUT_BATCH(0); + OUT_BATCH(1); /* single instance */ + OUT_BATCH(0); /* start instance location */ + OUT_BATCH(0); /* index buffer offset, ignored */ } static void gen9_emit_state_base_address(struct intel_batchbuffer *batch) { const unsigned offset = 0; - OUT_BATCH(GEN6_STATE_BASE_ADDRESS | + OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (19 - 2) /* DWORD count - 2 */); /* general state base address - requires BB address @@ -414,8 +414,8 @@ void gen9_setup_null_render_state(struct intel_batchbuffer *batch) /* State base addresses */ gen9_emit_state_base_address(batch); - OUT_CMD(GEN6_STATE_SIP, 3); - OUT_CMD(GEN6_3DSTATE_DRAWING_RECTANGLE, 4); + OUT_CMD(GEN4_STATE_SIP, 3); + OUT_CMD(GEN4_3DSTATE_DRAWING_RECTANGLE, 4); OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8); /* Chroma key */ -- cgit v1.2.3