From bba38422e7f903094562f1b78cc3579683c0a667 Mon Sep 17 00:00:00 2001 From: Katarzyna Dec Date: Wed, 3 Oct 2018 15:48:40 +0200 Subject: lib/i915: Move shaders directory In shaders/ directory we got Intel specific information. As igt is a project for more vendors, let's move this directory to lib/i915. v2: Changed shaders directory path in library files comments. Signed-off-by: Katarzyna Dec Cc: Arkadiusz Hiler Cc: Petri Latvala Cc: Kalamarz Lukasz Cc: Antonio Argenziano Reviewed-by: Chris Wilson --- lib/gpgpu_fill.c | 2 +- lib/i915/shaders/README | 25 +++++++++++ lib/i915/shaders/converter.py | 26 ++++++++++++ lib/i915/shaders/gpgpu/gpgpu_fill.gxa | 39 ++++++++++++++++++ lib/i915/shaders/gpgpu/gpgpu_fill_gen8.asm | 10 +++++ lib/i915/shaders/gpgpu/gpgpu_fill_gen9.asm | 10 +++++ lib/i915/shaders/media/media_fill.gxa | 44 ++++++++++++++++++++ lib/i915/shaders/media/media_fill_gen8.asm | 11 +++++ lib/i915/shaders/ps/blit.g7a | 66 ++++++++++++++++++++++++++++++ lib/i915/shaders/ps/blit_gen8.asm | 7 ++++ lib/i915/shaders/ps/neg1_gen8.asm | 9 ++++ lib/i915/shaders/ps/neg1_test.g7a | 9 ++++ lib/rendercopy_gen8.c | 2 +- lib/rendercopy_gen9.c | 2 +- shaders/README | 25 ----------- shaders/converter.py | 26 ------------ shaders/gpgpu/gpgpu_fill.gxa | 39 ------------------ shaders/gpgpu/gpgpu_fill_gen8.asm | 10 ----- shaders/gpgpu/gpgpu_fill_gen9.asm | 10 ----- shaders/media/media_fill.gxa | 44 -------------------- shaders/media/media_fill_gen8.asm | 11 ----- shaders/ps/blit.g7a | 66 ------------------------------ shaders/ps/blit_gen8.asm | 7 ---- shaders/ps/neg1_gen8.asm | 9 ---- shaders/ps/neg1_test.g7a | 9 ---- 25 files changed, 259 insertions(+), 259 deletions(-) create mode 100644 lib/i915/shaders/README create mode 100644 lib/i915/shaders/converter.py create mode 100644 lib/i915/shaders/gpgpu/gpgpu_fill.gxa create mode 100644 lib/i915/shaders/gpgpu/gpgpu_fill_gen8.asm create mode 100644 lib/i915/shaders/gpgpu/gpgpu_fill_gen9.asm create mode 100644 lib/i915/shaders/media/media_fill.gxa create mode 100644 lib/i915/shaders/media/media_fill_gen8.asm create mode 100644 lib/i915/shaders/ps/blit.g7a create mode 100644 lib/i915/shaders/ps/blit_gen8.asm create mode 100644 lib/i915/shaders/ps/neg1_gen8.asm create mode 100644 lib/i915/shaders/ps/neg1_test.g7a delete mode 100644 shaders/README delete mode 100644 shaders/converter.py delete mode 100644 shaders/gpgpu/gpgpu_fill.gxa delete mode 100644 shaders/gpgpu/gpgpu_fill_gen8.asm delete mode 100644 shaders/gpgpu/gpgpu_fill_gen9.asm delete mode 100644 shaders/media/media_fill.gxa delete mode 100644 shaders/media/media_fill_gen8.asm delete mode 100644 shaders/ps/blit.g7a delete mode 100644 shaders/ps/blit_gen8.asm delete mode 100644 shaders/ps/neg1_gen8.asm delete mode 100644 shaders/ps/neg1_test.g7a diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c index af2935ab..003f4616 100644 --- a/lib/gpgpu_fill.c +++ b/lib/gpgpu_fill.c @@ -34,7 +34,7 @@ #include "gpgpu_fill.h" #include "gpu_cmds.h" -/* shaders/gpgpu/gpgpu_fill.gxa */ +/* lib/i915/shaders/gpgpu/gpgpu_fill.gxa */ static const uint32_t gen7_gpgpu_kernel[][4] = { { 0x00400001, 0x20200231, 0x00000020, 0x00000000 }, { 0x00000041, 0x20400c21, 0x00000004, 0x00000010 }, diff --git a/lib/i915/shaders/README b/lib/i915/shaders/README new file mode 100644 index 00000000..06b9883c --- /dev/null +++ b/lib/i915/shaders/README @@ -0,0 +1,25 @@ +This directory is for shaders used in media_fill, gpgpu_fill, rendercopy +and media_spin libraries. + +Till Gen8 shaders were generated using intel-gen4asm script (implementation in +assembler/ directory). From Gen8 it is possible to use Intel Graphics Assembler +to generate binary from asm instructions. +https://github.com/intel/intel-graphics-compiler + 1. Clone IGC project + 2. Go to igc/visa/iga + 3. Build iga + cmake . && make + +For maintaining compatibility with our tests there is a bin to hex converter +written in python: + $>converter.py input_file > output_file +e.g.$>python converter.py gen9_iga_output > gen9_hex_array + +Commands used to generate the shader on gen7 +$> m4 gpgpu_fill.gxa > gpgpu_fill.gxm +$> intel-gen4asm -g 7 -o gpgpu_fill.gxm + +Commands used to generate the shader on gen8 +$> m4 media_fill.gxa > media_fill.gxm +$> intel-gen4asm -g 8 -o media_fill.gxm + diff --git a/lib/i915/shaders/converter.py b/lib/i915/shaders/converter.py new file mode 100644 index 00000000..25a79a94 --- /dev/null +++ b/lib/i915/shaders/converter.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +import struct +import sys +import argparse + +parser=argparse.ArgumentParser( + description='''Script for converting shaders from binary to hex ''' ) +parser = argparse.ArgumentParser(prog='converter.py', usage='%(prog)s binary_file') +parser.add_argument('binary', nargs=1, help='binary_file') +args=parser.parse_args() + +print "static const uint32_t kernel[][4] = {" +with open(sys.argv[1], 'r') as f: + fmt = 'UD') +define(`ORIG_X', `g2.0<1>UD') +define(`ORIG_Y', `g2.4<1>UD') +define(`COLOR', `g1.0') +define(`COLORUB', `COLOR<0,1,0>UB') +define(`COLORUD', `COLOR<0,1,0>UD') +define(`X', `g0.4<0,1,0>UD') +define(`Y', `g0.24<0,1,0>UD') + +mov(4) COLOR<1>UB COLORUB {align1}; + +/* WRITE */ +/* count thread group ID for X/Y offset */ +mul(1) ORIG_X X 0x10UD {align1}; +mov(1) ORIG_Y Y {align1}; +mov(8) g4.0<1>UD g0.0<8,8,1>UD {align1}; +mov(2) g4.0<1>UD ORIG {align1}; +/* Normal mode: for block height 1 row and block width 16 bytes */ +mov(1) g4.8<1>UD 0x0000000fUD {align1}; + +mov(16) g5.0<1>UD COLORUD {align1 compr}; + +/* + * write(0, 0, 10, 12) + * 10: media_block_write + * 12: data cache data port 1 + */ +send(16) 4 acc0<1>UW null write(0, 0, 10, 12) mlen 3 rlen 0 {align1}; + +/* EOT */ +mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; +send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; diff --git a/lib/i915/shaders/gpgpu/gpgpu_fill_gen8.asm b/lib/i915/shaders/gpgpu/gpgpu_fill_gen8.asm new file mode 100644 index 00000000..448e0256 --- /dev/null +++ b/lib/i915/shaders/gpgpu/gpgpu_fill_gen8.asm @@ -0,0 +1,10 @@ + mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub + mul (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud 0x10:ud + mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud + mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud + mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud + mov (1|M0) r4.2<1>:ud 0xF:ud + mov (16|M0) (eq)f0.0 r5.0<1>:ud r1.0<0;1,0>:ud + send (16|M0) acc0.0:uw r4:d 0xC 0x060A8000 // DP_DC1 wr:3h, rd:0, fc: 0x28000 + mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud + send (16|M0) null:uw r112:d 0x27 0x02000010 {EOT} // SPAWNER wr:1, rd:0, fc: 0x10 diff --git a/lib/i915/shaders/gpgpu/gpgpu_fill_gen9.asm b/lib/i915/shaders/gpgpu/gpgpu_fill_gen9.asm new file mode 100644 index 00000000..6f948935 --- /dev/null +++ b/lib/i915/shaders/gpgpu/gpgpu_fill_gen9.asm @@ -0,0 +1,10 @@ + mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub + mul (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud 0x10:ud + mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud + mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud + mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud + mov (1|M0) r4.2<1>:ud 0xF:ud + mov (16|M0) r5.0<1>:ud r1.0<0;1,0>:ud + send (16|M0) acc0.0:uw r4:d 0xC 0x060A8000 // DP_DC1 wr:3h, rd:0, fc: 0x28000 + mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud + send (16|M0) null:uw r112:d 0x27 0x02000010 {EOT} // SPAWNER wr:1, rd:0, fc: 0x10 diff --git a/lib/i915/shaders/media/media_fill.gxa b/lib/i915/shaders/media/media_fill.gxa new file mode 100644 index 00000000..75788906 --- /dev/null +++ b/lib/i915/shaders/media/media_fill.gxa @@ -0,0 +1,44 @@ +/* + * Registers + * g0 -- header + * g1 -- constant + * g2 -- inline data + * g3 -- reserved + * g4-g12 payload for write message + */ +define(`ORIG', `g2.0<2,2,1>UD') +define(`COLOR', `g1.0') +define(`COLORUB', `COLOR<0,1,0>UB') +define(`COLORUD', `COLOR<0,1,0>UD') + +mov(4) COLOR<1>UB COLORUB {align1}; + +/* WRITE */ +mov(8) g4.0<1>UD g0.0<8,8,1>UD {align1}; +mov(2) g4.0<1>UD ORIG {align1}; +mov(1) g4.8<1>UD 0x000f000fUD {align1}; + +mov(16) g5.0<1>UD COLORUD {align1 compr}; +mov(16) g7.0<1>UD COLORUD {align1 compr}; +mov(16) g9.0<1>UD COLORUD {align1 compr}; +mov(16) g11.0<1>UD COLORUD {align1 compr}; + +/* + * comment out the following instruction on Gen7 + * write(0, 0, 10, 12) + * 10: media_block_write + * 12: data cache data port 1 + */ +send(16) 4 acc0<1>UW null write(0, 0, 10, 12) mlen 9 rlen 0 {align1}; + +/* + * uncomment the following instruction on Gen7 + * write(0, 0, 10, 0) + * 10: media_block_write + * 0: reander cache data port + */ +/* send(16) 4 acc0<1>UW null write(0, 0, 10, 0) mlen 9 rlen 0 {align1}; */ + +/* EOT */ +mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; +send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; diff --git a/lib/i915/shaders/media/media_fill_gen8.asm b/lib/i915/shaders/media/media_fill_gen8.asm new file mode 100644 index 00000000..4b6eb84b --- /dev/null +++ b/lib/i915/shaders/media/media_fill_gen8.asm @@ -0,0 +1,11 @@ + mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub + mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud + mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud + mov (1|M0) r4.2<1>:ud 0xF000F:ud + mov (16|M0) r5.0<1>:ud r1.0<0;1,0>:ud + mov (16|M0) r7.0<1>:ud r1.0<0;1,0>:ud + mov (16|M0) r9.0<1>:ud r1.0<0;1,0>:ud + mov (16|M0) r11.0<1>:ud r1.0<0;1,0>:ud + send (16|M0) acc0.0:uw r4:d 0x1000000C 0x120A8000 // DP_DC1 wr:9h, rd:0, fc: 0x28000 + mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud + send (16|M0) null:uw r112:d 0x10000027 0x02000010 {EOT} // SPAWNER wr:1, rd:0, fc: 0x10 diff --git a/lib/i915/shaders/ps/blit.g7a b/lib/i915/shaders/ps/blit.g7a new file mode 100644 index 00000000..deeedcc5 --- /dev/null +++ b/lib/i915/shaders/ps/blit.g7a @@ -0,0 +1,66 @@ +/* Assemble with ".../intel-gen4asm/src/intel-gen4asm -g 7" */ + + +/* Move pixels into g10-g13. The pixel shaader does not load what you want. It + * loads the input data for a plane function to calculate what you want. The + * following is boiler plate code to move our normalized texture coordinates + * (u,v) into g10-g13. It does this 4 subspans (16 pixels) at a time. + * + * This should do the same thing, but it doesn't work for some reason. + * pln(16) g10 g6<0,1,0>F g2<8,8,1>F { align1 }; + * pln(16) g12 g6.16<1>F g2<8,8,1>F { align1 }; + */ +/* U */ +pln (8) g10<1>F g6.0<0,1,0>F g2.0<8,8,1>F { align1 }; /* pixel 0-7 */ +pln (8) g11<1>F g6.0<0,1,0>F g4.0<8,8,1>F { align1 }; /* pixel 8-15 */ +/* V */ +pln (8) g12<1>F g6.16<0,1,0> g2.0<8,8,1>F { align1 }; /* pixel 0-7 */ +pln (8) g13<1>F g6.16<0,1,0> g4.0<8,8,1>F { align1 }; /* pixel 8-15 */ + + +/* Next the we want the sampler to fetch the src texture (ie. src buffer). This + * is done with a pretty simple send message. The output goes to g112, which is + * exactly what we're supposed to use in our final send message. + * In intel-gen4asm, we should end up parsed by the following rule: + * predicate SEND execsize dst sendleadreg sndopr directsrcoperand instoptions + * + * Send message descriptor: + * 28:25 = message len = 4 // our 4 registers have 16 pixels + * 24:20 = response len = 8 // Each pixel is RGBA32, so we need 8 registers + * 19:19 = header present = 0 + * 18:17 = SIMD16 = 2 + * 16:12 = TYPE = 0 (regular sample) + * 11:08 = Sampler index = ignored/0 + * 7:0 = binding table index = src = 1 + * 0x8840001 + * + * Send message extra descriptor + * 5:5 = End of Thread = 0 + * 3:0 = Target Function ID = SFID_SAMPLER (2) + * 0x2 + */ + +send(16) g112 g10 0x2 0x8840001 { align1 }; + +/* g112-g119 now contains the sample source input, and all we must do is write + * it out to the destination render target. This is done with the send message + * as well. The only extra bits are to terminate the pixel shader. + * + * Send message descriptor: + * 28:25 = message len = 8 // 16 pixels RGBA32 + * 24:20 = response len = 0 + * 19:19 = header present = 0 + * 17:14 = message type = Render Target Write (12) + * 12:12 = Last Render Target Select = 1 + * 10:08 = Message Type = SIMD16 (0) + * 07:00 = Binding Table Index = dest = 0 + * 0x10031000 + * + * Send message extra descriptor + * 5:5 = End of Thread = 1 + * 3:0 = Target Function ID = SFID_DP_RC (5) + * 0x25 + */ +send(16) null g112 0x25 0x10031000 { align1, EOT }; + +/* vim: set ft=c ts=4 sw=2 tw=80 et: */ diff --git a/lib/i915/shaders/ps/blit_gen8.asm b/lib/i915/shaders/ps/blit_gen8.asm new file mode 100644 index 00000000..c35b70a1 --- /dev/null +++ b/lib/i915/shaders/ps/blit_gen8.asm @@ -0,0 +1,7 @@ + pln (8|M0) r10.0<1>:f r6.0<0;1,0>:f r2.0<8;8,1>:f + pln (8|M0) r11.0<1>:f r6.0<0;1,0>:f r4.0<8;8,1>:f + pln (8|M0) r12.0<1>:f r6.4<0;1,0>:f r2.0<8;8,1>:f + pln (8|M0) 13.0<1>:f r6.4<0;1,0>:f r4.0<8;8,1>:f + send (16|M0) r112:f r10:ub 0x10000002 0x08840001 // SAMPLER wr:4, rd:8, fc: 0x40001 + send (16|M0) null:f r112:ub 0x10000025 0x10031000 {EOT} // DP_RC wr:8, rd:0, Render Target Write msc:16, to #0 + diff --git a/lib/i915/shaders/ps/neg1_gen8.asm b/lib/i915/shaders/ps/neg1_gen8.asm new file mode 100644 index 00000000..582375b5 --- /dev/null +++ b/lib/i915/shaders/ps/neg1_gen8.asm @@ -0,0 +1,9 @@ +mov(8) r112:ud 0x3f800000:ud +mov(8) r113:ud 0x3f800000:ud +mov(8) r114:ud 0x3f800000:ud +mov(8) r115:ud 0x3f800000:ud +mov(8) r116:ud 0x3f800000:ud +mov(8) r117:ud 0x3f800000:ud +mov(8) r118:ud 0x3f800000:ud +mov(8) r119:ud 0x3f800000:ud +send(16) null r112 0x25 0x10031000 { EOT } diff --git a/lib/i915/shaders/ps/neg1_test.g7a b/lib/i915/shaders/ps/neg1_test.g7a new file mode 100644 index 00000000..744a7690 --- /dev/null +++ b/lib/i915/shaders/ps/neg1_test.g7a @@ -0,0 +1,9 @@ +mov(8) g112:UD 0x3f800000:UD { align1 }; +mov(8) g113:UD 0x3f800000:UD { align1 }; +mov(8) g114:UD 0x3f800000:UD { align1 }; +mov(8) g115:UD 0x3f800000:UD { align1 }; +mov(8) g116:UD 0x3f800000:UD { align1 }; +mov(8) g117:UD 0x3f800000:UD { align1 }; +mov(8) g118:UD 0x3f800000:UD { align1 }; +mov(8) g119:UD 0x3f800000:UD { align1 }; +send(16) null g112 0x25 0x10031000 { align1, EOT }; diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c index 1319b9e4..beb7a9b3 100644 --- a/lib/rendercopy_gen8.c +++ b/lib/rendercopy_gen8.c @@ -48,7 +48,7 @@ struct { uint32_t sf_clip_state; } viewport; -/* see shaders/ps/blit.g7a */ +/* see lib/i915/shaders/ps/blit.g7a */ static const uint32_t ps_kernel[][4] = { #if 1 { 0x0080005a, 0x2f403ae8, 0x3a0000c0, 0x008d0040 }, diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index 0ed89776..f324fbd7 100644 --- a/lib/rendercopy_gen9.c +++ b/lib/rendercopy_gen9.c @@ -49,7 +49,7 @@ struct { uint32_t sf_clip_state; } viewport; -/* see shaders/ps/blit.g7a */ +/* see lib/i915/shaders/ps/blit.g7a */ static const uint32_t ps_kernel[][4] = { #if 1 { 0x0080005a, 0x2f403ae8, 0x3a0000c0, 0x008d0040 }, diff --git a/shaders/README b/shaders/README deleted file mode 100644 index 06b9883c..00000000 --- a/shaders/README +++ /dev/null @@ -1,25 +0,0 @@ -This directory is for shaders used in media_fill, gpgpu_fill, rendercopy -and media_spin libraries. - -Till Gen8 shaders were generated using intel-gen4asm script (implementation in -assembler/ directory). From Gen8 it is possible to use Intel Graphics Assembler -to generate binary from asm instructions. -https://github.com/intel/intel-graphics-compiler - 1. Clone IGC project - 2. Go to igc/visa/iga - 3. Build iga - cmake . && make - -For maintaining compatibility with our tests there is a bin to hex converter -written in python: - $>converter.py input_file > output_file -e.g.$>python converter.py gen9_iga_output > gen9_hex_array - -Commands used to generate the shader on gen7 -$> m4 gpgpu_fill.gxa > gpgpu_fill.gxm -$> intel-gen4asm -g 7 -o gpgpu_fill.gxm - -Commands used to generate the shader on gen8 -$> m4 media_fill.gxa > media_fill.gxm -$> intel-gen4asm -g 8 -o media_fill.gxm - diff --git a/shaders/converter.py b/shaders/converter.py deleted file mode 100644 index 25a79a94..00000000 --- a/shaders/converter.py +++ /dev/null @@ -1,26 +0,0 @@ -#!/usr/bin/env python3 -import struct -import sys -import argparse - -parser=argparse.ArgumentParser( - description='''Script for converting shaders from binary to hex ''' ) -parser = argparse.ArgumentParser(prog='converter.py', usage='%(prog)s binary_file') -parser.add_argument('binary', nargs=1, help='binary_file') -args=parser.parse_args() - -print "static const uint32_t kernel[][4] = {" -with open(sys.argv[1], 'r') as f: - fmt = 'UD') -define(`ORIG_X', `g2.0<1>UD') -define(`ORIG_Y', `g2.4<1>UD') -define(`COLOR', `g1.0') -define(`COLORUB', `COLOR<0,1,0>UB') -define(`COLORUD', `COLOR<0,1,0>UD') -define(`X', `g0.4<0,1,0>UD') -define(`Y', `g0.24<0,1,0>UD') - -mov(4) COLOR<1>UB COLORUB {align1}; - -/* WRITE */ -/* count thread group ID for X/Y offset */ -mul(1) ORIG_X X 0x10UD {align1}; -mov(1) ORIG_Y Y {align1}; -mov(8) g4.0<1>UD g0.0<8,8,1>UD {align1}; -mov(2) g4.0<1>UD ORIG {align1}; -/* Normal mode: for block height 1 row and block width 16 bytes */ -mov(1) g4.8<1>UD 0x0000000fUD {align1}; - -mov(16) g5.0<1>UD COLORUD {align1 compr}; - -/* - * write(0, 0, 10, 12) - * 10: media_block_write - * 12: data cache data port 1 - */ -send(16) 4 acc0<1>UW null write(0, 0, 10, 12) mlen 3 rlen 0 {align1}; - -/* EOT */ -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; diff --git a/shaders/gpgpu/gpgpu_fill_gen8.asm b/shaders/gpgpu/gpgpu_fill_gen8.asm deleted file mode 100644 index 448e0256..00000000 --- a/shaders/gpgpu/gpgpu_fill_gen8.asm +++ /dev/null @@ -1,10 +0,0 @@ - mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub - mul (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud 0x10:ud - mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud - mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud - mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud - mov (1|M0) r4.2<1>:ud 0xF:ud - mov (16|M0) (eq)f0.0 r5.0<1>:ud r1.0<0;1,0>:ud - send (16|M0) acc0.0:uw r4:d 0xC 0x060A8000 // DP_DC1 wr:3h, rd:0, fc: 0x28000 - mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud - send (16|M0) null:uw r112:d 0x27 0x02000010 {EOT} // SPAWNER wr:1, rd:0, fc: 0x10 diff --git a/shaders/gpgpu/gpgpu_fill_gen9.asm b/shaders/gpgpu/gpgpu_fill_gen9.asm deleted file mode 100644 index 6f948935..00000000 --- a/shaders/gpgpu/gpgpu_fill_gen9.asm +++ /dev/null @@ -1,10 +0,0 @@ - mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub - mul (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud 0x10:ud - mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud - mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud - mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud - mov (1|M0) r4.2<1>:ud 0xF:ud - mov (16|M0) r5.0<1>:ud r1.0<0;1,0>:ud - send (16|M0) acc0.0:uw r4:d 0xC 0x060A8000 // DP_DC1 wr:3h, rd:0, fc: 0x28000 - mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud - send (16|M0) null:uw r112:d 0x27 0x02000010 {EOT} // SPAWNER wr:1, rd:0, fc: 0x10 diff --git a/shaders/media/media_fill.gxa b/shaders/media/media_fill.gxa deleted file mode 100644 index 75788906..00000000 --- a/shaders/media/media_fill.gxa +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Registers - * g0 -- header - * g1 -- constant - * g2 -- inline data - * g3 -- reserved - * g4-g12 payload for write message - */ -define(`ORIG', `g2.0<2,2,1>UD') -define(`COLOR', `g1.0') -define(`COLORUB', `COLOR<0,1,0>UB') -define(`COLORUD', `COLOR<0,1,0>UD') - -mov(4) COLOR<1>UB COLORUB {align1}; - -/* WRITE */ -mov(8) g4.0<1>UD g0.0<8,8,1>UD {align1}; -mov(2) g4.0<1>UD ORIG {align1}; -mov(1) g4.8<1>UD 0x000f000fUD {align1}; - -mov(16) g5.0<1>UD COLORUD {align1 compr}; -mov(16) g7.0<1>UD COLORUD {align1 compr}; -mov(16) g9.0<1>UD COLORUD {align1 compr}; -mov(16) g11.0<1>UD COLORUD {align1 compr}; - -/* - * comment out the following instruction on Gen7 - * write(0, 0, 10, 12) - * 10: media_block_write - * 12: data cache data port 1 - */ -send(16) 4 acc0<1>UW null write(0, 0, 10, 12) mlen 9 rlen 0 {align1}; - -/* - * uncomment the following instruction on Gen7 - * write(0, 0, 10, 0) - * 10: media_block_write - * 0: reander cache data port - */ -/* send(16) 4 acc0<1>UW null write(0, 0, 10, 0) mlen 9 rlen 0 {align1}; */ - -/* EOT */ -mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; -send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; diff --git a/shaders/media/media_fill_gen8.asm b/shaders/media/media_fill_gen8.asm deleted file mode 100644 index 4b6eb84b..00000000 --- a/shaders/media/media_fill_gen8.asm +++ /dev/null @@ -1,11 +0,0 @@ - mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub - mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud - mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud - mov (1|M0) r4.2<1>:ud 0xF000F:ud - mov (16|M0) r5.0<1>:ud r1.0<0;1,0>:ud - mov (16|M0) r7.0<1>:ud r1.0<0;1,0>:ud - mov (16|M0) r9.0<1>:ud r1.0<0;1,0>:ud - mov (16|M0) r11.0<1>:ud r1.0<0;1,0>:ud - send (16|M0) acc0.0:uw r4:d 0x1000000C 0x120A8000 // DP_DC1 wr:9h, rd:0, fc: 0x28000 - mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud - send (16|M0) null:uw r112:d 0x10000027 0x02000010 {EOT} // SPAWNER wr:1, rd:0, fc: 0x10 diff --git a/shaders/ps/blit.g7a b/shaders/ps/blit.g7a deleted file mode 100644 index deeedcc5..00000000 --- a/shaders/ps/blit.g7a +++ /dev/null @@ -1,66 +0,0 @@ -/* Assemble with ".../intel-gen4asm/src/intel-gen4asm -g 7" */ - - -/* Move pixels into g10-g13. The pixel shaader does not load what you want. It - * loads the input data for a plane function to calculate what you want. The - * following is boiler plate code to move our normalized texture coordinates - * (u,v) into g10-g13. It does this 4 subspans (16 pixels) at a time. - * - * This should do the same thing, but it doesn't work for some reason. - * pln(16) g10 g6<0,1,0>F g2<8,8,1>F { align1 }; - * pln(16) g12 g6.16<1>F g2<8,8,1>F { align1 }; - */ -/* U */ -pln (8) g10<1>F g6.0<0,1,0>F g2.0<8,8,1>F { align1 }; /* pixel 0-7 */ -pln (8) g11<1>F g6.0<0,1,0>F g4.0<8,8,1>F { align1 }; /* pixel 8-15 */ -/* V */ -pln (8) g12<1>F g6.16<0,1,0> g2.0<8,8,1>F { align1 }; /* pixel 0-7 */ -pln (8) g13<1>F g6.16<0,1,0> g4.0<8,8,1>F { align1 }; /* pixel 8-15 */ - - -/* Next the we want the sampler to fetch the src texture (ie. src buffer). This - * is done with a pretty simple send message. The output goes to g112, which is - * exactly what we're supposed to use in our final send message. - * In intel-gen4asm, we should end up parsed by the following rule: - * predicate SEND execsize dst sendleadreg sndopr directsrcoperand instoptions - * - * Send message descriptor: - * 28:25 = message len = 4 // our 4 registers have 16 pixels - * 24:20 = response len = 8 // Each pixel is RGBA32, so we need 8 registers - * 19:19 = header present = 0 - * 18:17 = SIMD16 = 2 - * 16:12 = TYPE = 0 (regular sample) - * 11:08 = Sampler index = ignored/0 - * 7:0 = binding table index = src = 1 - * 0x8840001 - * - * Send message extra descriptor - * 5:5 = End of Thread = 0 - * 3:0 = Target Function ID = SFID_SAMPLER (2) - * 0x2 - */ - -send(16) g112 g10 0x2 0x8840001 { align1 }; - -/* g112-g119 now contains the sample source input, and all we must do is write - * it out to the destination render target. This is done with the send message - * as well. The only extra bits are to terminate the pixel shader. - * - * Send message descriptor: - * 28:25 = message len = 8 // 16 pixels RGBA32 - * 24:20 = response len = 0 - * 19:19 = header present = 0 - * 17:14 = message type = Render Target Write (12) - * 12:12 = Last Render Target Select = 1 - * 10:08 = Message Type = SIMD16 (0) - * 07:00 = Binding Table Index = dest = 0 - * 0x10031000 - * - * Send message extra descriptor - * 5:5 = End of Thread = 1 - * 3:0 = Target Function ID = SFID_DP_RC (5) - * 0x25 - */ -send(16) null g112 0x25 0x10031000 { align1, EOT }; - -/* vim: set ft=c ts=4 sw=2 tw=80 et: */ diff --git a/shaders/ps/blit_gen8.asm b/shaders/ps/blit_gen8.asm deleted file mode 100644 index c35b70a1..00000000 --- a/shaders/ps/blit_gen8.asm +++ /dev/null @@ -1,7 +0,0 @@ - pln (8|M0) r10.0<1>:f r6.0<0;1,0>:f r2.0<8;8,1>:f - pln (8|M0) r11.0<1>:f r6.0<0;1,0>:f r4.0<8;8,1>:f - pln (8|M0) r12.0<1>:f r6.4<0;1,0>:f r2.0<8;8,1>:f - pln (8|M0) 13.0<1>:f r6.4<0;1,0>:f r4.0<8;8,1>:f - send (16|M0) r112:f r10:ub 0x10000002 0x08840001 // SAMPLER wr:4, rd:8, fc: 0x40001 - send (16|M0) null:f r112:ub 0x10000025 0x10031000 {EOT} // DP_RC wr:8, rd:0, Render Target Write msc:16, to #0 - diff --git a/shaders/ps/neg1_gen8.asm b/shaders/ps/neg1_gen8.asm deleted file mode 100644 index 582375b5..00000000 --- a/shaders/ps/neg1_gen8.asm +++ /dev/null @@ -1,9 +0,0 @@ -mov(8) r112:ud 0x3f800000:ud -mov(8) r113:ud 0x3f800000:ud -mov(8) r114:ud 0x3f800000:ud -mov(8) r115:ud 0x3f800000:ud -mov(8) r116:ud 0x3f800000:ud -mov(8) r117:ud 0x3f800000:ud -mov(8) r118:ud 0x3f800000:ud -mov(8) r119:ud 0x3f800000:ud -send(16) null r112 0x25 0x10031000 { EOT } diff --git a/shaders/ps/neg1_test.g7a b/shaders/ps/neg1_test.g7a deleted file mode 100644 index 744a7690..00000000 --- a/shaders/ps/neg1_test.g7a +++ /dev/null @@ -1,9 +0,0 @@ -mov(8) g112:UD 0x3f800000:UD { align1 }; -mov(8) g113:UD 0x3f800000:UD { align1 }; -mov(8) g114:UD 0x3f800000:UD { align1 }; -mov(8) g115:UD 0x3f800000:UD { align1 }; -mov(8) g116:UD 0x3f800000:UD { align1 }; -mov(8) g117:UD 0x3f800000:UD { align1 }; -mov(8) g118:UD 0x3f800000:UD { align1 }; -mov(8) g119:UD 0x3f800000:UD { align1 }; -send(16) null g112 0x25 0x10031000 { align1, EOT }; -- cgit v1.2.3