1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
|
/*
* Copyright © 2011,2013 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Daniel Vetter <daniel.vetter@ffwll.ch>
*
*/
#define _GNU_SOURCE
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <signal.h>
#include <sys/wait.h>
#include "drm.h"
#include "i915_drm.h"
#include "drmtest.h"
#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
#include "intel_gpu_tools.h"
/*
* Testcase: Kernel relocations vs. gpu races
*
*/
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
uint32_t blob[2048*2048];
#define NUM_TARGET_BOS 16
drm_intel_bo *pc_target_bo[NUM_TARGET_BOS];
drm_intel_bo *dummy_bo;
drm_intel_bo *special_bo;
uint32_t devid;
int special_reloc_ofs;
int special_batch_len;
#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
#define PIPE_CONTROL_WRITE_IMMEDIATE (1<<14)
#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
#define PIPE_CONTROL_DEPTH_STALL (1<<13)
#define PIPE_CONTROL_WC_FLUSH (1<<12)
#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
#define PIPE_CONTROL_CS_STALL (1<<20)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
static void create_special_bo(void)
{
uint32_t data[1024];
int len = 0;
int small_pitch = 64;
#define BATCH(dw) data[len++] = (dw);
memset(data, 0, 4096);
special_bo = drm_intel_bo_alloc(bufmgr, "special batch", 4096, 4096);
BATCH(XY_COLOR_BLT_CMD | COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
BATCH((3 << 24) | (0xf0 << 16) | small_pitch);
BATCH(0);
BATCH(1 << 16 | 1);
special_reloc_ofs = 4*len;
BATCH(0);
BATCH(0xdeadbeef);
#define CMD_POLY_STIPPLE_OFFSET 0x7906
/* batchbuffer end */
if (IS_GEN5(batch->devid)) {
BATCH(CMD_POLY_STIPPLE_OFFSET << 16);
BATCH(0);
}
igt_assert(len % 2 == 0);
BATCH(MI_NOOP);
BATCH(MI_BATCH_BUFFER_END);
drm_intel_bo_subdata(special_bo, 0, 4096, data);
special_batch_len = len*4;
}
static void emit_dummy_load(int pitch)
{
int i;
uint32_t tile_flags = 0;
if (IS_965(devid)) {
pitch /= 4;
tile_flags = XY_SRC_COPY_BLT_SRC_TILED |
XY_SRC_COPY_BLT_DST_TILED;
}
for (i = 0; i < 10; i++) {
BEGIN_BATCH(8);
OUT_BATCH(XY_SRC_COPY_BLT_CMD |
XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB |
tile_flags);
OUT_BATCH((3 << 24) | /* 32 bits */
(0xcc << 16) | /* copy ROP */
pitch);
OUT_BATCH(0 << 16 | 1024);
OUT_BATCH((2048) << 16 | (2048));
OUT_RELOC_FENCED(dummy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(0 << 16 | 0);
OUT_BATCH(pitch);
OUT_RELOC_FENCED(dummy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
ADVANCE_BATCH();
if (IS_GEN6(devid) || IS_GEN7(devid)) {
BEGIN_BATCH(3);
OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
}
}
intel_batchbuffer_flush(batch);
}
static void faulting_reloc_and_emit(int fd, drm_intel_bo *target_bo)
{
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 exec[2];
struct drm_i915_gem_relocation_entry reloc[1];
uint32_t handle_relocs;
void *gtt_relocs;
int ring;
if (intel_gen(devid) >= 6)
ring = I915_EXEC_BLT;
else
ring = 0;
exec[0].handle = target_bo->handle;
exec[0].relocation_count = 0;
exec[0].relocs_ptr = 0;
exec[0].alignment = 0;
exec[0].offset = 0;
exec[0].flags = 0;
exec[0].rsvd1 = 0;
exec[0].rsvd2 = 0;
reloc[0].offset = special_reloc_ofs;
reloc[0].delta = 0;
reloc[0].target_handle = target_bo->handle;
reloc[0].read_domains = I915_GEM_DOMAIN_RENDER;
reloc[0].write_domain = I915_GEM_DOMAIN_RENDER;
reloc[0].presumed_offset = 0;
handle_relocs = gem_create(fd, 4096);
gem_write(fd, handle_relocs, 0, reloc, sizeof(reloc));
gtt_relocs = gem_mmap(fd, handle_relocs, 4096,
PROT_READ | PROT_WRITE);
igt_assert(gtt_relocs);
exec[1].handle = special_bo->handle;
exec[1].relocation_count = 1;
/* A newly mmap gtt bo will fault on first access. */
exec[1].relocs_ptr = (uintptr_t)gtt_relocs;
exec[1].alignment = 0;
exec[1].offset = 0;
exec[1].flags = 0;
exec[1].rsvd1 = 0;
exec[1].rsvd2 = 0;
execbuf.buffers_ptr = (uintptr_t)exec;
execbuf.buffer_count = 2;
execbuf.batch_start_offset = 0;
execbuf.batch_len = special_batch_len;
execbuf.cliprects_ptr = 0;
execbuf.num_cliprects = 0;
execbuf.DR1 = 0;
execbuf.DR4 = 0;
execbuf.flags = ring;
i915_execbuffer2_set_context_id(execbuf, 0);
execbuf.rsvd2 = 0;
gem_execbuf(fd, &execbuf);
gem_close(fd, handle_relocs);
}
static void reloc_and_emit(int fd, drm_intel_bo *target_bo)
{
int ring;
if (intel_gen(devid) >= 6)
ring = I915_EXEC_BLT;
else
ring = 0;
drm_intel_bo_emit_reloc(special_bo, special_reloc_ofs,
target_bo,
0,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
drm_intel_bo_mrb_exec(special_bo, special_batch_len, NULL,
0, 0, ring);
}
static void do_test(int fd, bool faulting_reloc)
{
uint32_t tiling_mode = I915_TILING_X;
unsigned long pitch, act_size;
uint32_t test;
int i;
if (faulting_reloc)
igt_disable_prefault();
act_size = 2048;
dummy_bo = drm_intel_bo_alloc_tiled(bufmgr, "tiled dummy_bo", act_size, act_size,
4, &tiling_mode, &pitch, 0);
drm_intel_bo_subdata(dummy_bo, 0, act_size*act_size*4, blob);
create_special_bo();
for (i = 0; i < NUM_TARGET_BOS; i++) {
pc_target_bo[i] = drm_intel_bo_alloc(bufmgr, "special batch", 4096, 4096);
emit_dummy_load(pitch);
igt_assert(pc_target_bo[i]->offset == 0);
if (faulting_reloc)
faulting_reloc_and_emit(fd, pc_target_bo[i]);
else
reloc_and_emit(fd, pc_target_bo[i]);
}
/* Only check at the end to avoid unnecessary synchronous behaviour. */
for (i = 0; i < NUM_TARGET_BOS; i++) {
drm_intel_bo_get_subdata(pc_target_bo[i], 0, 4, &test);
igt_assert_f(test == 0xdeadbeef,
"mismatch in buffer %i: 0x%08x instead of 0xdeadbeef\n", i, test);
drm_intel_bo_unreference(pc_target_bo[i]);
}
drm_intel_gem_bo_map_gtt(dummy_bo);
drm_intel_gem_bo_unmap_gtt(dummy_bo);
drm_intel_bo_unreference(special_bo);
drm_intel_bo_unreference(dummy_bo);
if (faulting_reloc)
igt_enable_prefault();
}
#define INTERRUPT (1 << 0)
#define FAULTING (1 << 1)
#define THRASH (1 << 2)
#define THRASH_INACTIVE (1 << 3)
#define ALL_FLAGS (INTERRUPT | FAULTING | THRASH | THRASH_INACTIVE)
static void do_forked_test(int fd, unsigned flags)
{
int num_threads = sysconf(_SC_NPROCESSORS_ONLN);
struct igt_helper_process thrasher = {};
if (flags & (THRASH | THRASH_INACTIVE)) {
char fname[FILENAME_MAX];
int drop_caches_fd;
const char *data = THRASH_INACTIVE ? "0xf" : "0x7";
snprintf(fname, FILENAME_MAX, "%s/%i/%s",
"/sys/kernel/debug/dri", drm_get_card(),
"i915_gem_drop_caches");
drop_caches_fd = open(fname, O_WRONLY);
igt_require(drop_caches_fd >= 0);
igt_fork_helper(&thrasher) {
while (1) {
usleep(1000);
igt_assert(write(drop_caches_fd, data, strlen(data) + 1) == strlen(data) + 1);
}
}
}
igt_fork(i, num_threads * 4) {
/* re-create process local data */
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
batch = intel_batchbuffer_alloc(bufmgr, devid);
if (flags & INTERRUPT)
igt_fork_signal_helper();
do_test(fd, flags & FAULTING);
if (flags & INTERRUPT)
igt_stop_signal_helper();
}
igt_waitchildren();
if (flags & (THRASH | THRASH_INACTIVE))
igt_stop_helper(&thrasher);
}
int fd;
#define MAX_BLT_SIZE 128
int main(int argc, char **argv)
{
igt_subtest_init(argc, argv);
igt_skip_on_simulation();
memset(blob, 'A', sizeof(blob));
igt_fixture {
fd = drm_open_any();
bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
/* disable reuse, otherwise the test fails */
//drm_intel_bufmgr_gem_enable_reuse(bufmgr);
devid = intel_get_drm_devid(fd);
batch = intel_batchbuffer_alloc(bufmgr, devid);
}
igt_subtest("normal")
do_test(fd, false);
igt_subtest("faulting-reloc")
do_test(fd, true);
igt_fork_signal_helper();
igt_subtest("interruptible")
do_test(fd, false);
igt_subtest("faulting-reloc-interruptible")
do_test(fd, true);
igt_stop_signal_helper();
for (unsigned flags = 0; flags <= ALL_FLAGS; flags++) {
if ((flags & THRASH) && (flags & THRASH_INACTIVE))
continue;
igt_subtest_f("forked%s%s%s%s",
flags & INTERRUPT ? "-interruptible" : "",
flags & FAULTING ? "-faulting-reloc" : "",
flags & THRASH ? "-thrashing" : "",
flags & THRASH_INACTIVE ? "-thrash-inactive" : "")
do_forked_test(fd, flags);
}
igt_fixture {
intel_batchbuffer_free(batch);
drm_intel_bufmgr_destroy(bufmgr);
close(fd);
}
igt_exit();
}
|