<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/arch/arm/mach-tegra/tegra.c, branch vm-bind</title>
<subtitle>Linux Kernel</subtitle>
<id>https://git.etezian.org/cgit.cgi/linux.git/atom?h=vm-bind</id>
<link rel='self' href='https://git.etezian.org/cgit.cgi/linux.git/atom?h=vm-bind'/>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/'/>
<updated>2021-08-11T09:51:39+00:00</updated>
<entry>
<title>soc/tegra: pmc: Prevent racing with cpuilde driver</title>
<updated>2021-08-11T09:51:39+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-07-18T21:27:05+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=9c93ccfc86f2cdeab8a34408759abad594e439b9'/>
<id>urn:sha1:9c93ccfc86f2cdeab8a34408759abad594e439b9</id>
<content type='text'>
Both PMC and cpuidle drivers are probed at the same init level and
cpuidle depends on the PMC suspend mode. Add new default suspend mode
that indicates whether PMC driver has been probed and reset the mode in
a case of deferred probe of the PMC driver.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Create tegra20-cpufreq platform device on Tegra30</title>
<updated>2020-05-06T17:01:17+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-03-19T19:02:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=b9bf73aed99ed3170b37fbbf98557c70a6f19e50'/>
<id>urn:sha1:b9bf73aed99ed3170b37fbbf98557c70a6f19e50</id>
<content type='text'>
The tegra20-cpufreq now instantiates cpufreq-dt and Tegra30 is fully
supported by that driver.

Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt;
Tested-by: Marcel Ziswiler &lt;marcel@ziswiler.com&gt;
Tested-by: Jasper Korten &lt;jja2000@gmail.com&gt;
Tested-by: David Heidelberg &lt;david@ixit.cz&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Correct PL310 Auxiliary Control Register initialization</title>
<updated>2020-05-06T16:43:24+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-03-13T09:01:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=35509737c8f958944e059d501255a0bf18361ba0'/>
<id>urn:sha1:35509737c8f958944e059d501255a0bf18361ba0</id>
<content type='text'>
The PL310 Auxiliary Control Register shouldn't have the "Full line of
zero" optimization bit being set before L2 cache is enabled. The L2X0
driver takes care of enabling the optimization by itself.

This patch fixes a noisy error message on Tegra20 and Tegra30 telling
that cache optimization is erroneously enabled without enabling it for
the CPU:

	L2C-310: enabling full line of zeros but not enabled in Cortex-A9

Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>cpuidle: tegra: Squash Tegra114 driver into the common driver</title>
<updated>2020-03-13T10:32:01+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-02-24T22:40:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=14e086baca509ef244715ad8b6c3f7bf80621e0b'/>
<id>urn:sha1:14e086baca509ef244715ad8b6c3f7bf80621e0b</id>
<content type='text'>
Tegra20/30/114/124 SoCs have common idling states, thus there is no much
point in having separate drivers for a similar hardware. This patch moves
Tegra114/124 arch/ drivers into the common driver without any functional
changes. The CC6 state is kept disabled on Tegra114/124 because the core
Tegra PM code needs some more work in order to support that state.

Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Expose PM functions required for new cpuidle driver</title>
<updated>2020-03-13T10:22:41+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-02-24T22:40:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=7741868f3837fb7eca7df8f4046f9faa3007831b'/>
<id>urn:sha1:7741868f3837fb7eca7df8f4046f9faa3007831b</id>
<content type='text'>
The upcoming unified CPUIDLE driver will be added to the drivers/cpuidle/
directory and it will require all these exposed Tegra PM-core functions.

Acked-by: Peter De Schrijver &lt;pdeschrijver@nvidia.com&gt;
Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt;
Tested-by: Jasper Korten &lt;jja2000@gmail.com&gt;
Tested-by: David Heidelberg &lt;david@ixit.cz&gt;
Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt;
Acked-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
[treding@nvidia.com: fixup missing include rename]
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282</title>
<updated>2019-06-05T15:36:37+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-29T14:17:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=9c92ab61914157664a2fbdf926df0eb937838e45'/>
<id>urn:sha1:9c92ab61914157664a2fbdf926df0eb937838e45</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this software is licensed under the terms of the gnu general public
  license version 2 as published by the free software foundation and
  may be copied distributed and modified under those terms this
  program is distributed in the hope that it will be useful but
  without any warranty without even the implied warranty of
  merchantability or fitness for a particular purpose see the gnu
  general public license for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 285 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Alexios Zavras &lt;alexios.zavras@intel.com&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>firmware: Move Trusted Foundations support</title>
<updated>2019-04-17T14:43:03+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-04-10T08:47:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=4cb5d9eca143f7fbf8cc457be19a91914f978a00'/>
<id>urn:sha1:4cb5d9eca143f7fbf8cc457be19a91914f978a00</id>
<content type='text'>
Move the Trusted Foundations support out of arch/arm/firmware and into
drivers/firmware where most other firmware support implementations are
located.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Set up L2 cache using Trusted Foundations firmware</title>
<updated>2019-04-09T14:36:23+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2019-03-17T22:52:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=6ad27b8350401a3c79899b431097afc361b46374'/>
<id>urn:sha1:6ad27b8350401a3c79899b431097afc361b46374</id>
<content type='text'>
On Tegra30 L2 cache should be initialized using firmware call if CPU
is running in insecure mode. Set up the required outer-cache write_sec()
callback early during boot using the firmware API, it is always a NO-OP
on T114+ and is NO-OP on T20/30 if Trusted Foundations firmware node
isn't present in device-tree.

Tested-by: Robert Yang &lt;decatf@gmail.com&gt;
Tested-by: Michał Mirosław &lt;mirq-linux@rere.qmqm.pl&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>ARM: tegra: Create platform device for tegra20-cpufreq driver</title>
<updated>2018-05-18T09:15:42+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2018-05-17T18:00:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=15164e0072b579f77c9025f3da3ed931869b89cd'/>
<id>urn:sha1:15164e0072b579f77c9025f3da3ed931869b89cd</id>
<content type='text'>
Tegra20-cpufreq driver require a platform device in order to be loaded,
instantiate a simple platform device for the driver during of the machines
late initialization.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>soc/tegra: Register SoC device</title>
<updated>2017-08-17T14:43:13+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2017-08-17T14:42:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=27a0342ac162bf2ba30c288cfb7b72eabed38d8b'/>
<id>urn:sha1:27a0342ac162bf2ba30c288cfb7b72eabed38d8b</id>
<content type='text'>
Move this code from arch/arm/mach-tegra and make it common among 32-bit
and 64-bit Tegra SoCs. This is slightly complicated by the fact that on
32-bit Tegra, the SoC device is used as the parent for all devices that
are instantiated from device tree.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
