<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/clk/qcom/Kconfig, branch vm-bind</title>
<subtitle>Linux Kernel</subtitle>
<id>https://git.etezian.org/cgit.cgi/linux.git/atom?h=vm-bind</id>
<link rel='self' href='https://git.etezian.org/cgit.cgi/linux.git/atom?h=vm-bind'/>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/'/>
<updated>2022-05-19T21:41:32+00:00</updated>
<entry>
<title>clk: qcom: add sc8280xp GCC driver</title>
<updated>2022-05-19T21:41:32+00:00</updated>
<author>
<name>Bjorn Andersson</name>
<email>bjorn.andersson@linaro.org</email>
</author>
<published>2022-05-05T02:54:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=d65d005f9a6cffb1efb205f3af4d0de8f1e3b352'/>
<id>urn:sha1:d65d005f9a6cffb1efb205f3af4d0de8f1e3b352</id>
<content type='text'>
Add support for the Global Clock Controller found in the Qualcomm
SC8280XP platform.

Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Reviewed-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Reviewed-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Link: https://lore.kernel.org/r/20220505025457.1693716-3-bjorn.andersson@linaro.org
</content>
</entry>
<entry>
<title>clk: qcom: lpass: Add support for LPASS clock controller for SC7280</title>
<updated>2022-04-13T02:17:42+00:00</updated>
<author>
<name>Taniya Das</name>
<email>tdas@codeaurora.org</email>
</author>
<published>2022-02-23T17:22:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=a9dd26639d0567043bb3d8761380d505f2318e44'/>
<id>urn:sha1:a9dd26639d0567043bb3d8761380d505f2318e44</id>
<content type='text'>
The Low Power Audio subsystem core and audio clocks are required for
Audio client to be able to request for the clocks and power domains.

Signed-off-by: Taniya Das &lt;tdas@codeaurora.org&gt;
Reviewed-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20220223172248.18877-2-tdas@codeaurora.org
</content>
</entry>
<entry>
<title>clk: qcom: Add display clock controller driver for SM6125</title>
<updated>2022-03-09T14:53:30+00:00</updated>
<author>
<name>Martin Botka</name>
<email>martin.botka@somainline.org</email>
</author>
<published>2022-03-03T13:18:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=6e87c8f074075e10c5352d3256879b4e6dd6cb81'/>
<id>urn:sha1:6e87c8f074075e10c5352d3256879b4e6dd6cb81</id>
<content type='text'>
Add support for the display clock controller found on SM6125
based devices. This allows display drivers to probe and
control their clocks.

Signed-off-by: Martin Botka &lt;martin.botka@somainline.org&gt;
Signed-off-by: Marijn Suijten &lt;marijn.suijten@somainline.org&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@collabora.com&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20220303131812.302302-4-marijn.suijten@somainline.org
</content>
</entry>
<entry>
<title>clk: qcom: Fix sorting of SDX_GCC_65 in Makefile and Kconfig</title>
<updated>2022-03-09T14:53:29+00:00</updated>
<author>
<name>Marijn Suijten</name>
<email>marijn.suijten@somainline.org</email>
</author>
<published>2022-03-03T13:18:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=620f512528389929d9af795f82c63e52a589b53c'/>
<id>urn:sha1:620f512528389929d9af795f82c63e52a589b53c</id>
<content type='text'>
In order to keep at least the list of `CONFIG_SM_` drivers sorted
alphabetically, SDX_GCC_65 should have been moved one line up.  This in
turn makes it easier and cleaner to add the followup SM_DISPCC_6125
driver in the right place, right before SM_DISPCC_8250.

Fixes: d79afa201328 ("clk: qcom: Add SDX65 GCC support")
Signed-off-by: Marijn Suijten &lt;marijn.suijten@somainline.org&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20220303131812.302302-2-marijn.suijten@somainline.org
</content>
</entry>
<entry>
<title>clk: qcom: Add SDX65 APCS clock controller support</title>
<updated>2022-03-08T22:17:40+00:00</updated>
<author>
<name>Rohit Agarwal</name>
<email>quic_rohiagar@quicinc.com</email>
</author>
<published>2022-02-22T04:56:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=2081df368ef325bd7f659e395620090ab2d8d1c0'/>
<id>urn:sha1:2081df368ef325bd7f659e395620090ab2d8d1c0</id>
<content type='text'>
Update APCS Kconfig to reflect support for SDX65
APCS clock controller.

Signed-off-by: Rohit Agarwal &lt;quic_rohiagar@quicinc.com&gt;
Reviewed-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Reviewed-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/1645505785-2271-6-git-send-email-quic_rohiagar@quicinc.com
</content>
</entry>
<entry>
<title>clk: qcom: Add A7 PLL support for SDX65</title>
<updated>2022-03-08T22:17:40+00:00</updated>
<author>
<name>Rohit Agarwal</name>
<email>quic_rohiagar@quicinc.com</email>
</author>
<published>2022-02-22T04:56:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=af44e3276bf8f79bed480764c6a6296be73e073f'/>
<id>urn:sha1:af44e3276bf8f79bed480764c6a6296be73e073f</id>
<content type='text'>
Update A7 PLL Kconfig to reflect support for SDX65.

Signed-off-by: Rohit Agarwal &lt;quic_rohiagar@quicinc.com&gt;
Reviewed-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Reviewed-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/1645505785-2271-3-git-send-email-quic_rohiagar@quicinc.com
</content>
</entry>
<entry>
<title>clk: qcom: Add GPU clock controller driver for SM6350</title>
<updated>2022-03-08T22:16:47+00:00</updated>
<author>
<name>Konrad Dybcio</name>
<email>konrad.dybcio@somainline.org</email>
</author>
<published>2022-02-22T01:15:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=013804a727a0482bc6661e15dfababde5f856550'/>
<id>urn:sha1:013804a727a0482bc6661e15dfababde5f856550</id>
<content type='text'>
Add support for the GPU clock controller found on SM6350.

Signed-off-by: Konrad Dybcio &lt;konrad.dybcio@somainline.org&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20220222011534.3502-4-konrad.dybcio@somainline.org
</content>
</entry>
<entry>
<title>clk: qcom: Add display clock controller driver for SM6350</title>
<updated>2022-03-08T22:16:47+00:00</updated>
<author>
<name>Konrad Dybcio</name>
<email>konrad.dybcio@somainline.org</email>
</author>
<published>2022-02-22T01:15:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=837519775f1d3945e3d4019641f7120d58325059'/>
<id>urn:sha1:837519775f1d3945e3d4019641f7120d58325059</id>
<content type='text'>
Add support for the display clock controller found on SM6350.

Signed-off-by: Konrad Dybcio &lt;konrad.dybcio@somainline.org&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20220222011534.3502-2-konrad.dybcio@somainline.org
</content>
</entry>
<entry>
<title>clk: qcom: Add display clock controller driver for QCM2290</title>
<updated>2022-02-10T23:56:10+00:00</updated>
<author>
<name>Loic Poulain</name>
<email>loic.poulain@linaro.org</email>
</author>
<published>2022-02-09T18:45:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=cc517ea3333f586cb63d76f4e1e8ae3d2469b010'/>
<id>urn:sha1:cc517ea3333f586cb63d76f4e1e8ae3d2469b010</id>
<content type='text'>
Add support for the display clock controller found in QCM2290
based devices. This clock controller feeds the Multimedia Display
SubSystem (MDSS).

It's a porting of dispcc-scuba GPL-2.0 driver from CAF msm-4.19 kernel:
https://source.codeaurora.org/quic/la/kernel/msm-4.19/tree/drivers/clk/qcom/dispcc-scuba.c?h=LE.UM.4.4.1.r3

Global clock name references (parent_names) have been replaced by
parent_data and parent_hws.

Clocks marked enable_safe_config have their clk_rcg2_ops moved to
clk_rcg2_shared_ops.

Signed-off-by: Loic Poulain &lt;loic.poulain@linaro.org&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/1644432308-21099-2-git-send-email-loic.poulain@linaro.org
</content>
</entry>
<entry>
<title>clk: qcom: Add MSM8976/56 Global Clock Controller (GCC) driver</title>
<updated>2021-12-16T19:17:23+00:00</updated>
<author>
<name>AngeloGioacchino Del Regno</name>
<email>angelogioacchino.delregno@somainline.org</email>
</author>
<published>2021-12-08T09:10:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=8f62718bd0f7278f08ca00ea4664f54a6258044f'/>
<id>urn:sha1:8f62718bd0f7278f08ca00ea4664f54a6258044f</id>
<content type='text'>
Add support for the global clock controller found on MSM8956
and MSM8976 SoCs.
Since the multimedia clocks are actually in the GCC on these
SoCs, this will allow drivers to probe and control basically
all the required clocks.

Signed-off-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@somainline.org&gt;
Co-developed-by: Marijn Suijten &lt;marijn.suijten@somainline.org&gt;
Signed-off-by: Marijn Suijten &lt;marijn.suijten@somainline.org&gt;
Co-developed-by: Konrad Dybcio &lt;konrad.dybcio@somainline.org&gt;
Signed-off-by: Konrad Dybcio &lt;konrad.dybcio@somainline.org&gt;
Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20211208091036.132334-3-marijn.suijten@somainline.org
</content>
</entry>
</feed>
