<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/drivers/clk/qcom, branch master</title>
<subtitle>Linux Kernel</subtitle>
<id>https://git.etezian.org/cgit.cgi/linux.git/atom?h=master</id>
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<updated>2016-11-24T00:41:19+00:00</updated>
<entry>
<title>clk: qcom: Put venus core0/1 gdscs to hw control mode</title>
<updated>2016-11-24T00:41:19+00:00</updated>
<author>
<name>Sricharan R</name>
<email>sricharan@codeaurora.org</email>
</author>
<published>2016-11-18T12:28:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=96893e101eb294bced8358fbd48cbac175977aa4'/>
<id>urn:sha1:96893e101eb294bced8358fbd48cbac175977aa4</id>
<content type='text'>
The venus video ip's internal core blocks are under the
control of the firmware and their powerdomains needs to be
'ON' only when used by the firmware. So putting it into
hw controlled mode lets this to happen, otherwise the firmware
hangs checking for this.

Signed-off-by: Sricharan R &lt;sricharan@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: gdsc: Add support for gdscs with HW control</title>
<updated>2016-11-24T00:41:15+00:00</updated>
<author>
<name>Rajendra Nayak</name>
<email>rnayak@codeaurora.org</email>
</author>
<published>2016-11-18T12:28:26+00:00</published>
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<id>urn:sha1:904bb4f5c7de2f40ff31d43d3547d40910e46640</id>
<content type='text'>
Some GDSCs might support a HW control mode, where in the power
domain (gdsc) is brought in and out of low power state (while
unsued) without any SW assistance, saving power.
Such GDSCs can be configured in a HW control mode when powered on
until they are explicitly requested to be powered off by software.

Signed-off-by: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Sricharan R &lt;sricharan@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: clk-rpm: Fix clk_hw references</title>
<updated>2016-11-23T19:12:48+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>georgi.djakov@linaro.org</email>
</author>
<published>2016-11-23T14:52:49+00:00</published>
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<id>urn:sha1:c260524aba53b57f72b5446ed553080df30b4d09</id>
<content type='text'>
Fix the clk_hw references to the actual clocks and add a xlate function
to return the hw pointers from the already existing static array.

Reported-by: Michael Scott &lt;michael.scott@linaro.org&gt;
Signed-off-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: clk-smd-rpm: Fix clk_hw references</title>
<updated>2016-11-23T19:12:47+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>georgi.djakov@linaro.org</email>
</author>
<published>2016-11-23T14:52:48+00:00</published>
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<id>urn:sha1:81b7667aace061c6edd57d2fadd70374ceda2c81</id>
<content type='text'>
Fix the clk_hw references to the actual clocks and add a xlate function
to return the hw pointers from the already existing static array.

Reported-by: Michael Scott &lt;michael.scott@linaro.org&gt;
Signed-off-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops</title>
<updated>2016-11-23T19:00:06+00:00</updated>
<author>
<name>Rajendra Nayak</name>
<email>rnayak@codeaurora.org</email>
</author>
<published>2016-11-21T06:37:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=5f5001a978fc966974b136c00cfb2134edd3f2bd'/>
<id>urn:sha1:5f5001a978fc966974b136c00cfb2134edd3f2bd</id>
<content type='text'>
The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084
expects a clk_set_rate() on the sdcc rcg clk to set
a floor value of supported clk rate closest to the requested
rate, by looking up the frequency table.
So move all the sdcc rcgs on all these platforms to use the
newly introduced clk_rcg2_floor_ops

Signed-off-by: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Ritesh Harjani &lt;riteshh@codeaurora.org&gt;
Signed-off-by: Jeremy McNicoll &lt;jeremymc@redhat.com&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Add rcg ops to return floor value closest to the requested rate</title>
<updated>2016-11-23T19:00:05+00:00</updated>
<author>
<name>Rajendra Nayak</name>
<email>rnayak@codeaurora.org</email>
</author>
<published>2016-11-21T06:37:11+00:00</published>
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<id>urn:sha1:081ba80206d6b53d45ee31bc6c90871e8cfbc117</id>
<content type='text'>
The default behaviour with clk_rcg2_ops is for the
clk_round_rate()/clk_set_rate() to return/set a ceil clock
rate closest to the requested rate by looking up the corresponding
frequency table.
However, we do have some instances (mainly sdcc on various platforms)
of clients expecting a clk_set_rate() to set a floor value instead.
Add a new clk_rcg2_floor_ops to handle this for such specific
rcg instances

Signed-off-by: Rajendra Nayak &lt;rnayak@codeaurora.org&gt;
Signed-off-by: Ritesh Harjani &lt;riteshh@codeaurora.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'clk-qcom-rpm' into clk-next</title>
<updated>2016-11-11T00:50:16+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>sboyd@codeaurora.org</email>
</author>
<published>2016-11-11T00:50:16+00:00</published>
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<id>urn:sha1:81ab3279c5e1db8e61536646f1150cf66d8d5bad</id>
<content type='text'>
* clk-qcom-rpm:
  clk: qcom: Add support for RPM Clocks
  clk: qcom: Add support for SMD-RPM Clocks
  clk: qcom: Always add factor clock for xo clocks
</content>
</entry>
<entry>
<title>clk: qcom: Add support for RPM Clocks</title>
<updated>2016-11-11T00:46:56+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>georgi.djakov@linaro.org</email>
</author>
<published>2016-11-02T15:56:57+00:00</published>
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<id>urn:sha1:872f91b5ea720c72f81fb46d353c43ecb3263ffa</id>
<content type='text'>
This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_rpm driver to communicate with RPM.
Such platforms are apq8064 and msm8960.

Signed-off-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Add support for SMD-RPM Clocks</title>
<updated>2016-11-11T00:37:55+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>georgi.djakov@linaro.org</email>
</author>
<published>2016-11-02T15:56:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.etezian.org/cgit.cgi/linux.git/commit/?id=00f64b58874e14dec2b9c02f7d63147315e0a09b'/>
<id>urn:sha1:00f64b58874e14dec2b9c02f7d63147315e0a09b</id>
<content type='text'>
This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_smd_rpm driver to communicate with RPM.
Such platforms are msm8916, apq8084 and msm8974.

The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shared memory
and accepts clock requests, aggregates the requests and turns
the clocks on/off or scales them on demand.

This driver is based on the codeaurora.org driver:
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c

Signed-off-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
[sboyd@codeaurora.org: Remove useless braces for single line if]
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
<entry>
<title>clk: qcom: Always add factor clock for xo clocks</title>
<updated>2016-11-11T00:36:19+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>georgi.djakov@linaro.org</email>
</author>
<published>2016-11-02T15:56:58+00:00</published>
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<id>urn:sha1:54823af9cd529c00f0e9a9e12ea29159ac401894</id>
<content type='text'>
Currently the RPM/RPM-SMD clock drivers do not register the xo clocks,
so we should always add factor clock. When we later add xo clocks support
into the drivers, we should update this function to skip registration.
By doing so we avoid any DT dependencies.

Signed-off-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
</content>
</entry>
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