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<title>linux.git/drivers/gpu/drm/i915, branch multitile</title>
<subtitle>Linux Kernel</subtitle>
<id>https://git.etezian.org/cgit.cgi/linux.git/atom?h=multitile</id>
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<updated>2022-01-06T11:50:58+00:00</updated>
<entry>
<title>drm/i915/gt: make a gt sysfs group and move power management files</title>
<updated>2022-01-06T11:50:58+00:00</updated>
<author>
<name>Andi Shyti</name>
<email>andi.shyti@linux.intel.com</email>
</author>
<published>2020-03-23T02:25:44+00:00</published>
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<id>urn:sha1:ce5d314cdd2215ac206cf615dfa2a0e214528ef2</id>
<content type='text'>
The GT has its own properties and in sysfs they should be grouped
in the 'gt/' directory.

Create a 'gt/' directory in sysfs which will contain gt0...gtN
directories related to each tile configured in the GPU. Move the
power management files inside those directories.

The previous power management files are kept in their original
root directory to avoid breaking the ABI. They point to the tile
'0' and a warning message is printed whenever accessed to. The
deprecated interface needs for the CONFIG_SYSFS_DEPRECATED_V2
flag in order to be generated.

The new sysfs structure will have a similar layout for the 4 tile
case:

/sys/.../card0
         ├── gt
         │   ├── gt0
         │   │   ├── id
         │   │   ├── rc6_enable
         │   │   ├── rc6_residency_ms
         │   │   ├── rps_act_freq_mhz
         │   │   ├── rps_boost_freq_mhz
         │   │   ├── rps_cur_freq_mhz
         │   │   ├── rps_max_freq_mhz
         │   │   ├── rps_min_freq_mhz
         │   │   ├── rps_RP0_freq_mhz
         │   │   ├── rps_RP1_freq_mhz
         │   │   └── rps_RPn_freq_mhz
	 .   .
	 .   .
	 .   .
         │   └── gt3
         │       ├── id
         │       ├── rc6_enable
         │       ├── rc6_residency_ms
         │       ├── rps_act_freq_mhz
         │       ├── rps_boost_freq_mhz
         │       ├── rps_cur_freq_mhz
         │       ├── rps_max_freq_mhz
         │       ├── rps_min_freq_mhz
         │       ├── rps_RP0_freq_mhz
         │       ├── rps_RP1_freq_mhz
         │       └── rps_RPn_freq_mhz
         ├── gt_act_freq_mhz   -+
         ├── gt_boost_freq_mhz  |
         ├── gt_cur_freq_mhz    |    Original interface
         ├── gt_max_freq_mhz    +─-&gt; kept as existing ABI;
         ├── gt_min_freq_mhz    |    it points to gt0/
         ├── gt_RP0_freq_mhz    |
         └── gt_RP1_freq_mhz    |
         └── gt_RPn_freq_mhz   -+

Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Cc: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Cc: Sujaritha Sundaresan &lt;sujaritha.sundaresan@intel.com&gt;
Cc: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/guc: Update CT debug macro for multi-tile</title>
<updated>2022-01-06T11:50:52+00:00</updated>
<author>
<name>Michal Wajdeczko</name>
<email>michal.wajdeczko@intel.com</email>
</author>
<published>2021-10-08T21:56:33+00:00</published>
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<id>urn:sha1:cbf88fc029bdb41141c59d36448eb5e230699795</id>
<content type='text'>
Update CT debug macros by including tile ID in all messages.

Cc: Michał Winiarski &lt;michal.winiarski@intel.com&gt;
Signed-off-by: Michal Wajdeczko &lt;michal.wajdeczko@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/xehp: Make IRQ reset and postinstall multi-tile aware</title>
<updated>2022-01-06T11:50:46+00:00</updated>
<author>
<name>Paulo Zanoni</name>
<email>paulo.r.zanoni@intel.com</email>
</author>
<published>2021-10-08T21:56:32+00:00</published>
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<id>urn:sha1:58c933b72fd7bfce77d5f833f184b87ebeed6c88</id>
<content type='text'>
Loop through all the tiles when initializing and resetting interrupts.

Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/xehp: Determine which tile raised an interrupt</title>
<updated>2022-01-06T11:50:37+00:00</updated>
<author>
<name>Paulo Zanoni</name>
<email>paulo.r.zanoni@intel.com</email>
</author>
<published>2021-10-08T21:56:31+00:00</published>
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<id>urn:sha1:ee89365613084ad33059259d78cd350827950e6b</id>
<content type='text'>
The first step of interrupt handling is to read a tile0 register that
tells us in which tile the interrupt happened; we can then we read the
usual interrupt registers from the appropriate tile.

Note that this is just the first step of handling interrupts properly on
multi-tile platforms.  Subsequent patches will convert other parts of
the interrupt handling flow.

Cc: Stuart Summers &lt;stuart.summers@intel.com&gt;
Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915: Initial support for per-tile uncore</title>
<updated>2022-01-06T11:50:29+00:00</updated>
<author>
<name>Daniele Ceraolo Spurio</name>
<email>daniele.ceraolospurio@intel.com</email>
</author>
<published>2021-10-08T21:56:30+00:00</published>
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<id>urn:sha1:f56c41968d902ad1be2bce1f1259494dbbd58511</id>
<content type='text'>
Initialization and suspend/resume is replicated per-tile.

Signed-off-by: Daniele Ceraolo Spurio &lt;daniele.ceraolospurio@intel.com&gt;
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915/xehpsdv: add device info</title>
<updated>2022-01-06T11:50:13+00:00</updated>
<author>
<name>Tvrtko Ursulin</name>
<email>tvrtko.ursulin@intel.com</email>
</author>
<published>2021-11-16T19:13:57+00:00</published>
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<id>urn:sha1:cd3746336e0c589749b35c14bff74461ab50ac99</id>
<content type='text'>
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>drm/i915: Prepare for multiple gt platforms</title>
<updated>2022-01-06T11:50:07+00:00</updated>
<author>
<name>Tvrtko Ursulin</name>
<email>tvrtko.ursulin@intel.com</email>
</author>
<published>2021-10-29T03:28:10+00:00</published>
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<id>urn:sha1:a5b42292d07cc27b42cb7c31a155715465c18611</id>
<content type='text'>
On a multi-tile platform, each tile has its own registers + GGTT space,
and BAR 0 is extended to cover all of them.  Probe the tiles
individually.

Add some basic plumbing to support more than one dynamically allocated
struct intel_gt.  Up to four gts are supported in i915-&gt;gts[], with slot
zero shadowing the existing i915-&gt;gt to enable source compatibility with
legacy driver paths.  A for_each_gt macro is added to iterate over the
GTs and will be used by upcoming patches that convert various parts of
the driver to be multi-gt aware.

Check how many extra GT tiles are available on the system and setup
register access for all of them. We can detect how may GT tiles are
available by reading a register on the root tile. The same register
returns the tile ID on all tiles.

Signed-off-by: Abdiel Janulgue &lt;abdiel.janulgue@gmail.com&gt;
Signed-off-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Signed-off-by: Paulo Zanoni &lt;paulo.r.zanoni@intel.com&gt;
Signed-off-by: Daniele Ceraolo Spurio &lt;daniele.ceraolospurio@intel.com&gt;
Signed-off-by: Michal Wajdeczko &lt;michal.wajdeczko@intel.com&gt;
Signed-off-by: Venkata Sandeep Dhanalakota &lt;venkata.s.dhanalakota@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Cc: Daniele Ceraolo Spurio &lt;daniele.ceraolospurio@intel.com&gt;
Cc: Matthew Auld &lt;matthew.auld@intel.com&gt;
Cc: Joonas Lahtinen &lt;joonas.lahtinen@linux.intel.com&gt;
Cc: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Cc: Jani Nikula &lt;jani.nikula@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'drm-intel/topic/core-for-CI' into drm-tip</title>
<updated>2022-01-06T00:13:50+00:00</updated>
<author>
<name>Douglas Anderson</name>
<email>dianders@chromium.org</email>
</author>
<published>2022-01-06T00:13:50+00:00</published>
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<id>urn:sha1:f757b390faab6c38fe0887dc2123dcb615e21953</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'drm-intel/drm-intel-gt-next' into drm-tip</title>
<updated>2022-01-06T00:13:45+00:00</updated>
<author>
<name>Douglas Anderson</name>
<email>dianders@chromium.org</email>
</author>
<published>2022-01-06T00:13:45+00:00</published>
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<id>urn:sha1:443c053f51f9173042a2b45d0db7271cebe78198</id>
<content type='text'>
# Conflicts:
#	drivers/gpu/drm/i915/display/intel_fbc.c
#	drivers/gpu/drm/i915/gt/intel_gt.c
#	drivers/gpu/drm/i915/i915_driver.c
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'drm-intel/drm-intel-next' into drm-tip</title>
<updated>2022-01-06T00:13:43+00:00</updated>
<author>
<name>Douglas Anderson</name>
<email>dianders@chromium.org</email>
</author>
<published>2022-01-06T00:13:43+00:00</published>
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<content type='text'>
</content>
</entry>
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