linux.git/drivers/gpu, branch tizen/tizen

drm/exynos: dsi: Remove bridge node reference in removal

2017-02-13T23:22:16+00:00

Since bridge node is referenced during in the probe, it should be released on removal. Change-Id: I54c0759098d44eff327889e6c21d6a8e585bbb38 Suggested-by: Andrzej Hajda Signed-off-by: Hoegeun Kwon

drm/exynos/hdmi: fix PLL for 27MHz settings

2016-12-14T04:54:35+00:00

Current settings for 27MHz and 27.027MHz do not work. Use the settings from vendor code instead. Change-Id: I701555eff3fca430736664e0f628fc50d9a6dc4f Signed-off-by: Andrzej Hajda

drm/bridge/sii8620: enable interlace modes

2016-12-14T04:54:34+00:00

Bug in DECON(CRTC) driver prevented interlace modes from proper work. Since DECON is fixed interlace modes can be enabled in MHL. Change-Id: Ifdebbf921e173a1c10af36d678aa6f8e2921e74a Signed-off-by: Andrzej Hajda

drm/exynos/decon5433: do not stop DECON before reset

2016-12-14T04:54:33+00:00

DECON fails to stop in reasonable time in case of interlaced mode. But since device is reset anyway this step can be safely omitted. Change-Id: I15a78685c9573b9799ac63b7810ff3655763e461 Signed-off-by: Andrzej Hajda

drm/exynos/decon5433: fix porch calculation in interlaced mode

2016-12-14T04:54:33+00:00

Interlaced mode requires different porch calculation in DECON. Change-Id: I1bfc2554cd3204ebb270ab2e4a396d0f69f5a7f4 Signed-off-by: Andrzej Hajda

drm/exynos/decon5433: signal vblank only on odd fields

2016-12-14T04:54:32+00:00

In case of interlace mode irq is generated for odd and even fields, but vblank should be signaled only for the last emitted field. Change-Id: Icfae5a6729a0168b4f565e79825083b39cce5ca3 Signed-off-by: Andrzej Hajda

drm/bridge/sii8620: enable MHL3 mode if possible

2016-12-14T04:54:32+00:00

Since all sub-protocols of MHL3 are already supported MHL3 mode can be enabled. With this patch it is possible to use packed pixel modes and clocks up to 300MHz - 1920x1080@60Hz and 4K modes. Change-Id: I04ade01bff1af0cd0c44818bd4be45a33acf2ecd Signed-off-by: Andrzej Hajda

drm/bridge/sii8620: add HSIC initialization code

2016-12-14T04:54:31+00:00

In case of MHL3 HSIC should be initialized. Change-Id: Ieda42af182300d0f2f9c8da1bfb9f5b6a0c014ef Signed-off-by: Andrzej Hajda

drm/bridge/sii8620: improve gen2 write burst IRQ routine

2016-12-14T04:54:31+00:00

The patch adds code to report back feature complete IRQ, and code to read and drop burst writes from peer. Change-Id: I19df1e7d08c43661896aced305fe32e88b919a09 Signed-off-by: Andrzej Hajda

drm/bridge/sii8620: send EMSC features on request

2016-12-14T04:54:30+00:00

Device should report to the peer which features are really supported. Change-Id: I6aeeef9bfdf28bc38a7026f4289a89cbabd62544 Signed-off-by: Andrzej Hajda