diff options
| author | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2021-05-31 09:48:44 +0300 |
|---|---|---|
| committer | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2021-07-27 12:38:01 +0300 |
| commit | 9243b966a20b356e03c767bccabea4f4cd9e9274 (patch) | |
| tree | 9d167059f1ab8d68ffb00b50227c3ccbc67eaa7b | |
| parent | 6bdab0e5b5c0aca6f5aba952df0e4c5934547681 (diff) | |
drm/i915: Extend QGV point restrict mask to 0x3
According to BSpec there is now also a code 0x02,
which corresponds to QGV point being rejected,
this code so lets extend mask to check this.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210531064845.4389-1-stanislav.lisovskiy@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e13e913fb5c4..5d670c54e3af 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9375,7 +9375,7 @@ enum { #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8)) #define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe #define ICL_PCODE_POINTS_RESTRICTED 0x0 -#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1 +#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x3 #define GEN6_PCODE_READ_D_COMP 0x10 #define GEN6_PCODE_WRITE_D_COMP 0x11 #define ICL_PCODE_EXIT_TCCOLD 0x12 |