diff options
| author | Sharat Masetty <smasetty@codeaurora.org> | 2018-10-04 15:11:41 +0530 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2018-10-04 09:14:20 -0400 |
| commit | c28aa2031f64701d4a1a78f97147e93fc5eb0c04 (patch) | |
| tree | 4f7859b4a71ce15ca4d78255c54317055c11c0bc | |
| parent | d3fa91c90931e6f3b26f7acbac84b44c6756fa08 (diff) | |
drm/msm/a6xx: Add gmu_read64() register read op
Add a simple function to read 64 registers in the GMU domain
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index ad3bc5a77639..f34630c72c4d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -98,6 +98,16 @@ static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) gmu_write(gmu, reg, val | or); } +static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) +{ + u64 val; + + val = (u64) msm_readl(gmu->mmio + (lo << 2)); + val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32); + + return val; +} + #define gmu_poll_timeout(gmu, addr, val, cond, interval, timeout) \ readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \ interval, timeout) |