diff options
| author | Ping Gao <ping.a.gao@intel.com> | 2016-10-28 10:21:45 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2016-11-07 14:16:59 +0800 |
| commit | d4362225e8cbd4416ab08f3b4b98622b70817d6a (patch) | |
| tree | cc7a2cf928875ef0de77e2edcf113146487164c3 | |
| parent | f24940e00062f47f1e45fb20c405c2ed6bc006a3 (diff) | |
drm/i915/gvt: update misc ctl regs base on stepping info
Misc ctl related registers are for WA purpose, should detect the
stepping info first before updating HW value.
Signed-off-by: Ping Gao <ping.a.gao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/handlers.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 2d97fb78343e..bb45d5d7957c 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1278,19 +1278,20 @@ static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset, switch (offset) { case 0x4ddc: vgpu_vreg(vgpu, offset) = 0x8000003c; + /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */ + if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) + I915_WRITE(reg, vgpu_vreg(vgpu, offset)); break; case 0x42080: vgpu_vreg(vgpu, offset) = 0x8000; + /* WaCompressedResourceDisplayNewHashMode:skl */ + if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) + I915_WRITE(reg, vgpu_vreg(vgpu, offset)); break; default: return -EINVAL; } - /** - * TODO: need detect stepping info after gvt contain such information - * 0x4ddc enabled after C0, 0x42080 enabled after E0. - */ - I915_WRITE(reg, vgpu_vreg(vgpu, offset)); return 0; } |