diff options
| author | Jaehoon Chung <jh80.chung@samsung.com> | 2015-04-30 16:42:36 +0900 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:44:40 +0900 |
| commit | 36b67be6bc51d8e5e540642f1d4c81425129cd88 (patch) | |
| tree | 7500598368ee0b405133135c339465e04b94c1bd | |
| parent | dd0c58f725ee388ec1aefbf7c31df2586db384e2 (diff) | |
local/mmc: dw_mmc: exynos: dynamically adjust the SAMPLE_CLK_TUNING
This is workaround patch.
Some board doesn't work fine, when send the tuning command.
It's related with CLK_TUNING bits.
But every board doesn't work fine with same values.
(In future, needs to analysis this problem.)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| -rw-r--r-- | drivers/mmc/host/dw_mmc-exynos.c | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 90cdafcd4d48..5c9c20384d8a 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -433,8 +433,9 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv = host->priv; + const u8 clk_tuning[] = {3, 0}; u32 clksel; - u8 sample; + u8 sample, idx; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) @@ -443,14 +444,21 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) clksel = mci_readl(host, CLKSEL); sample = (clksel + 1) & 0x7; - clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample) | - SDMMC_CLKSEL_SAMPLE_CLK_TUNING(0x3) | - SDMMC_CLKSEL_CORE_CLK_TUNING(0x1); + clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) { + /* + * Workaround for Exynos5433 TM2 board. + * If other Exynos variants are not working, + * needs to set other value. + */ + idx = sample / 7; + clksel |= SDMMC_CLKSEL_SAMPLE_CLK_TUNING(clk_tuning[idx]) | + SDMMC_CLKSEL_CORE_CLK_TUNING(0x1); + mci_writel(host, CLKSEL64, clksel); - else + } else mci_writel(host, CLKSEL, clksel); return sample; |