diff options
| author | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2016-02-22 11:43:39 +0000 |
|---|---|---|
| committer | Sasha Levin <sasha.levin@oracle.com> | 2016-07-10 23:07:17 -0400 |
| commit | 5356deeafda4e139a44f6f82a99439d93a7b84cf (patch) | |
| tree | b8538a3b54c23e10df88629c0651b2b27aa2517a | |
| parent | ea0b24134918a838f1ff94ac4707d3dcc637630c (diff) | |
clk: qcom: msm8960: fix ce3_core clk enable register
[ Upstream commit 732d6913691848db9fabaa6a25b4d6fad10ddccf ]
This patch corrects the enable register offset which is actually 0x36cc
instead of 0x36c4
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Fixes: 5f775498bdc4 ("clk: qcom: Fully support apq8064 global clock control")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
| -rw-r--r-- | drivers/clk/qcom/gcc-msm8960.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c index eb6a4f9fa107..9ce658ae72b7 100644 --- a/drivers/clk/qcom/gcc-msm8960.c +++ b/drivers/clk/qcom/gcc-msm8960.c @@ -2769,7 +2769,7 @@ static struct clk_branch ce3_core_clk = { .halt_reg = 0x2fdc, .halt_bit = 5, .clkr = { - .enable_reg = 0x36c4, + .enable_reg = 0x36cc, .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "ce3_core_clk", |