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authorMarek Szyprowski <m.szyprowski@samsung.com>2016-05-19 12:15:23 +0200
committerSeung-Woo Kim <sw0312.kim@samsung.com>2016-12-14 13:50:42 +0900
commit5b62dd3472f8e4e75a2efd65324f4f17d755e20a (patch)
treeb2e056690a21c4781ac30d17eb5a86f7e6a8c24f
parent950296ac28380d0b6c7b5b4ea0dd890f205c86a3 (diff)
Revert "drm/exynos: gsc: always use hw buffer 0 until queue management get fixed"
This reverts commit 937b633eebe825aad14181b168c5b79eccad833d. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Change-Id: I488bb9ee60e0fe8e711b9c116b04483ac99a66e8
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_gsc.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
index 70a2b5edcb1d..6adafba9f40f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -852,16 +852,16 @@ static int gsc_src_set_addr(struct device *dev,
}
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
- GSC_IN_BASE_ADDR_Y(0));
+ GSC_IN_BASE_ADDR_Y(buf_id));
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
- GSC_IN_BASE_ADDR_CB(0));
+ GSC_IN_BASE_ADDR_CB(buf_id));
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
- GSC_IN_BASE_ADDR_CR(0));
+ GSC_IN_BASE_ADDR_CR(buf_id));
break;
case IPP_BUF_DEQUEUE:
- gsc_write(0x0, GSC_IN_BASE_ADDR_Y(0));
- gsc_write(0x0, GSC_IN_BASE_ADDR_CB(0));
- gsc_write(0x0, GSC_IN_BASE_ADDR_CR(0));
+ gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));
+ gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));
+ gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));
break;
default:
/* bypass */
@@ -1317,16 +1317,16 @@ static int gsc_dst_set_addr(struct device *dev,
}
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
- GSC_OUT_BASE_ADDR_Y(0));
+ GSC_OUT_BASE_ADDR_Y(buf_id));
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
- GSC_OUT_BASE_ADDR_CB(0));
+ GSC_OUT_BASE_ADDR_CB(buf_id));
gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
- GSC_OUT_BASE_ADDR_CR(0));
+ GSC_OUT_BASE_ADDR_CR(buf_id));
break;
case IPP_BUF_DEQUEUE:
- gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(0));
- gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(0));
- gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(0));
+ gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));
+ gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));
+ gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));
break;
default:
/* bypass */