diff options
| author | Marek Szyprowski <m.szyprowski@samsung.com> | 2015-09-01 11:22:18 +0200 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:50:34 +0900 |
| commit | 77d83016100c1433255e6351b54d0ba7cf241dea (patch) | |
| tree | 7b8cc41980b394165e59259b7adb9a5d7473bd02 | |
| parent | 5d36736404a5802d9478ca3e38808e86af6875a2 (diff) | |
clk: samsung: exynos5422: add missing parent GSCL block clocks
This patch adds clocks, which are required for preserving parent clock
configuration on GSCALLER power domain on/off.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 8 | ||||
| -rw-r--r-- | include/dt-bindings/clock/exynos5420.h | 2 |
2 files changed, 6 insertions, 4 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 03cdea4f3789..bb43ed29260a 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -681,8 +681,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP5, 20, 1), MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1), - MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p, - SRC_TOP5, 28, 1), + MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl", + mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1), MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), @@ -733,8 +733,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { SRC_TOP12, 20, 1), MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1), - MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p, - SRC_TOP12, 28, 1), + MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl", + mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1), /* DISP1 Block */ MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3), diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index dde96643e585..7699ee9c16c0 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -212,6 +212,8 @@ #define CLK_MOUT_SW_ACLK300 649 #define CLK_MOUT_USER_ACLK400_DISP1 650 #define CLK_MOUT_SW_ACLK400 651 +#define CLK_MOUT_USER_ACLK300_GSCL 652 +#define CLK_MOUT_SW_ACLK300_GSCL 653 /* divider clocks */ #define CLK_DOUT_PIXEL 768 |