diff options
| author | Andrzej Hajda <a.hajda@samsung.com> | 2015-04-03 15:20:52 +0200 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:45:48 +0900 |
| commit | 938ba05a98cdae34fc5d27954e1b49a201800f34 (patch) | |
| tree | 11c0b8cb27bee4223cbd7799ffe23efabc1c4119 | |
| parent | 4f9beed858c48972fa30b836a61a07ae88931394 (diff) | |
clk: exynos5433: add defines for HDMI-PHY output clocks
HDMI driver must re-parent respective muxes during HDMI-PHY on/off to
HDMI-PHY output clocks. To reference those clocks their defines should be added.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 6 | ||||
| -rw-r--r-- | include/dt-bindings/clock/exynos5433.h | 5 |
2 files changed, 8 insertions, 3 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index bd2cd3ce88ae..2c2ac75a5ae5 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -2735,8 +2735,10 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] __initdata = { FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT, 100000000), /* PHY clocks from HDMI_PHY */ - FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 300000000), - FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 166000000), + FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", + NULL, CLK_IS_ROOT, 300000000), + FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy", + NULL, CLK_IS_ROOT, 166000000), }; static struct samsung_mux_clock disp_mux_clks[] __initdata = { diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index ca61ceb793d2..5e395dab336f 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -767,7 +767,10 @@ #define CLK_SCLK_RGB_VCLK 109 #define CLK_SCLK_RGB_TV_VCLK 110 -#define DISP_NR_CLK 111 +#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111 +#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112 + +#define DISP_NR_CLK 113 /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1 |