diff options
| author | Jaehoon Chung <jh80.chung@samsung.com> | 2015-04-29 15:44:35 +0900 |
|---|---|---|
| committer | Seung-Woo Kim <sw0312.kim@samsung.com> | 2016-12-14 13:44:23 +0900 |
| commit | af5e231b9a7f7dc231c1df51376caa52e07371e6 (patch) | |
| tree | 33af7628122dfd6614a860d53dbc79573a4d1d6d | |
| parent | 3bc56086fc25f6d06ffc6d050cb6fc9724056aad (diff) | |
local/mmc: dw_mmc: exynos: use the bits relevant to clock tuning
There are bits relevant to clock tuning at CLKSEL register.
BIT[31:30] - CORE_CLK_TUNING
BIT[23:22] - DRV_CLK_TUNING
BIT[7:6] - SAMPLE_CLK_TUNING
These bits should be affected when card is tuning.
(In future, need to find the optimal values.)
At now, it used temporary these values.
(CORE_CLK_TUNING - 0x3, SAMPLE_CLK_TUNING - 0x1)
After sampling clock, these value have to set to 0.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
| -rw-r--r-- | drivers/mmc/host/dw_mmc-exynos.c | 7 | ||||
| -rw-r--r-- | drivers/mmc/host/dw_mmc-exynos.h | 10 |
2 files changed, 14 insertions, 3 deletions
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 6b5843279348..90cdafcd4d48 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -139,7 +139,8 @@ static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing) else clksel = mci_readl(host, CLKSEL); - clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; + clksel = (clksel & ~(SDMMC_CLKSEL_TIMING_MASK | + SDMMC_CLKSEL_TUNING_MASK)) | timing; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) @@ -420,6 +421,7 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample) clksel = mci_readl(host, CLKSEL64); else clksel = mci_readl(host, CLKSEL); + clksel &= ~SDMMC_CLKSEL_TUNING_MASK; clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) @@ -442,7 +444,8 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) sample = (clksel + 1) & 0x7; clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample) | - SDMMC_CLKSEL_SAMPLE_CLK_TUNING(0x3); + SDMMC_CLKSEL_SAMPLE_CLK_TUNING(0x3) | + SDMMC_CLKSEL_CORE_CLK_TUNING(0x1); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h index 588ec167c7ea..3b144609f096 100644 --- a/drivers/mmc/host/dw_mmc-exynos.h +++ b/drivers/mmc/host/dw_mmc-exynos.h @@ -34,7 +34,15 @@ SDMMC_CLKSEL_CCLK_DRIVE(y) | \ SDMMC_CLKSEL_CCLK_DIVIDER(z)) #define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7) -#define SDMMC_CLKSEL_SAMPLE_CLK_TUNING(x) ((x) << 6) +#define SDMMC_CLKSEL_SAMPLE_CLK_TUNING(x) (((x) & 0x3) << 6) +#define SDMMC_CLKSEL_SAMPLE_CLK_TUNING_MASK (0x3 << 6) +#define SDMMC_CLKSEL_DRV_CLK_TUNING(x) (((x) & 0x3) << 22) +#define SDMMC_CLKSEL_DRV_CLK_TUNING_MASK (0x3 << 22) +#define SDMMC_CLKSEL_CORE_CLK_TUNING(x) (((x) & 0x3) << 30) +#define SDMMC_CLKSEL_CORE_CLK_TUNING_MASK (0x3 << 30) +#define SDMMC_CLKSEL_TUNING_MASK (SDMMC_CLKSEL_CORE_CLK_TUNING_MASK | \ + SDMMC_CLKSEL_DRV_CLK_TUNING_MASK | \ + SDMMC_CLKSEL_SAMPLE_CLK_TUNING_MASK) #define SDMMC_CLKSEL_WAKEUP_INT BIT(11) /* RCLK_EN register defines */ |